CN1685504A - 包含漏极夹的半导体管芯封装 - Google Patents

包含漏极夹的半导体管芯封装 Download PDF

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CN1685504A
CN1685504A CNA038232154A CN03823215A CN1685504A CN 1685504 A CN1685504 A CN 1685504A CN A038232154 A CNA038232154 A CN A038232154A CN 03823215 A CN03823215 A CN 03823215A CN 1685504 A CN1685504 A CN 1685504A
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lead
drain
source
semiconductor die
moulding material
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CN100362656C (zh
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R·玛德里德
M·C·Y·坤恩纳斯
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Fairchild Semiconductor Corp
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Fairchild Semiconductor Corp
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Abstract

一种半导体管芯封装(100)包括半导体管芯(108)，它包括第一表面、第二表面和垂直功率MOSFET，该垂直功率MOSFET的栅极区和源极区位于第一表面而漏极区位于第二表面。具有主表面(101(a))的漏极夹(101)电气耦合到漏极区。栅极引线(112)电气耦合到栅极区。源极引线(111)电气耦合到源极区。非导电模制材料(102)密封半导体管芯(108)。漏极夹(101)的主表面(101(a))通过非导电模制材料(102)而暴露。

Description

包含漏极夹的半导体管芯封装
发明背景
存在许多半导体管芯封装。在半导体管芯封装的一个实例中，半导体管芯用引线安装于引线框架。线路将半导体管芯耦合到引线。接着，线路、半导体管芯以及随后的多数引线框架(除向外延伸的引线)被密封于模制材料中。随后，使模制材料成形。所形成的半导体管芯封装包括具有侧向延伸离开模制体的引线的模制体。半导体管芯封装可安装到电路板上。
虽然这种半导体封装是有用的，但可进行改良。例如，期望半导体管芯封装的厚度减小。随消费电子产品(例如，蜂窝电话、膝上计算机等)继续减小尺寸，越发需要更薄的电子器件以及更薄的电子部件。此外，期望改善半导体管芯封装的散热属性。例如，诸如垂直MOSFET(金属氧化物场效应晶体管)的功率半导体器件会产生显著的热量。对于高输出功率应用(例如，超过60瓦)，需要特殊封装用于除去功率晶体管的热量以避免过热。过热还会劣化功率晶体管的操作属性。
本发明的实施例单独和共同地解决了这些和其它问题。
发明内容
本发明的实施例针对半导体管芯封装和用于制造半导体管芯封装的方法。
本发明的一个实施例针对一种半导体管芯封装，它包括：(a)半导体管芯，它包括第一表面、第二表面和垂直功率MOSFET，该垂直功率MOSFET的栅极区和源极区位于第一表面而漏极区位于第二表面；(b)漏极夹，它具有主表面并电气耦合到漏极区；(c)栅极引线，它电气耦合到栅极区；(d)源极引线，它电气耦合到源极区；以及(e)非导电模制材料，它密封半导体管芯，其中漏极夹的主表面通过非导电模制材料而暴露。
本发明的另一个实施例针对一种半导体管芯封装，它包括：(a)半导体管芯，它包括第一表面、第二表面和垂直功率MOSFET，该垂直功率MOSFET的栅极区和源极区位于第一表面而漏极区位于第二表面；(b)漏极夹，它具有主表面并电气耦合到漏极区；(c)漏极引线，它电气耦合到漏极夹的一端；(d)栅极引线，它电气耦合到栅极区；(e)源极引线结构，它包括至少一个源极引线和含主表面的突出区，以及与源极引线结构的主表面相对的管芯附着表面，该管芯附着表面电气耦合到源极区；以及(f)非导电模制材料，它密封半导体管芯，其中漏极夹的主表面通过非导电模制材料而暴露。
本发明的另一个实施例针对一种用于制造半导体管芯封装的方法，该方法包括：(a)提供含第一表面、第二表面和垂直功率MOSFET的半导体管芯，其中垂直功率MOSFET的栅极区和源极区位于第一表面而漏极区位于第二表面；(b)将源极引线结构附着到源极区并将栅极引线附着到栅极区；(c)将含主表面的漏极夹附着到漏极区；(d)将模制材料模制于半导体管芯周围；从而主表面通过模制材料暴露。
以下将详细描述本发明的这些和其它实施例。
附图概述
图1示出了半导体管芯封装的透视图。通过封装的上侧暴露漏极夹的主表面且该主表面平行于模制材料的表面。
图2示出了半导体管芯封装的透视底视图。源极引线结构的主表面、栅极引线的表面以及源极引线的表面通过模制材料暴露。
图3示出半导体管芯封装的透视三维示图，其中部分地除去部分模制材料示出模制的装配部分。
图4示出半导体管芯封装的透视三维示图，其中部分地除去部分模制材料示出模制的装配部分。
图5示出了根据本发明实施例的半导体管芯封装的侧剖视图。
图6示出漏极引线、源极引线结构以及栅极引线。
图7示出了半导体管芯封装的分解图。
图8示出根据本发明实施例用于制造半导体管芯封装的实例性方法的框图。
具体实施方式
本发明的实施例涉及半导体管芯封装。它们可以按任何合适的方式制成。例如，在某些实施例中，可将其前侧上具有焊料凸起的半导体管芯颠倒并附着到引线框架上。引线框架可以是铜引线框架。在某些实施例中，凸起的半导体管芯包括一个或多个栅极焊料凸起和源极焊料凸起。栅极焊料凸起可附着到引线框架的隔离的栅极引线结构上，同时源极焊料凸起可附着到引线框架中的一个或多个源极引线结构上。栅极和源极引线结构最终形成用于半导体管芯中的MOSFET的栅极和源极连接。
与MOSFET的漏极区相对应的半导体管芯背侧电气耦合到漏极夹(drainclip)。漏极夹可使用焊料糊附着到半导体管芯的背侧。漏极夹将半导体管芯的背侧互连到包含漏极引线的漏极引线结构。焊料糊(例如，焊料糊合金)可用于将漏极夹电气连接到漏极引线结构。漏极夹、焊料和漏极引线结构可提供从半导体管芯的背侧到半导体管芯的前侧的漏极连接。
半导体管芯封装中的源极引线结构包括具有主表面的突出部分。源极引线结构的源极引线、栅极引线结构的栅极引线以及源极引线结构的主表面通过模制材料暴露。这些表面位于相同平面内并也可以与漏极引线结构中的漏极引线的表面共面。在半导体管芯的相对侧处，漏极夹的主表面通过模制材料暴露。
本发明的实施例具有许多优点。首先根据本发明实施例的半导体管芯封装具有较低的整体封装电阻(即，较低的RdSon)。在本发明的实施例中，半导体管芯中的漏极区电气耦合到漏极夹，且漏极夹用漏极引线电气连接到漏极引线结构。源极引线结构和栅极引线结构可分别耦合到半导体管芯中的源极区和栅极区。对半导体管芯中的栅极、源极和漏极区进行基本直接的电气连接，这减小了整体封装电阻。其次，该半导体管芯封装可容纳较大的半导体管芯，或者较小的半导体管芯(例如，达4密耳厚)同时提供可靠的互连。第三，本发明的实施例较薄。例如，在本发明的实施例中，半导体管芯封装可以薄至0.75mm或以下。第四，本发明的实施例还呈现改良的热性能。可以实现改良的热性能，因为漏极夹被暴露并与半导体管芯封装中模制材料的表面相共面。这提供了半导体管芯封装中的自然散热片。此外，在本发明的实施例中，源极和漏极在一个装配过程中从封装的上部和下部同时暴露。漏极夹和源极引线结构的暴露的主表面可用作自然冷却装置，以便在工作时冷却半导体管芯。第五，本发明的实施例还可以大批量地制造。倒装芯片、引线框架、漏极夹和模制材料可用于本发明的实施例中以有助于较高的产量。
图1-7说明了本发明的实施例。图1-7中，相同数字表示相同元件。
图1是根据本发明实施例的半导体管芯封装100的顶透视图。半导体管芯封装100包括漏极夹101和模制于漏极夹101周围的模制材料102。如图1所示，漏极夹101的主表面101(a)经过模制材料102暴露。模制材料102可包括本领域中已知的任何合适的可模制介质材料。
模制材料102保护封装100内的半导体管芯(未示出)不受任何来自周围环境的污染或侵蚀。在本发明的实施例中，首先将模制材料102模制，随后成形。在模制后，模制材料102可被锯掉并与其它半导体管芯封装分开，以使所形成的半导体管芯封装是块状的。或者，可单独将模制材料102模制而不进行锯切。
半导体管芯108可包括任何合适的半导体器件。合适器件包括垂直功率晶体管。垂直功率晶体管包括VDMOS晶体管。VDMOS晶体管是含有通过扩散形成的两个或更多半导体区域的MOSFET。它具有源极区、漏极区以及栅极区。器件是垂直的，其中源极区和漏极区处于半导体管芯的相对表面处。栅极区可以是开槽栅极结构或者平面栅极结构，并形成于与源极区相同的表面处。开槽栅极结构是优选的，因为与平面栅极结构相比开槽的栅极结构更窄并占据更少的空间。在操作期间，在VDMOS器件中从源极区流到漏极区的电流基本垂直于管芯表面。在本发明的实施例中，半导体管芯的前侧可以包括源极区和栅极区，而半导体管芯的背侧可以包括漏极区。
图2示出半导体管芯封装100的下部。半导体管芯封装100包括漏极引线107。在所示的实施例中，漏极引线107同栅极引线112和源极引线111位于半导体管芯封装100的相对侧处。源极引线结构103的主表面103(a)通过模制材料102暴露。漏极引线107也通过模制材料102暴露。如图2所示，漏极引线107、栅极引线112和源极引线111不延伸超过模制材料102的侧表面。这形成更加紧凑的半导体管芯封装。
系杆区106位于源极和栅极引线111、112以及漏极引线107之间。在未切系杆区106时，系杆区106将包含源极和栅极引线111、112以及漏极引线107的引线框架连接到引线框架阵列中的其它引线框架。在封装装配之前和期间，系杆区106用于支持引线框架。
图3示出根据本发明实施例的半导体管芯封装100的装配切开顶视图。将半导体管芯108附着到源极引线结构103的管芯附着表面109。源极引线结构103也包括系杆区106。具有栅极引线112的栅极引线结构171通过焊料凸起141附着到半导体管芯108的栅极区(未示出)。漏极夹101通过焊料层(未示出)附着到半导体管芯108上。漏极夹101具有主表面101(a)。包含漏极引线107的漏极引线结构177也通过焊料层附着到漏极夹101。源极引线111被示作在半导体管芯封装100的一侧处露出。
图4示出半导体管芯封装100的装配切开底视图。下部切开部分示出源极引线结构103的暴露的主表面103(a)。主表面103(a)可直接耦合到印刷电路板(PCB)(未示出)。漏极引线107的表面被示作与源极引线111和栅极引线112的表面以及主表面103(a)共面。
如图4所示，主表面103(a)是从相邻表面113突出的源极引线103的突出部分的一部分。相邻表面113可通过蚀刻形成。在图4所示的实施例中，用于形成栅极引线结构和源极引线结构的引线框架被部分蚀刻(例如，半蚀刻)以允许模制材料在模制期间流动。部分蚀刻的区域为模制化合物提供足够区域以流动和完整地保持装配的管芯封装并在模制后加以保护。可使用本领域已知的光刻法和蚀刻工艺进行部分蚀刻。例如，形成图案的光阻材料层可形成于引线框架的所需区域上。随后，可(例如，使用湿法或干法蚀刻)将引线框架蚀刻到预定深度，从而在某些区域中部分蚀刻引线框架。
图5示出根据本发明实施例的半导体管芯封装的侧剖视图。如图5所示，漏极夹101被弯曲约45度角并具有弯曲部分117。该漏极夹101用一层低共熔焊料糊116电气耦合到半导体管芯108的背侧。漏极夹101具有通过模制材料102暴露的主表面。漏极夹101与漏极引线结构177电气耦合，该漏极引线结构177具有与漏极夹101的主要部分形成V形的弯曲部分120。低共熔焊料糊118将漏极夹101连接到漏极引线结构120。漏极引线结构120在标号119处被部分蚀刻以允许漏极夹101的弯曲。源极引线结构103的下部也包括部分蚀刻区113。部分蚀刻的源极引线结构103的用途是允许模制材料流动和完整地保持半导体管芯封装100并加以保护。通过标号104、107示出半导体管芯封装100的足印。倒装芯片焊料凸起115和回流的焊料糊114将源极引线结构103和半导体管芯108电气耦合在一起。
图6示出引线框架结构的详细设计。隔离的栅极引线112被部分蚀刻以提供足够的区域以便模制材料流到其上。源极引线111基本与源极引线结构103的主表面103(a)共面并也可以使用部分蚀刻工艺形成。引线框架的下部分在设置相邻表面113的区域处被部分蚀刻。部分蚀刻的区域将允许模制材料在模制期间流动。漏极引线结构177具有漏极引线107和弯曲部分120。弯曲部分120是漏极引线结构177耦合到漏极夹(未示出)的位置。漏极引线107也可通过部分蚀刻形成。
图7示出了根据本发明实施例的半导体管芯封装的分解示图。在最终装配中示出模制材料102，它一起保持半导体管芯封装中的各种其它部件。如图所示，金属化的漏极引线结构177和源极引线结构103用作半导体管芯封装的漏极和源极端子。如图7所示，半导体管芯108用焊料凸起且这直接附着到源极引线结构103。漏极夹101可以是成形的铜片，它将半导体管芯108的漏极区连接到漏极引线结构177。漏极夹101的端部被弯曲45度角以匹配漏极引线结构177的角度弯曲。漏极引线结构177和漏极夹101的有角部分使用焊料糊电气耦合。虽然以上描述了45度的弯曲角，但可以理解，漏极引线结构177和漏极夹101可以具有任何合适大小的弯曲角。
根据本发明实施例的半导体管芯封装可以是任何合适的尺寸。例如，封装尺寸可小于2×2mm2或者可以大于20×20mm2。较佳地，根据本发明实施例的半导体管芯封装优选实际上是立方的。它们有时可称作“倒装芯片四方包(flip chip quadpacks)”。
可根据任何合适的方法制造根据本发明实施例的半导体管芯封装。在某些实施例中，方法包括提供包括第一表面、第二表面和垂直功率MOSFET的半导体管芯，其中垂直功率MOSFET的栅极区和源极区在第一表面处而漏极区在第二表面处。随后，源极引线结构被附着到源极区而栅极引线被附着到栅极区。含主表面的漏极夹也附着到漏极区。模制材料被模制于半导体管芯周围，从而通过模制材料暴露主表面。
图8示出实例性的过程流程。如图8所示，具有焊料凸起的半导体管芯使用倒装芯片管芯附着工艺被附着到半导体管芯封装中的引线框架(包括将成为源极引线结构、栅极引线结构以及漏极引线结构的部分)(步骤302)。引线框架可以在引线框架阵列中。在焊料凸起附着前，引线框架可以在所需区域中被部分蚀刻(如上所述)，且可以弯曲引线框架中的一部分漏极引线结构。随后，执行红外线(IR)回流工艺(步骤304)以回流焊料凸起并建立半导体管芯和源极引线结构之间的电气连接。
随后，将漏极夹结合到半导体管芯(步骤306)。漏极夹和/或半导体管芯可包含一层焊料或一焊料凸起阵列。漏极夹也可用焊料结合到引线框架中的漏极引线结构。漏极夹也可用焊料结合到漏极引线结构。这些部件随后被结合在一起，且焊料可经过回流处理(步骤308)。
接着，可使用膜辅助模制过程将模制材料模制于半导体管芯、引线框架结构和漏极夹周围。例如，膜可以是带接到漏极夹的主表面上的一片带。该带防止模制材料沉积于漏极夹的主表面上。在带位于漏极夹上时，模制材料可以模制于半导体管芯、漏极夹和引线框架结构的周围。可将多余的模制材料从与漏极夹相对的半导体管芯的侧部移除。喷水去毛刺工艺(步骤312)可用于除去多余的模制材料(例如，在栅极引线结构上)。接着，使模制材料硬化。在模制和去毛刺后，除去带。
激光标记工艺可用于标记所形成的产品(步骤314)。将引线框架与其它引线框架保持在一起的系杆(也连接到源极引线、栅极引线和漏极引线)锯切，使阵列中的封装单个化(步骤316)。单个化后封装的最终形状因素可以是正方形的，其中所有侧边都具有模制材料边缘内的引线。随后，可以测试单个半导体管芯封装(步骤318)。
这里所采用的术语和表达用作描述术语而非限制，且不期望这种术语和表达的使用排除所示和所描述的特点或其一部分的等效物，可以理解，所要求的本发明内的各种修改都是可以的。例如，上述许多实施例都包括作为分离元件的漏极夹和漏极引线结构。在其它实施例中，漏极夹可包括漏极引线，从而在其它实施例中分开的漏极引线结构是不必要的。

Claims (13)

1.一种半导体管芯封装，其特征在于，包括：
(a)半导体管芯，它包括第一表面、第二表面和垂直功率MOSFET，该垂直功率MOSFET的栅极区和源极区位于第一表面而漏极区位于第二表面；
(b)漏极夹，它具有主表面并电气耦合到漏极区；
(c)栅极引线，它电气耦合到栅极区；
(d)源极引线，它电气耦合到源极区；以及
(e)非导电模制材料，它密封半导体管芯，其中漏极夹的主表面通过非导电模制材料而暴露。
2.如权利要求1所述的半导体管芯封装，其特征在于，进一步包括漏极引线，它电气耦合到漏极夹的一端，其中漏极引线的至少一个表面基本与栅极引线的表面以及源极引线的表面共面。
3.如权利要求1所述的半导体管芯封装，其特征在于，模制材料具有上表面和下表面，其中上表面基本与漏极夹的主表面共面，其中下表面基本与栅极引线的表面和源极引线的表面共面。
4.如权利要求1所述的半导体管芯封装，其特征在于，源极引线结构包括管芯附着垫，其中半导体管芯附着到该管芯附着垫上。
5.如权利要求1所述的半导体管芯封装，其特征在于，源极引线是具有主表面的源极引线结构的一部分，其中模制材料具有上表面和下表面，其中上表面基本与漏极夹的主表面共面且下表面基本与栅极引线的表面、源极引线的表面以及源极引线结构的主表面共面，且其中源极引线结构的主表面和漏极夹的主表面形成半导体管芯封装的外部表面。
6.一种半导体管芯封装，其特征在于，包括：
(a)半导体管芯，它包括第一表面、第二表面和垂直功率MOSFET，该垂直功率MOSFET的栅极区和源极区位于第一表面而漏极区位于第二表面；
(b)漏极夹，它具有主表面并电气耦合到漏极区；
(c)漏极引线，它电气耦合到漏极夹的一端；
(d)栅极引线，它电气耦合到栅极区；
(e)源极引线结构，它包括至少一个源极引线和含主表面的突出区，以及与源极引线结构的主表面相对的管芯附着表面，该管芯附着表面电气耦合到源极区；以及
(f)非导电模制材料，它密封半导体管芯，其中漏极夹的主表面通过非导电模制材料而暴露。
7.如权利要求6所述的半导体管芯，其特征在于，栅极引线的表面、源极引线的表面和源极引线结构的主表面基本共面并通过模制材料暴露。
8.如权利要求6所述的半导体管芯，其特征在于，漏极夹包括铜。
9.一种用于制造半导体管芯封装的方法，其特征在于，该方法包括：
(a)提供含第一表面、第二表面和垂直功率MOSFET的半导体管芯，其中垂直功率MOSFET的栅极区和源极区位于第一表面而漏极区位于第二表面；
(b)将源极引线结构附着到源极区并将栅极引线附着到栅极区；
(c)将含主表面的漏极夹附着到漏极区；
(d)将模制材料模制于半导体管芯周围；从而主表面通过模制材料暴露。
10.如权利要求9所述的方法，其特征在于，在(b)中，源极引线是源极引线结构的一部分且源极引线结构和栅极引线是引线框架结构的一部分。
11.如权利要求9所述的方法，其特征在于，源极引线结构包括管芯附着表面。
12.如权利要求11所述的方法，其特征在于，通过蚀刻管芯附着表面周围的区域形成源极引线结构。
13.如权利要求9所述的方法，其特征在于，进一步包括使用焊料将漏极引线附着到漏极夹上。
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