CN1669160A - 自对准纳米管场效应晶体管及其制造方法 - Google Patents

自对准纳米管场效应晶体管及其制造方法 Download PDF

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CN1669160A
CN1669160A CNA038062925A CN03806292A CN1669160A CN 1669160 A CN1669160 A CN 1669160A CN A038062925 A CNA038062925 A CN A038062925A CN 03806292 A CN03806292 A CN 03806292A CN 1669160 A CN1669160 A CN 1669160A
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effect transistor
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乔尔格·阿彭泽勒
佩登·阿沃里斯
凯文·K·钱
菲利普·G·科林斯
理查德·马特尔
汉森·P·黄
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Core Usa Second LLC
GlobalFoundries Inc
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Abstract

一种自对准碳纳米管场效应晶体管半导体器件，包括沉积在衬底(102)上的碳纳米管(104)、分别形成在该碳纳米管(104)的第一端和第二端的源极和漏极(106－107)、以及基本形成在该碳纳米管(104)的一部分上并通过介电膜(111)与该碳纳米管隔开的栅极(112)。

Description

自对准纳米管场效应晶体管及其制造方法
技术领域
本发明涉及场效应晶体管，并且更加特别地涉及碳纳米管场效应晶体管。
背景技术
在分子纳米电子(molecular nanoelectronics)领域，很少有材料表现得如纳米管一般充满希望，特别是碳纳米管，其包括埃量级直径的石墨中空圆筒。依赖纳米管的电学特性，纳米管可以应用于诸如二极管和晶体管的电子器件中。纳米管的尺寸、形状和物理性质是独特的。结构上，碳纳米管类似于卷成圆筒的碳六角形点阵。
除了在低温下展现出引人注目的量子行为以外，碳纳米管还表现出至少两种重要特性：根据其空间螺旋特性(即构象几何)，纳米管可以是金属性的或半导体性的。金属性的纳米管可以以固定的电阻率承载极大的电流密度。半导体性的纳米管可以如场效应晶体管(FET)般电导通和截止。这两种类型可以共价结合(共享电子)。这些特性指出了纳米管是用于制造纳米尺寸半导体电路的优良材料。
另外，碳纳米管是一维电学导体，即仅以一维量子力学模式承载电流。对于碳纳米管基晶体管的器件性能，这可以成为明显的优点，因为材料中的散射得到明显抑制。更少的散射意味着更好的器件性能。
对于三端器件，诸如FET，栅极(第三端子)需要与电性有源沟道区以及源极和漏极隔离开。为此，可以使用介电材料，例如二氧化硅。为了改善硅器件中的器件特性，可以减小这一层的厚度。这种减小增加了栅极电容并改善了栅极与沟道的耦合。对于标准的硅场效应器件，栅极电容的大小与介电膜的厚度成反比。对于目前制造的高性能处理器，SiO2的厚度小于4nm。值得注意的是，很难实现进一步的减小，因为通过介电膜的栅极泄漏对于厚度在4nm以下的氧化物成指数形式增大。
然而，碳纳米管晶体管的栅极电容并不与介电膜的厚度成反比。相反，碳纳米管遵循对数比例的规则。与标准的硅场效应晶体管相比，碳纳米管晶体管的栅极电容可以更大，应为这些对象的圆筒形几何形状。
尚无已知的系统或方法在FET中应用纳米管以获得性能和更小的尺寸。因此，需要制备纳米管基FET的系统及方法。
发明内容
根据本发明一实施例，提供一种自对准碳纳米管场效应晶体管半导体器件。该器件包括沉积在衬底上的碳纳米管、形成在该碳纳米管第一端和第二端处的源极和漏极、以及基本(substantially)形成在该碳纳米管的一部分上并通过介电膜与该碳纳米管分开的栅极。
该衬底包括沉积在硅衬底上的热氧化物。该热氧化物约150纳米厚。
该栅极还通过氧化层与该碳纳米管分开。该栅极的一部分通过氮化物间隔壁与该源极和漏极分开。
该器件还包括器件上的钝化介电层。
该器件包括衬底中的对准标记，该源极和漏极与该对准标记对准。
该栅极包围(wrap)该介电膜和该碳纳米管，从而与该碳纳米管的背侧接触。
根据本发明一实施例，提供一种碳纳米管场效应晶体管半导体器件。该器件包括被包围在介电材料中的垂直碳纳米管、分别形成在该碳纳米管的第一侧和第二侧上的源极和漏极、通过其形成每个该源极和漏极的连接带(bandstrap)从而将包围在介电材料中的该碳纳米管连接至该源极和漏极的双层氮化物复合体(bilayer nitride complex)、以及基本形成在该碳纳米管的一部分上的栅极。
该器件包括碳纳米管基部处的金属催化剂。
根据本发明的一个实施例，提供一种用于形成自对准碳纳米管场效应晶体管半导体器件的方法。该方法包括：在热氧化物衬底上沉积纳米管，其中该衬底包括对准标记；在该纳米管的每个端部处形成金属触点，其中第一金属触点为源极而第二金属触点为漏极；以及在该器件上沉积非晶硅层。该方法还包括：在每个金属触点的相对侧面上形成氮化物间隔壁；在该器件上沉积高k介电膜；氧化该非晶硅；以及基本在该源极与漏极之间、并且在该纳米管上方形成栅极。
该方法包括在该器件上沉积钝化电介质。
该纳米管为单壁纳米管。该金属触点使用光致抗蚀剂形成。
根据本发明一实施例，提供一种用于形成自对准碳纳米管场效应晶体管半导体器件的方法。该方法包括：在热氧化物衬底上沉积纳米管，其中该衬底包括对准标记；通过反应离子蚀刻在纳米管的每个端部处形成金属触点，其中第一金属触点为源极而第二金属触点为漏极；以及在每个金属触点的相对侧面上形成氮化物间隔壁。该方法还包括：在该器件上沉积高k介电膜；以及基本在该源极与漏极之间、且在该纳米管上方形成栅极。
该方法包括在该器件上沉积钝化电介质。
根据本发明一实施例，提供一种用于形成自对准碳纳米管场效应晶体管半导体器件的方法。该方法包括：在热氧化物衬底上沉积纳米管，其中该衬底包括对准标记；以及在该纳米管的每个端部上形成非晶硅柱。该方法还包括：利用一层氧化物隔离该非晶硅柱；在非晶硅柱之间形成栅极介电层；以及基本在该非晶硅柱之间、且在该纳米管上形成栅极。该方法包括：在该栅极上形成氮化物层；在该栅极的每一侧上形成氧化物间隔壁；以金属触点取代非晶硅，其中第一金属触点为源极而第二金属触点为漏极；以及在该器件上沉积钝化电介质。
根据本发明另一实施例，提供一种用于形成自对准碳纳米管场效应晶体管半导体器件的方法。该方法包括：在热氧化物衬底上沉积金属催化剂；在该器件上沉积低温氧化物层；穿过该氧化物、金属催化剂，进入该金属催化剂下面的热氧化物中蚀刻出沟槽；以及蚀刻该低温氧化物层从而形成氧化物岛。该方法还包括：剥落暴露的金属催化剂；在氧化物岛下的金属催化剂之间生长纳米管；以及将纳米管包围在栅极电介质中。该方法包括：在氧化物岛的相对的表面上形成氮化物间隔壁；通过化学气相沉积基本在氧化物岛之间、且在纳米管上形成栅极；以及在该器件上沉积钝化电介质。
根据本发明一实施例，提供一种用于形成自对准碳纳米管场效应晶体管半导体器件的方法。该方法包括：从形成在半导体器件表面上的金属催化剂垂直地生长纳米管；形成氮化物块结构(block structure)；以及将纳米管包围在栅极电介质中。该方法包括：沉积栅极金属，其通过该电介质与金属催化剂隔开；沉积氮化物层；以及形成由该氮化物层封盖的栅极金属柱。该方法在所述柱周围形成氮化物间隔壁；基本在该些柱之间沉积漏极金属，其通过该介电层与栅极金属隔开；以及在该器件上沉积钝化电介质。
附图说明
下面将参照附图更加详细地介绍本发明的优选实施例：
图1a至1i示出了根据本发明一实施例的第一碳纳米管场效应晶体管的源极/漏极；
图2a至2b示出了根据本发明一实施例的第一碳纳米管场效应晶体管的另一源极/漏极；
图3a至3g示出了根据本发明一实施例的第一碳纳米管场效应晶体管的栅极；
图4a至4d示出了根据本发明一实施例的包括在适当位置生长的纳米管的碳纳米管场效应晶体管；
图5a至5n示出了根据本发明一实施例的包括在适当位置垂直生长的纳米管的碳纳米管场效应晶体管；以及
图6a至6b示出了根据本发明一实施例的纳米管的定向组装。
具体实施方式
根据本发明一实施例，场效应晶体管(FET)的栅极、源极和漏极是自对准的，由此减小交叠电容。
根据本发明一实施例，可使用通过剥离蚀刻(lift-off etch)的图案转移来制造碳纳米管FET，其中源极和漏极在栅极之前形成。参照图1a至1i，在热氧化物102和硅衬底103中形成对准标记101。对准标记101是定位图案时可用作参照的高精度部件。在硅103上沉积热氧化物102。硅可以是例如P+掺杂的(0.01Ω·cm，约3×1018cm-3)。可以在热氧化物102上沉积纳米管104，并可以通过光刻定位光致抗蚀剂105。纳米管可以以浆料的形式沉积，其中纳米管沉积是随机的。可以通过定向组装来沉积纳米管，如下所述。光致抗蚀剂暴露纳米管的端部。在暴露出纳米管端部的沟槽中形成金属触点106-107。该金属可以是例如钴(Co)、镍(Ni)、钨(W)或钛(Ti)。可以在器件上沉积金属，填充暴露出纳米管104的端部的沟槽。可以剥落光致抗蚀剂105。沉积在沟槽中的金属形成源极/漏极触点106-107。可在器件上沉积非晶硅(a-Si)108。可以在a-Si层上沉积氮化物层109。可以蚀刻该氮化物从而在金属触点106-107的侧面上形成间隔壁，例如110。可以选择性地去除或湿法化学氧化非晶硅108。可以在器件上沉积栅极介电膜111。此处，如下面的方法，电介质可以是二氧化硅以及任何其它高k介电材料，例如，HfO2。可以通过例如CVD和蚀刻基本在形成源极和漏极的金属触点106-107之间形成栅极112。在器件上沉积钝化介电层113。源极、漏极和栅极112自对准于对准标记101。
二者择一地，可以在形成栅极之前通过反应离子蚀刻(RIE)形成源极/漏极。参照图2a至2b，方法首先使用RIE形成源极/漏极106-107，从而限定源极/漏极金属。RIE需要与碳纳米管104隔离。可以在器件上沉积氮化物层201，并从围绕金属触点的区域蚀刻掉该氮化物层。可以在金属触点的侧面上形成氮化物间隔壁，例如202。在器件上沉积栅极电介质203。可以基本在源极与漏极106至107之间形成栅极金属204。可以在器件上沉积钝化电介质205。热氧化物可以是约150nm厚。
根据本发明另一实施例，可以在源极/漏极之前形成栅极。可在纳米管104的端部上沉积非晶硅301。可以利用氧化物层302覆盖a-Si。可以在a-Si(例如301)之间沉积栅极电介质303。可以基本在a-Si柱(例如301)之间形成栅极304。可以在栅极金属304上形成氮化物层305。可以在栅极金属304的端部上形成氧化物间隔壁，例如306。可以剥落a-Si/氧化物的暴露的角，暴露出a-Si。围绕栅极金属的剩余的a-Si可以通过RIE去除。可以在先前由a-Si占据的区域中沉积金属触点307-308。金属触点307-308与栅极电介质303和栅极金属304下面延伸的纳米管104连接。金属触点307-308形成器件的源极和漏极。金属触点307-308可以与沉积在热氧化物102和硅衬底103中的对准标记101对准。可以在器件上沉积钝化电介质309。
根据本发明一实施例，可以在适当位置(in place)生长碳纳米管FET。源极/漏极可以在栅极之前形成。在热氧化物层102上沉积非晶硅层401。可以在金属催化剂上沉积低温氧化物(LTO)层402。可以由氧化物402、非晶硅401和热氧化物102中蚀刻出沟槽。非晶硅401可以从氧化物402下方被部分底切(under cut)。可以在底切的非晶硅膜401的边缘上自组装金属催化剂401B，例如Fe、Co、Ni或Fe/Mo。可以在金属催化剂401B的剩余部分之间生长碳纳米管403，其中，一部分纳米管悬在热氧化物102上方。可以通过化学气相沉积(CVD)沉积栅极介电膜404，包围纳米管403。由此，可以完全以栅极电介质(例如SiO2)覆盖纳米管403。可以在氧化物(例如402)的侧面上形成间隔壁，例如405。可以基本在氧化物(例如402)之间形成栅极406。若热氧化物102中的蚀刻足够深，则栅极金属406可以围绕整个纳米管403和介电膜404叠层。为此，可以借助化学气相沉积来沉积栅极金属，从而覆盖纳米管/介电膜叠层的背侧。包围构造提供了良好的栅极与纳米管耦合(gate-to-nanotube coupling)。可以在器件的表面上沉积钝化电介质406。
根据本发明另一实施例，可以在适当位置垂直生长碳纳米管。纳米管可以从例如基体处的金属源或金属粒子催化剂垂直生长。参照图5a至5n，可以在硅衬底502上形成金属催化剂501。可以在器件上沉积第一层氮化物503。可以在第一层氮化物503上沉积氧化物层504。可以在氧化物504上沉积第二层氮化物505。可以通过光刻在器件上形成光致抗蚀剂，例如506，其中暴露出金属催化剂501。在器件上沉积多个第二金属催化剂，例如507。可以剥落光致抗蚀剂，例如506，使得形成在第一金属催化剂501上的第二催化剂(例如507)保留下来。可以自每个第二金属催化剂(例如507)垂直生长纳米管，例如508。由此，可以形成纳米管的二维和三维阵列。
纳米管的垂直生长发生在金属粒子催化剂位于垂直于衬底排列的孔中时。在此情况下，用于生长的空间受到限制，并迫使管的生长沿着垂直方向。具体而言，如图5b中的垂直孔可以使用抗蚀剂和图案转移来形成。
可以在器件上沉积非晶硅层509。可以向下平坦化器件至第二氮化物层505。可以从器件上去除氮化物-氧化物-氮化物层503至505的一部分。围绕纳米管(例如508)和金属催化剂501和507的柱体保留了下来。可以在氮化物层505、纳米管508、以及a-Si 509上形成牺牲层510。接触层可以是例如钛或钨。可以从氮化物层503与505之间去除氧化物层504。可以从纳米管(例如508)周围，与氧化物层504同时蚀刻掉a-Si 509。或者，可以在已经去除了氧化物层504后去除a-Si 509。可以在纳米管(例如508)周围、金属催化剂501上面和牺牲层510下面形成栅极电介质，例如511。或者，对于纳米管二维阵列，栅极电介质511可以沉积在纳米管之间。可以通过例如蚀刻去除牺牲层510。可以在器件表面上面沉积栅极金属512。可以在栅极金属512上沉积第三氮化物层513。可以去除部分栅极金属512和第三氮化层513。栅极金属和氮化物间隔壁(例如512和513)的柱体保留在金属催化剂-纳米管结构的周围。氮化物间隔壁(例如514)形成在每个柱体周围。可以在金属催化剂-纳米管结构上形成漏极515，由此形成FET。可以在FET之间沉积钝化电介质516。
应注意，纳米管自金属催化剂的生长的确切机理目前未知。然而，由金属催化剂(例如氧化铝支撑钼(Mo)颗粒上的钴(Co))生长单壁纳米管的工艺可以按多种方式实施。
根据本发明一实施例，纳米管可通过定向组装(directed assembly)而非上述的沉积或生长的方法而被放置在适当位置。使用通过化学或物理工艺驱动的选择性沉积，定向组装可用于纳米管的水平和垂直沉积。选择性沉积可包括形成附着层或起受体(receptor)作用的化学基，从而促进在给定位置的管的所需沉积。图6a和6b分别示出了用于水平和垂直定向组装的方法。可以制备在每一端包括预定化学基602(例如DNA链(strand)或硫醇基)的纳米管601。可以将纳米管601置于包括受体604的衬底603的附近，例如在使用DNA的情况下，可使用互补的DNA链。在使用硫醇基(thiol group)时，可以构造金粒子或包括金的接触形状，从而与纳米管601的化学基602结合。由此可以根据定向组装将纳米管601置于衬底603上。
为改善高k介电膜的性能，具有高介电常数的介电膜可以用作栅极绝缘体。碳纳米管FET的电容不随介电膜的厚度明显改变，由此，难以实现期望的电容，即使使用薄的栅极介电膜。关于这一点，氧化铝Al2O3(k＝9)以及氧化铪(HfO2)(k＝20)是有希望的候选者。可以氧化CVD-铝从而产生高k栅极电介质，或可以直接沉积CVD-Al2O3(HfO2)。与SiO2相比，这些材料将栅极电容提高达5倍，并且与减小介电膜厚度相比可以对器件性能产生更大作用。由于纳米管在大气环境中为pFET，而退火后在真空和诸如氩(Ar)的惰性气体中变为nFET，因此可以在增加介电膜的沉积前将器件退火。这样将管转变为nFET。利用电介质将其封盖在原位还防止了管再次变为pFET。对于互补技术，应转化为pFET的FET上的介电膜可以局部地去除，也允许该FET被掺杂。低温下的CVD沉积再次覆盖这些器件(之前无需额外的退火步骤)。
由于所有结构(pFET和nFET)都以氧化物(或任何其它适合的介电膜)覆盖，所以在制造栅极电极时不产生短路。CVD可以用于栅极的沉积。对如图4和5所述的制造过程使用化学气相沉积，可以确保已经包围在介电膜中的纳米管完全被金属栅极围绕。这对于良好的栅极与纳米管耦合会是重要的。在需要时，可以构图和去除栅极金属。可以为电连接而露出源极和漏极电极。
以上已经介绍了碳纳米管FET及其制造方法的优选实施例，注意，本领域技术人员在上述教导的启发下可进行改动和变化。因此应理解，可以对所公开的本发明的特定实施例在由所附权利要求限定的本发明的范围和实质内进行改动。对于由此以细节和专利法所需的特定内容介绍的本发明，专利文件所要求和期望保护的，在所附权利要求中列示。

Claims (19)

1.一种自对准碳纳米管场效应晶体管半导体器件，包括：
沉积在衬底上的碳纳米管；
形成在该碳纳米管的第一端的源极；
形成在该碳纳米管的第二端的漏极；以及
基本形成在该碳纳米管的一部分上，通过介电膜与该碳纳米管隔开的栅极。
2.如权利要求1所述的自对准碳纳米管场效应晶体管半导体器件，其中该衬底包括沉积在硅衬底上的热氧化物。
3.如权利要求2所述的自对准碳纳米管场效应晶体管半导体器件，其中该热氧化物约150纳米厚。
4.如权利要求1所述的自对准碳纳米管场效应晶体管半导体器件，其中该栅极的一部分还通过氧化物层与该碳纳米管隔开。
5.如权利要求1所述的自对准碳纳米管场效应晶体管半导体器件，其中该栅极通过氮化物间隔壁与该源极和漏极隔开。
6.如权利要求1所述的自对准碳纳米管场效应晶体管半导体器件，还包括在该器件上的钝化介电层。
7.如权利要求1所述的自对准碳纳米管场效应晶体管半导体器件，还包括在该衬底中的对准标记，该源极和漏极与该对准标记对准。
8.如权利要求1所述的自对准碳纳米管场效应晶体管半导体器件，其中该栅极包围在该介电膜和该碳纳米管周围，从而与该碳纳米管的背侧接触。
9.一种碳纳米管场效应晶体管半导体器件，包括：
包围在介电材料中的垂直碳纳米管；
形成在该碳纳米管的第一侧的源极；
形成在该碳纳米管的第二侧的漏极；
双层氮化物复合体，通过该双层氮化物复合体形成每个该源极和漏极的连接带，将包围在该介电材料中的该碳纳米管连接至该源极和漏极；以及
基本形成在该碳纳米管的一部分上的栅极。
10.如权利要求9所述的碳纳米管场效应晶体管半导体器件，还包括该碳纳米管的基部处的金属催化剂。
11.一种形成自对准碳纳米管场效应晶体管半导体器件的方法，包括步骤：
在热氧化物衬底上沉积纳米管，其中该衬底包括对准标记；
在该纳米管的每个端部处形成金属触点，其中第一金属触点为源极，第二金属触点为漏极；
在该器件上沉积非晶硅层；
在每个金属触点的相对侧面上形成氮化物间隔壁；
在该器件上沉积高k介电膜；
氧化该非晶硅；以及
基本在该源极与漏极之间，在该纳米管上面形成栅极。
12.如权利要求11所述的方法，还包括在该器件上沉积钝化电介质的步骤。
13.如权利要求11所述的方法，其中该纳米管为单壁纳米管。
14.如权利要求11所述的方法，其中该金属触点利用光致抗蚀剂形成。
15.一种形成自对准碳纳米管场效应晶体管半导体器件的方法，包括步骤：
在热氧化物衬底上沉积纳米管，其中该衬底包括对准标记；
通过反应离子蚀刻在该纳米管的每个端部处形成金属触点，其中第一金属触点为源极，第二金属触点为漏极；
在每个金属触点的相对侧面上形成氮化物间隔壁；
在该器件上沉积高k介电膜；以及
基本在该源极与漏极之间和该纳米管上面形成栅极。
16.如权利要求15所述的方法，还包括在该器件上沉积钝化电介质的步骤。
17.一种形成自对准碳纳米管场效应晶体管半导体器件的方法，包括步骤：
在热氧化物衬底上沉积纳米管，其中该衬底包括对准标记；
在该纳米管的每个端部上形成非晶硅柱；
利用一层氧化物隔离该非晶硅柱；
在非晶硅柱之间形成栅极介电层；
基本在该非晶硅柱之间和该纳米管上面形成栅极；
在该栅极上形成氮化物层；
在该栅极的每一侧上形成氧化物间隔壁；
以金属触点取代该非晶硅，其中第一金属触点为源极，第二金属触点为漏极；以及
在该器件上沉积钝化电介质。
18.一种形成自对准碳纳米管场效应晶体管半导体器件的方法，包括步骤：
在热氧化物衬底上沉积金属催化剂；
在该器件上沉积低温氧化物层；
穿过该氧化物、金属催化剂，并进入该金属催化剂下面的热氧化物中蚀刻出沟槽；
蚀刻该低温氧化物层，从而形成氧化物岛；
剥落暴露的金属催化剂；
在该氧化物岛下的金属催化剂之间生长纳米管；
将该纳米管包围在栅极电介质中；
在该氧化物岛的相对的表面上形成氮化物间隔壁；
通过化学气相沉积基本在该氧化物岛之间、以及在该纳米管上面形成栅极；以及
在该器件上沉积钝化电介质。
19.一种形成自对准碳纳米管场效应晶体管半导体器件的方法，包括步骤：
自形成在该半导体器件的表面上的金属催化剂垂直地生长纳米管；
形成氮化物块结构；
将该纳米管包围在栅极电介质中；
沉积栅极金属，其通过该栅极电介质与该金属催化剂隔开；
沉积氮化物层；
形成由该氮化物层封盖的栅极金属柱；
在所述柱周围形成氮化物间隔壁；
基本在该些柱之间沉积漏极金属，其通过该介电层与该栅极金属隔开；以及
在该器件上沉积钝化电介质。
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