CN1612326B - 调节半导体器件中载流子迁移率的方法和装置 - Google Patents

调节半导体器件中载流子迁移率的方法和装置 Download PDF

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CN1612326B
CN1612326B CN2004100692526A CN200410069252A CN1612326B CN 1612326 B CN1612326 B CN 1612326B CN 2004100692526 A CN2004100692526 A CN 2004100692526A CN 200410069252 A CN200410069252 A CN 200410069252A CN 1612326 B CN1612326 B CN 1612326B
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M·P·别良斯基
D·恰丹巴拉奥
O·H·多库马奇
B·B·多里斯
O·格卢斯陈克夫
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GlobalFoundries Inc
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Abstract

本发明提供了一种调节半导体器件中载流子迁移率的方法和装置。在制造互补型金属-氧化物-半导体(CMOS)场效应晶体管(包括nFET和pFET)时，通过使栅极材料和金属反应在晶体管栅极内产生应力合金(最好是CoSi2、NiSi、或PdSi)，提高或调节了载流子的迁移率。在nFET和pFET同时存在的情况中，各个合金的固有应力在各个晶体管的沟道上导致相反的应变。通过在nFET和pFET合金或硅化物中保持相反的应变，在单个芯片或衬底上的两类晶体管的载流子迁移率都可得到提高，从而提高CMOS器件和集成电路的性能。

Description

调节半导体器件中载流子迁移率的方法和装置
技术领域
本发明一般涉及集成电路中的晶体管的制造，尤其涉及在极小尺度下性能得到提高的场效应晶体管互补对的制造。
技术背景
集成电路设计和制造的性能和经济因素已经导致集成电路的元件(如，晶体管、电容等)的尺度在尺寸上急剧减小，而在芯片上的紧凑度急剧增大。也就是说，通过减少为了实现片上系统的目标所需的芯片间和板间互连的数量，而增加的元件的集成度和紧凑度，减小了信号传输路径长度、信号传输时间、对噪音的敏感度和可能的时钟频率的增加，而增加集成度所需的元件尺寸的减小，增加了在芯片上提供的性能与每芯片生产成本(如，晶片/芯片面积和工艺材料)和潜在地含有芯片的器件的成本的比值。
然而，当集成电路元件的尺度缩小时，不可避免地损害了使晶体管和其它元件运转的恒定材料特性和物理效应。因此，对晶体管的设计已进行了很多改进，以把这些元件的性能保持到合适的水平。例如，已使用轻掺杂漏区(LDD)结构(现在一般称为延伸掺杂，因为已在电流最小值特征尺寸条件中要求重掺杂水平)、卤素掺杂以及渐变杂质分布，以抵消短沟道效应和穿通效应等，尤其对于场效应晶体管(FET)，场效应晶体管已成为供除最高频率器件的所有器件选择的有源器件。器件尺度的减小也要求在降低的电压下工作，以保持充分的性能且不损坏器件，虽然可以降低运行限度(operating margin)。
在场效应晶体管中保持充分性能的重要因素是载流子迁移率，其影响在通过非常薄的介质与沟道隔离的栅极上施加的电压的控制下，在掺杂半导体沟道中(以电子或空穴)流动的电流或电荷量。FET中载流子迁移率的降低不仅减小给定晶体管的开关速度/转换率，也减少了“开态”电阻到“关态”电阻之间的差别。后一个效应增加了对噪音的敏感度，减少了下行(downstream)晶体管栅极(电容性负载)的数量，和/或降低了驱动下行晶体管栅极(电容性负载)的速度。即使在金属-氧化物-半导体(MOS)场效应晶体管和互补MOS(CMOS)器件(目前在集成电路中广泛使用)的早期开发中，载流子的迁移率尤其是设计重点，由于nMOS器件中的主要载流子电子和pMOS器件中的主要载流子空穴之间的载流子的迁移率的差别，经常要求将pMOS器件制成比互补nMOS器件大好几倍，pMOS器件与互补nMOS器件配对以获得CMOS对的合理对称操作。在更近来的严格设计中已经表现出，由于抑制短沟道效应和超薄氧化物效应需要的重掺杂，在体积缩小很多的MOS器件中，载流子迁移率下降了。
也已在理论上表现出，并得到试验证实，FET的沟道区中的机械应力可以显著提高或降低载流子的迁移率；依赖于应力的符号(如，张力或压力)和载流子类型(如，电子或空穴)。在形成晶体管沟道的掺杂半导体晶格中，张应力提高电子迁移率，降低空穴迁移率，而压应力提高空穴迁移率，降低电子迁移率。该现象得到了公认，而与导致其发生的物理效应相关的理论对于其开发并不重要。在这点上，已经提出了大量的结构和材料用于在半导体材料中包括张力或压力，如在集成电路设计中通常包括的浅沟槽隔离(STI)结构、栅极隔板、蚀刻阻挡层和硅化物。使Si沟道应变的现有技术方法包括使用SiGe从沟道底部施加应力，而使用STI材料和SiN蚀刻阻挡层的方法从侧面施加纵向应力。
然而，如本领域技术人员所公知，关于SiGe缓冲层或利用应变Si盖层的注入-退火-缓冲方法，存在一些问题，包括严重影响效率的位错，以及包括砷扩散加大、成本和过度复杂性的重大问题。STI方法成本较低，但是不对栅极自对准，并具有外部电阻(RX)尺寸灵敏性。使用氮化物蚀刻阻挡层产生应力(而值得使用只是因为它相对便宜)的方法确实有利，但是效果相对微小。
另外，在现有技术中，一般只能将该结构制成为一种类型；以产生张应力或压应力而不是同时产生二者。因此，在同时使用pFET和nFET晶体管的集成电路设计和CMOS技术(其中主要通过互补pMOS和nMOS晶体管对执行逻辑)中，特别地，一类晶体管中载流子迁移率的提高需要伴随有另一或互补类型的晶体管中载流子迁移率的降低；虽然在理论上有利于提高CMOS对的对称操作，既便得到一些，也是很少的净性能提高。而且，由这种结构产生的和/或在可能超出晶体管尺寸的很多区域上的单一类型应力，将导致晶片或衬底的翘曲或卷曲，所述翘曲或卷曲会损害后来的光刻工艺，如接触和连接的形成，或在严重的情况下，芯片或晶片破裂；当投入使用后，降低制造效率(在少数情况)或可靠性。另外，由这种结构产生的应力水平一般难于控制，尤其因为该结构尺寸经常被如隔离和击穿电压的其它设计考虑所限定。而且，这种结构可在芯片或晶片表面上呈现出不利的形貌，其将损害后续的制造工艺。
发明内容
因此本发明的一个目的是提供一种在同一芯片或晶片上的不同电子元件结构中可以提供张应力和压应力的方法和结构。
本发明的另一目的是提供一种具有高制造效率，可容易和重复实现的方法和结构，其对芯片或晶片或早期或后期进行的制造工艺不产生负面影响，其中可容易地控制张应力和压应力水平。
本发明的再一目的是提供一种方法和结构，其相对可以避免由在净形变接近零的衬底上交替施加多次相反的应力引起的翘曲。
为实现本发明这些和其它目的，提供了一种调节半导体器件中的载流子的迁移率的方法，包括以下步骤：淀积金属或金属的组合物，以接触第一或第二晶体管栅极结构，以及使金属与晶体管栅极结构形成合金，以形成晶体管栅极内的第一应力硅化物。在选定晶体管的沟道内产生第一应力，而没有在另一个晶体管的沟道中产生应力。同样，可在另一个晶体管中形成第二应力硅化物，以在其沟道中提供应力，但是所述应力不影响第一晶体管内沟道上的应力。
根据本发明另一个目的，提供了一种调节半导体器件中的载流子迁移率的装置，包括：衬底，在所述衬底上形成的均具有栅极介质、栅极、以及源、漏和栅极区的第一和第二晶体管，至少在第一晶体管的一个沟道中提供张应力的第一应力硅化物，以及至少在第二晶体管的一个沟道中提供压应力的第二应力硅化物。
附图说明
通过参考附图对本发明优选实施例的下述详细说明，将更好的理解前述和其它目的、方面和优点，其中：
图1a、1b和1c提供了制造CMOS晶体管的第一步骤的进行过程的截面图，包括初始Si衬底(图1a)、形成器件隔离(图1b)，以及栅极氧化(图1c)；
图2为制造CMOS晶体管的第二步骤的截面图，包括栅极材料的淀积；
图3为制造CMOS晶体管的第三步骤的截面图，包括施加硬掩膜、光刻胶，以及构图所述光刻胶；
图4为制造CMOS晶体管的第四步骤的截面图，包括除去所述光刻胶，并蚀刻栅极叠层材料；
图5为制造CMOS晶体管的第五步骤的截面图，包括延伸区的注入，隔板的制造，接着进行源漏区注入，随后进行结退火并硅化；
图6为制造CMOS晶体管的第六步骤的截面图，包括SiN衬层的淀积；
图7为制造CMOS晶体管的第七步骤的截面图，包括氧化膜的淀积，接着进行栅极叠层顶部的CMP；
图8为制造CMOS晶体管的第八步骤的截面图，包括使用光刻和蚀刻工艺构图氧化或氮化膜，以在pEFT的硅化过程中阻挡nFET区；
图9为制造CMOS晶体管的第九步骤的截面图，包括在晶片顶部淀积金属，以形成张力硅化物；
图10为制造CMOS晶体管的第十步骤的截面图，包括使用标准RTA工艺使第一硅化物与施加的金属反应，以及除去过剩的没有反应的金属；
图11为制造CMOS晶体管的第十一步骤的截面图，包括使用干或湿蚀刻工艺除去nFET阻挡层，以及施加pFET阻挡层和施加与nFET栅极接触的金属；
图12为制造CMOS晶体管的第十二步骤的截面图，包括使用常规RTA工艺形成第二硅化物，接着除去未反应的金属和pFET阻挡层，示出了最终的优选实施例；
图13为在衬底和使用硅化钴(CoSi2)栅极结构的栅极区中产生的压应力和张应力的截面图；
图14为在衬底和使用硅化钯栅极结构的栅极区中产生的压应力和张应力的截面图；
图15为三栅极器件的截面图，其允许沟道在沟道的栅极控制得到提高的FET中具有更大的应力和载流子迁移率。
具体实施方式
在下述对图1-12的讨论中，应该认识到，希望下述实施例在大部分应用和集成电路设计中是最有利的，从而对所提供的本发明有最全面的认识和了解。也就是说，下述实施例及其变化将说明对在单个芯片上的各个相邻晶体管施加的各种张应力和压应力，并将提供对载流子迁移率的提高或其它调节。然而，也可应用结合该实施例说明的本发明的原理，给任何设计中和为任何目的的相邻晶体管，提供任何希望大小、任意符号的应力。
现在参考附图，尤其参考图1a、1b和1c，示出了制造本发明优选实施例的首先的几步，包括：制备衬底22(如，Si、应变Si、SiGe、Ge、SOI、或任何其它半导体衬底)，形成隔离器件23，如在所述衬底22上用于限定衬底22的n阱区和p阱区的浅沟槽隔离(STI)，接着在衬底上形成氧化层21，其在后来构成栅极介质。在氧化后，在整个晶片上淀积适于形成栅极的半导体材料20(如，硅或锗)，如图2所示。如图3所示，使用硬掩膜材料24覆盖该材料20，然后用光刻胶层25覆盖硬掩膜材料24。将光刻胶层25构图为位于希望的pFET和nFET栅极区正上方的至少两部分251、252。然后使用光刻胶部分251/252将硬掩膜的曝光区域除去，变为与光刻胶部分251/252具有相同平面尺寸的至少两部分241/242。
现在参考图4，在构图硬掩膜24后除去光刻胶25，将材料20和栅极氧化物蚀刻为至少两个独立的栅极叠层，所述栅极叠层限定了衬底22上的nFET和pFET，nFET和pFET分别包括剩余栅极氧化物212/211的薄层、栅极202/201、以及硬掩膜242/241。
在形成栅极后，注入延伸区26，形成隔板27，随后形成源/漏区注入34，接着进行结退火并形成硅化物或其它半导体材料的合金(有时统称为“硅化物”，即使不包括硅)35，以及把杂质扩散到特定区域，如图5所示。
如图6所示，对整个晶片施加SiN衬层。然后淀积氧化膜29，随后对栅极叠层顶部进行CMP，从而使栅极顶部的整个晶片的表面平面化，并除去硬掩膜242/241，如图7所示。
现在参考图8，示出了中间结构，其中，使用光刻和蚀刻工艺构图氧化或氮化膜30，以阻挡nFET区来制备pFET的硅化。
下一步，如图9所示，在整个晶片上淀积用来形成张力合金或硅化物(如，CoSi2)的金属31。当栅极材料20与金属31反应时，在栅极区201内形成张力硅化物。张力硅化物希望位于pFET的栅极中，从而张力硅化物在沟道341内产生压应力和提高空穴迁移率的环境，从而提高了性能。
使用如标准RTA工艺使该第一合金或硅化物201(下文中有时优选地简称“硅化物”，虽然本发明可利用其它半导体材料实施)反应，随后，如图10所示，除去过剩的没有反应的金属。然后，从nFET上除去阻挡层30，并在pFET区上设置新的阻挡层32，以允许另一金属33在施加时只与nFET栅极202接触，如图11所示。
如第一硅化物，使用如常规RTA工艺形成第二硅化物。与nFET栅极接触，形成第二合金或硅化物(表现压力特性)。nFET栅极最好表现压力特性，以对nFET沟道342施加张应力。公知nFET沟道342中的张应力可以增加电子迁移率和提高nFET性能。
除去未反应的金属和pFET上的阻挡层32，以形成如图12所示的本发明优选实施例的最终结构，可以通过连接、钝化层等公知方法完成所述最终结构。
如图所示，重要的是观察张力硅化物201和压力硅化物202都没有到达它们各自的沟道341，342。栅极区内未反应的Si(优选约100的厚度)适当地避免了功函数和阈值的改变以及对栅极氧化物完整性的可能影响。通过精确测量多层厚度和精确淀积金属厚度调节该过程，以使未反应的硅化物不与沟道中的Si接触。也使用精确温度控制产生希望的反应并定位硅化物。
公知CoSi2膜非常抗张，而NiSi较小抗张，以及PdSi非常抗压。公知其它合金(如，Ge或SiGe的合金)也具有类似效应。通过选择形成硅化物的金属，通过形成在pFET沟道中产生压应力并防止在nFET沟道中产生压应力的，以及反之亦然的结构和方法，本发明使用这些合金或硅化物的特性明确地达到了电子和空穴迁移率的希望值。可使用这些硅化物和厚度的任何组合来优化应力，并因此优化各个晶体管沟道中载流子的迁移率和栅极的功函数，以达到希望的开关阈值。例如，形成具有如下组合的栅极是有利的：在栅极叠层底部(接近沟道)使用NiSi或CoSi2，并在栅极预部使用PdSi。可通过如下实现上述：凹入多晶Si栅极201或202，形成NiSi或CoSi2，然后淀积更多多晶Si，进行CMP，然后与Pd反应形成PdSi。这里的主要优点为，如果栅极被完全硅化，或接近完全硅化，可以使用最接近沟道区的硅化物设计栅极的功函数，而使用在栅极顶部的硅化物设计沟道应力。通过使用非常薄的第一硅化层和厚得多的第二硅化层产生沟道应力，可能实现上述操作。这样，在允许栅极功函数的设计完全自由的同时，在从硅化物得到的张力和压力对空穴和电子载流子迁移率影响的范围内，可将空穴和电子载流子的迁移率提高或调节到任意希望值。
图13示出了CoSi栅极叠层(位于pFET栅极中)中的应力等高线，使用虚线表示压应力的分布，使用实线表示张应力的分布。显示了位于CoSi2栅极201正下方的沟道区341的截面图上的应力。非常抗张的CoSi2栅极显著扩展，提供所有示出应力图形的来源，并在衬底22a的沟道区内导致高度压力环境。压应力在衬底区22a中最大，当应力散开到衬底区22e时，压应力减小。应力符号在栅极边缘处突变。
图14示出了PdSi栅极叠层(位于nFET栅极中)中的应力等高线，使用虚线表示压应力的分布，使用实线表示张应力的分布。显示了位于PdSi栅极202正下方的沟道区342的截面图上绘制的应力。非常抗压的PdSi栅极显著缩短，提供所有示出应力图形的来源，并在衬底22a的沟道区内导致高度张力环境。张应力在栅极边缘的衬底区22a中最大，当应力散开到衬底区22e时，张应力减小。
图15示出了窄宽度沟道FET，有时称为FinFET，或代表CMOS对的nFET或者pFET的三栅极器件。最近，对于小尺寸需求下的高性能FET，有源Si区38的这种几何形状已经引起了关注，并尤其适合根据本发明的改进。在实施例中，使用了具有用栅极20包围有源区38的结构的器件。栅极20与金属反应以形成覆盖有源Si区38的至少三面的应力硅化物(如，PdSi、CoSi2、或NiSi)。此外，通过淀积硅可调节硅化物的位置，可能进行几步，(每步)之后，通过在适合的温度下退火形成适合厚度的金属和硅化物。该结构导致应力沿Si 37a和37b的垂直部分以及Si 36的水平部分扩展。在该结构中，由栅极的每个侧面在沟道中引起的应变被累积而显著增加，并且来自栅极的每个垂直部分和水平部分的应力，可以提高沟道的所有三个部分37a、37b和36的载流子迁移率。
如前所述，可以发现，本发明提供了用于控制和提高在同一芯片上的nFET和pFET中的载流子迁移率的方法和结构，没有损害制造效率或对早期形成的结构或后期执行的工艺产生不利的影响，并且在不损害制造效率的情况下，只需一些附加而公知的工艺就可容易地控制载流子的迁移率。由于在相对较小的各区域(相比于芯片厚度)施加虽然可能较大的压力和张力，芯片或晶片不会趋于翘曲或卷曲，首先，因为张应力和压应力区域分散，其次，因为只在与沟道一起延伸的相对小的栅极区施加应力。而且，由于硅化物的添加没有增加晶体管的面积，而只是改变其中的材料以大幅度提高性能、形貌的准确性、空间尺度和集成度。应该认识到，尽管对载流子迁移率的“改进”一般指其中的增加，但是通过相同的工艺，只是交换关于晶体管类型的硅化物材料，以颠倒施加到各晶体管导电/掺杂类型上的张力和压力类型，就可以减小载流子迁移率。另外，可使用备用材料进一步调节沟道应力的大小。形成硅化物的次序也可在晶体管之间变化，因为这些工艺通过掩蔽来阻挡。
尽管根据单个优选实施例描述了本发明，本领域的技术人员将认识到，本发明可在所附权利要求书的精神和范围内进行改变。

Claims (20)

1.一种调节半导体器件中载流子迁移率的方法，包括以下步骤：
淀积金属或金属组合物，以接触第一或第二晶体管栅极结构中的一个，以及
使所述金属或金属组合物和所述晶体管栅极结构成为合金，以在所述晶体管栅极内形成第一应力合金，从而在所述第一或第二晶体管的至少一个相应的沟道中产生第一应力，而没有在所述第一或第二晶体管的另一个晶体管的至少一个沟道中产生应力。
2.根据权利要求1的方法，其中所述合金为硅化物。
3.根据权利要求1的方法，其中第一晶体管和第二晶体管具有相反的导电类型。
4.根据权利要求1的方法，其中所述淀积步骤包括：
将第一金属淀积到所述第一晶体管的一部分所述栅极材料上，以在邻接所述第一晶体管的沟道的栅极的下部区域形成第三合金；以及
在所述第一晶体管栅极上淀积第二金属，以在栅极的上部区域形成所述第一晶体管栅极内第一应力合金。
5.根据权利要求4的方法，其中所述淀积步骤还包括：
将第三金属淀积到所述第二晶体管的一部分所述栅极材料上，以在邻接所述第二晶体管的沟道的栅极的下部区域形成第四合金；以及
在所述第二晶体管栅极上淀积第四金属，以在栅极的上部区域形成所述第二晶体管栅极内的第二应力合金，由此所述第二应力合金在所述第二晶体管的沟道区产生第二应力。
6.根据权利要求5的方法，其中第一应力合金和第二应力合金具有相反的应力。
7.根据权利要求6的方法，其中第一晶体管和第二晶体管具有相反的导电类型。
8.根据权利要求7的方法，其中
所述第一晶体管是nFET，其中所述第一应力合金受到压应力，产生所述第一应力，其中第一应力为张力，以及
所述第二晶体管是pFET，其中所述第二应力合金受到张应力，产生所述第二应力，其中第二应力为压力。
9.一种调节半导体器件中载流子迁移率的方法，包括以下步骤：
在第一晶体管栅极而不是第二晶体管栅极上淀积金属，以与第一晶体管栅极形成合金，从而形成第一应力合金，导致在所述第一晶体管的至少一个沟道中施加的第一应力，以及
在所述第二晶体管栅极而不是所述第一晶体管栅极上淀积金属，以与第二晶体管栅极形成合金，从而形成第二应力合金，导致至少在所述第二晶体管的沟道中施加的第二应力，
所述第一晶体管和所述第二晶体管具有相反的导电类型。
10.根据权利要求9的方法，其中所述第一应力合金和第二应力合金施加相反的应力。
11.根据权利要求10的方法，其中
由所述第一应力合金导致的所述第一应力至少在所述第一晶体管的沟道区表现应力，其与由所述第一应力合金提供的应力相反，以及
由所述第二应力合金导致的所述第二应力至少在所述第二晶体管的沟道区表现应力，其与由所述第二应力合金提供的应力相反。
12.根据权利要求11的方法，其中通过对所述第一晶体管的至少一个沟道施加张应力，而对所述第二晶体管的至少一个沟道施加压应力，来调节载流子的迁移率。
13.一种调节半导体器件中载流子迁移率的装置，包括：
衬底，
第一晶体管，包括栅极介质、栅极、以及源、漏和栅极区，形成于所述衬底上，
第二晶体管，包括栅极介质、栅极、以及源、漏和栅极区，形成于所述衬底上，以及
第一应力合金，至少在第一晶体管的一个沟道提供张应力。
14.根据权利要求13的装置，其中所述合金是硅化物。
15.根据权利要求13的装置，还包括第二应力合金，至少在第二晶体管的一个沟道提供压应力。
16.根据权利要求15的装置，其中可由SiNi、CoSi2、PdSi或其它表现张力或压力特性的材料构成所述第一和第二应力合金。
17.根据权利要求16的装置，还包括：
位于所述第一晶体管的栅极区的下部区域的第三合金，以及
位于所述第二晶体管的栅极区的下部区域的第四合金。
18.根据权利要求17的装置，其中栅极包围每个所述第一和第二晶体管的所述沟道的至少两侧。
19.根据权利要求13的装置，其中可由SiNi、CoSi2、PdSi或其它表现张力或压力特性的材料构成第一应力合金。
20.根据权利要求19的装置，其中栅极包围每个所述第一和第二晶体管的所述沟道的至少两侧。
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