CN1605121A - 管芯底部与支撑板分隔开的表面安装封装 - Google Patents

管芯底部与支撑板分隔开的表面安装封装 Download PDF

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CN1605121A
CN1605121A CNA028252802A CN02825280A CN1605121A CN 1605121 A CN1605121 A CN 1605121A CN A028252802 A CNA028252802 A CN A028252802A CN 02825280 A CN02825280 A CN 02825280A CN 1605121 A CN1605121 A CN 1605121A
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semiconductor packages
semiconductor device
device die
mosfet
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CN100559557C (zh
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马丁·斯坦丁
安德鲁N·萨乐
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Infineon science and technology Americas
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Abstract

根据本发明的半导体封装包括金属壳体(12)，在金属壳体(12)的内部空间容纳有MOSFET(10)。所容纳的MOSFET(10)被定向，从而其漏极面向壳体(12)的底部，并通过导电环氧树脂层(14)或焊料等与壳体的底部电连接。MOSFET(10)的边缘与壳体(12)的壁隔开。MOSFET(10)的边缘和壳体(12)的壁之间的间隙被绝缘层(16)填充。MOSFET(10)的表面(标为A′)稍低于金属壳体(12)的凸起(22)形成的衬底的平面(标为A)。

Description

管芯底部与支撑板分隔开的表面安装封装
相关申请的交叉引用
本发明基于并要求由Martin standing和Andrew N.Sawle于2001年12月21日提交的题为“SURFACE MOUNTED PACKAGE WITH DIEBOTTOM SPACED FORM SUPPORT BOARD(管芯底部与支撑板隔开的表面安装封装)”的第60/342,333号美国临时申请的优先权，并且是由Martin Standing和Hazel Deborah Schofield于2001年3月28日提交的题为“CHIP SCALE SURFACE MOUNTED DEVICE AND PROCESS OFMANUFACTURE(芯片级表面安装器件和制造工艺)”的第09/819,774号美国专利申请的部分连续申请。上述两个申请的主题和公开内容被合并入本文中以作为参考。
发明领域
本发明涉及一种半导体封装，尤其涉及一种用于容纳具有可减少温度循环故障的结构的功率半导体管芯(semiconductor die)的半导体封装。
背景技术
通常，热循环会导致频繁和重复的应力，这种应力在分层结构中可能导致因老化等原因而造成的破裂，因此，温度循环(temperature cycling)是导致分层结构出现故障的一种材料因素(material factor)。
在半导体器件封装中，温度循环导致管芯与底层填料(die-underfill)的接合、底层填料与衬底的接合、焊料隆起焊盘(solder bump)连接以及其他区域中的钝化层的故障。这降低了封装的可靠性。因此，需要提供一种方法来减少由温度循环引起的故障。
现在参照附图，其中类似的参考标号指代了类似的元件。图1和图2示出了在2001年3月28日提交的第09/819,774号美国专利申请中得到完整描述的半导体封装5。该申请已转让给本申请的受让人并被合并入本文以用作参考。如图1和图2所示，半导体封装5包括在杯状壳体12内的MOSFET(金属氧化物半导体场效应管)10，壳体12起到漏极夹具的作用。壳体12优选地由铜合金制成并被镀银。壳体12具有大于MOSFET10的内部尺寸；因此MOSFET 10易于容纳在壳体12的内部中。MOSFET10的漏极触点通过装填了银的导电环氧树脂层14与壳体12的底部连接。环绕MOSFET 10的边缘涂布有一圈低应力高粘性的环氧树脂环16，用以对封装进行密封并为封装增加额外的结构强度。如图1所示，MOSFET 10的源极触点18和栅极触点20(它们布置在MOSFET 10的与其漏极触点相对的表面上)被暴露出来。壳体12包括两行凸起22，它们排列在壳体12的两个相对的边缘上。这些凸起被配置用于与诸如绝缘金属衬底或普通电路板的电路板(未示出)上的各个焊盘(land)电接触，从而使MOSFET10的漏极与其在电路中的位置电连接。如图1所示，MOSFET 10的源极触点18与壳体12的凸起22的接触表面平齐，因此，当在电路板上安装封装5时，MOSFET 10的源极触点18和栅极触点20将与电路板的表面相平齐。
如上所述，上述封装易于遭受因为温度循环而造成的可能的故障。因此，人们希望做出这样一种封装设计，其具有与上述结构相类似的结构，并且能够减少由热循环引致的衬底故障。
发明内容
为减少由例如热循环引致的衬底故障，本发明公开了一种半导体器件封装，其包括半导体器件管芯，所述半导体器件管芯具有与第二表面基本平行的第一表面，并且所述第一和第二表面每个都具有可焊接平面金属电极。另外，还公开了一种金属夹具(clip)，其具有包括第一和第二表面的平连接板(flat web)部分，其中，所述第二表面与所述半导体器件管芯的所述第一表面电连接。
至少一个可焊接平面金属柱状电极从所述夹具的平连接板部分的边缘向上延伸并与所述半导体器件管芯的边缘分隔开，所述管芯被置于所述夹具的内部，从而所述管芯向内凹入到所述夹具的内部，所述管芯的第二表面不与所述至少一个可焊接平面金属柱状电极平齐(或共面)。所述可焊接平面金属柱状电极的内部被去除至位于所述管芯的第二表面的平面上方的平行平面。
所述至少一个可焊接平面金属柱状电极可安装在诸如电路板的支撑表面的金属化的图案上，并且所述管芯的第二表面与所述支撑表面上的金属化图案分隔开。
因此，根据本发明所述的半导体封装减少了由于热循环引致的故障的数量，从而增加了封装可靠性。另外，根据本发明所述的半导体封装包括诸如MOSFET的垂直导电的金属氧化物半导体门控管芯(MOS-gateddie)，其具有第一主表面和与所述第一主表面相对的另一主表面，所述第一主表面上配置有主电极和控制电极，所述另一主表面上配置有另一主电极。根据惯例，在本发明所述封装中使用的垂直导电的MOSFET内的所述第一主电极为源电极；而其第二主电极为漏电极。垂直导电的MOSFET中的控制电极习惯上被称为栅电极。
尽管本文所描述的管芯为功率MOSFET，但显然管芯可以是任何所需的管芯，包括任何金属氧化物半导体门控器件(例如，绝缘栅双极型晶体管IGBT)、半导体闸流管或二极管等。
附图的简要说明
图1示出了现有技术的半导体封装的俯视图；
图2示出了沿线1-1方向看到的图1所示的半导体封装的剖视图；
图3示出了根据本发明所述经过改进的图1和图2所示的半导体封装的剖视图。
优选实施例的详细说明
现在参照图3，根据本发明，半导体封装24包括MOSFET(金属氧化物半导体场效应晶体管)10，与图1和图2所示的现有技术的封装相比，MOSFET 10被更深地设置(set back)入壳体(can)12的内部。因此，MOSFET 10的源极触点18和栅极触点20(图3中未示出)不再与壳体12的凸起22平齐。这种结构在图3中由虚线A、A′之间的间隙示出。可以发现，当MOSFET 10在壳体12中设置得更深从而使源极18与电路板的平面(由虚线A表示)偏移约0.001-0.005英寸时，由于在被环氧树脂焊接(solder down)或粘附到衬底时部件的热循环(themal cycling)所引起的故障被减少。
换句话说，根据本发明的半导体封装包括金属壳体，该壳体的内部空间能够容纳MOSFET或其他类似的半导体类型器件管芯。被这样容纳的MOSFET向内凹入壳体中并被定向，从而使MOSFET的漏极面向壳体的底部，并通过导电环氧树脂层或焊料等与其电连接。如此放置的MOSFET的边缘被与壳体的壁隔开。MOSFET的边缘与壳体的壁之间的间隙被绝缘层填充。该壳体优选地在其相对的边缘上包括两行接线柱(post)。这些接线柱可与衬底(如电路板)上的适当导电垫连接，以将MOSFET的漏极与其在电路内的适当位置连接。另外，在本发明的可选实施例中，接线柱可以是壳体边缘的全部或局部。
作为这种结构的结果，当将壳体安装在衬底上时，MOSFET的源极和栅极面向衬底。已经发现，如果MOSFET被定位在壳体内以使MOSFET的源极和栅极与衬底表面的下方平齐(sub-flush)，则由于热循环引起的故障可得到改善。因此根据本发明的一个方面，MOSFET的底面比衬底平面低0.001-0.005英寸，以减少温度循环故障。该稍低的空间被诸如焊料、环氧树脂等的导电连接材料填充。
在不偏离本发明的精神和范围的情况下对所披露的本发明进行变换是可能的。因而本领域的技术人员应该意识到，也可利用本发明优选实施例所用的材料之外的材料来实现本发明所预期的有益效果。例如，除了MOSFET 10以外，也可在本发明所述的封装中采用IGBT(绝缘栅双极型晶体管)、半导体闸流管、二极管或其它任何适当的半导体器件。作为其它一些例子，可以采用具有银的环氧树脂14以外的其他合金来形成壳体12和/或其它导电装置，以将半导体管芯连接至壳体12。
因此，虽然本发明是结合其特定实施例得到描述的，但对本领域技术人员来说，许多其它的变换、修改和其它用途是显而易见。因而声明，本发明不受本文特定公开的限制，而只受所附权利要求的限制。

Claims (8)

1.一种半导体器件封装，包括
半导体器件管芯，其具有与第二表面基本平行的第一表面；
所述第一表面具有第一可焊接平面金属电极；
所述第二表面具有第二平面金属性电极；
具有平连接板部分的金属夹具，所述平连接板部分具有第一表面和第二表面，所述平连接板部分的所述第二表面与所述半导体器件管芯的所述第一表面电连接；以及
从所述平连接板部分的边缘向上延伸并与所述半导体器件管芯的边缘分隔开的至少一个可焊接平面金属柱状电极，其中所述半导体器件管芯向内凹入所述夹具的内部，从而所述半导体器件管芯的所述第二表面不与所述至少一个可焊接平面金属柱状电极平齐，并且所述至少一个可焊接平面金属柱状电极安装在支撑表面的金属化图案上。
2.根据权利要求1所述的半导体封装，其特征在于，所述半导体器件管芯向内凹入0.001到0.005英寸。
3.根据权利要求1所述的半导体封装，其特征在于，所述夹具为杯状结构并且具有至少一个外围边缘部分，所述至少一个外围边缘部分为环绕所述管芯外部的连续边缘，并且与所述管芯的外部分隔开。
4.根据权利要求3所述的半导体封装，其特征在于，所述管芯和所述外边缘之间的所述间隙被绝缘球填充。
5.根据权利要求1所述的半导体封装，其特征在于，所述半导体器件管芯为金属氧化物半导体场效应晶体管、绝缘栅双极型晶体管、功率二极管以及半导体闸流管中的一种。
6.根据权利要求1所述的半导体封装，其特征在于，所述夹具为单体并且为杯状。
7.根据权利要求1所述的半导体封装，其特征在于，所述夹具由铜合金制成并镀有银。
8.根据权利要求1所述的半导体封装，其特征在于，所述第一可焊接平面金属电极通过装填有银的导电环氧树脂与所述平连接板部分的所述第二表面电连接。
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