CN1593041A - 具有多个首部的包的解封装和封装的方法、装置和计算机程序 - Google Patents
具有多个首部的包的解封装和封装的方法、装置和计算机程序 Download PDFInfo
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Abstract
描述了转发网络包的一种方法。该方法包括读取包含多个标志的表(114)以确定多个标志中的哪一个被置位或清零(116、130、132),以及在该包上执行一操作以按照标志的值解封装(118、120)或封装(134)该包。
Description
技术领域
本发明涉及在网络域之间转发网络包。
背景技术
通过一系列路由设备路由包,每个设备都在其从源到目的地的路径上存储和转发包。例如,包可能作为因特网包出发,经过ATM(异步传输模式路径)转发,然后回到公司网络上的以太网到达其最终预期的接受者。在网络通过这些网络域时,可为包添加各种首部封装或者从包删除各种首部封装。有些连接使用点对点协议(PPP),而其它的使用多协议标记交换(multiprotocol labelswitching)MPLS、层隧道协议(layer to tunneling protocol)LTTP、ATM等。
概述
[概述]
附图说明
图1是使用基于硬件的多线程处理器的通信系统的方框图。
图2-1至2-4是图1的基于硬件的多线程处理器的详细方框图。
图3是描述图2的多线程处理器的功能配置的方框图。
图4是描述用于图1处理器的存储器中的数据结构。
图5是描述在图4的表中使用的转发表的格式。
图6是描述通用包转发进程的流程图。
图7是流程图,描述图6的包转发进程的一个可供选择的方面。
详细说明
参考图1,通信系统10包括一并行的、基于硬件的多线程处理器12。基于硬件的多线程处理器12连接至诸如PCI总线14这样的总线、存储系统16和第二总线18。系统10对于能够分解成并行子任务或功能的任务特别有用。具体地说,基于硬件的多线程处理器12对于面向带宽而不是面向等待时间的任务是有用的。基于硬件的多线程处理器12具有多个微引擎22,每个都能同时激活多个独立工作于一个任务的硬件控制的线程,并在其上工作。
基于硬件的多线程处理器12还包括一中央控制器20,它帮助装入用于基于硬件的多线程处理器12的其它资源的微码控制(microcode control),并执行其它通用计算机类型功能,诸如处理协议、异常、对包处理的额外支持,其中微引擎停止包用于诸如在边界条件下的更详细地处理,。在一个实施例中,处理器20是基于Strong Arm的结构。通用多处理器20具有一操作系统。通过操作系统,处理器20可调用函数对微引擎22a-22f起作用。处理器20可使用任何支持的操作系统,更适宜于实时操作系统,诸如Microsoft NTrealtime、VXWorks。
基于硬件的多线程处理器12还包括多个功能微引擎22a-22f。功能微引擎(微引擎)22a-22f各自在硬件中维护多个程序计数器和与程序计数器相关联的状态。事实上,相应的多个线程组能同时在每个微引擎22a-22f上激活,尽管在任一时刻只有一个在实际运行。
在一个实施例中,有六个微引擎22a-22f示出。每个微引擎22a-22f具有处理四个硬件线程的能力。六个微引擎22a-22f用包括存储系统16和总线接口24和28在内的共享资源运行。存储系统16包括同步动态随机存取存储器(SDRAM)控制器26a和静态随机存取存储器(SRAM)控制器26b。SDRAM存储器16a和SDRAM控制器26a一般用于处理大量数据,例如,来自网络包的网络有效负载的处理。在用于较少等待时间、快速存取的任务的网络实现中,使用SRAM控制器26b和SRAM存储器16b,例如,访问查找表、核心处理器20的存储器等等。
六个微引擎22a-22f基于数据的特征访问SDRAM16a,或者SRAM16b。这样,在SRAM中存取较少等待时间、低带宽数据,而等待时间不是很重要r较高带宽数据,则在SDRAM中存取。微引擎22a-22f能够执行对于SDRAM控制器26a或SRAM控制器26b的存储器访问指令。
硬件多线程的优点能由SRAM或SDRAM访问来说明。作为例子,由来自一个微引擎的Thread_0所请求的SRAM访问,将引起SRAM控制器26b起动对SRAM存储器16b的访问。SRAM控制器控制SRAM总线的判优(arbitration),访问SRAM16b,从SRAM16b取出数据,并将数据返回给发请求的微引擎22a-22b。在SRAM访问期间,如果微引擎,例如22a,只有一个能运行的单一线程,该微引擎将休止直至数据从SRAM返回。通过在每个微引擎22a-22f内使用硬件关联交换(hardware context swapping),硬件关联交换使得具有唯一程序计数器的其它关联能够在同一微引擎中执行。这样,另一个线程,例如Thread_1直运行,而同时第一线程,例如Thread_0,等待返回读取数据。在执行期间,Thread_1可访问SDRAM存储器16a。当Thread_1在SDRAM单元上操作、且Thread_0在SRAM单元上操作时,一个新的线程,例如Thread_2,现在能在微引擎22a上运行。Thread_2能运行某个时间量,直到它需要访问存储器或完成一些其它较长等待时间的操作,诸如对总线接口进行访问。因此,处理器12在同时能通过一个微引擎22a完成或者运行总线操作、SRAM操作和SDRAM操作,并在数据路径上具有可用于处理更多工作的另外一个线程。
硬件关联交换还同步任务的完成。例如,两个线程可能达到同一共享资源,例如SRAM。这些独立功能单元的每一个,例如FBUS接口28、SRAM控制器26a和SDRAM控制器26b,当它们完成来自微引擎线程关联之一的所请求任务时,报告返回一个表征操作完成的信号标志。当微引擎接收到这个标志时,微引擎可确定哪个线程打开。
基于硬件的多线程处理器12的一种应用的一个例子是作为网络处理器。作为网络处理器,基于硬件的多线程处理器12与如下列介质访问控制器设备的网络设备相接口,例如,10/100BaseT八进制MAC 13a或千兆以太网设备13b。通常,网络处理器可与接收/发送大量数据的任何类型的通信设备或接口相接口。在网络应用中运行的通信系统10能从设备13a、13b接收多个网络包,并以并行方式处理那些包。用基于硬件的多线程处理器12,可独立地处理每个网络包。使用处理器12的另一个例子是postscript(一种页面描述语言)处理器的打印引擎,或者作为存储子系统即RAID磁盘存储的处理器。还有一个应用是作为匹配引擎。例如在证券行业中,电子交易的出现要求使用电子匹配引擎来匹配买卖双方的订单。这些和其它并行类型的任务能在系统10上完成。
处理器12包括将处理器连接到第二总线18的总线接口28。在一个实施例中,总线接口28将处理器12连接到所谓的FBUS 18(FIFO总线)。FBUS接口28负责控制处理器12并将其与FBUS 18相接口。FBUS 18是64位宽的FIFO总线,目前它作为用于介质访问控制器(Media Access Controller)(MAC)设备的最佳总线而获得接受。
处理器12包括一个第二接口,例如PCI总线接口24,它将驻留在PCI 14总线上的其它系统组件连接至处理器12。PCI总线接口24提供高速数据通路24a至存储器16,例如SDRAM存储器16a。通过这个通路,数据能经由直接存储访问(DMA)传送的,通过PCI总线14快速从SDRAM16a移出。另外,PCI总线接口24支持目标和主(master)操作。目标操作是当总线14上从属设备通过读写访问SDRAM时的操作,读写是作为从属至目标的操作提供服务的。在主操作中,处理器核心20直接发送数据至PCI接口24,或者从PCI接口24直接接收数据。
每个功能单元连接在一条或多条内部总线上。处理器包括AMBA总线,它将处理器核心20连接到存储控制器26a、26c以及下述的AMBA译码器30。处理器还包括专用总线34,它连接微引擎单元到SRAM 26b、AMBA译码器30和FBUS接口28。存储总线38将存储控制器26a、26b连接到总线接口24和28以及存储系统16,存储系统16包括用于启动操作等的闪存。
参考图2-1至2-4,每个微引擎22a-22f包括一个判优器(arbiter),它检查标志以确定要在其上运行的可用线程。来自任何微引擎22a-22f的任何线程都能访问SDRAM控制器26a、SRAM控制器26b或FBUS接口28。存储控制器26a和26b各自包括多个队列,以存储未完成的存储器访问请求。队列或者保持存储器访问的次序或者安排存储器访问以优化存储器带宽。例如,如果thread_0不依赖thread_1或者与thread_1没有关系,则线程1和0没有理由不能不按次序地完成它们对SRAM的存储器访问。微引擎22a-22f将存储器访问请求发到存储控制器26a和26b。微引擎22a-22f用足够的存储器访问请求操作充满了存储子系统26a和26b,使得存储子系统26a和26b成为处理器12操作的瓶颈。
如果存储子系统16被实际上独立的存储请求充满,则处理器12能执行存储器访问排序。存储器访问排序提高可达到的存储器带宽。如下所述,存储器访问排序减少了在访问SRAM时发生的空载时间(dead time)或气泡(bubble)。在对SRAM的存储器访问时,在读与写之间信号线上切换电流方向产生气泡或空载时间,等待电流在将SRAM 16a连接到SRAM控制器26b的导体上稳定。
即,驱动总线上电流的驱动器需要在改变状态前稳定下来。这样,读后面跟着写的重复循环会降低峰值带宽。存储器访问排序允许处理器12组织对存储器的访问,使得长串的读取能够跟着长串的写入。这能用于最小化管线中的空载时间,以有效地达到更接近于最大可用带宽。访问排序帮助保持并行硬件关联线程。在SDRAM上,访问排序允许隐匿从一个存储体(bank)到另一个存储体的预充电。具体地说,如果将存储系统16b组织成奇存储体或偶存储体,在处理器对奇存储体操作的同时,存储控制器能开始预充电偶存储体。如果存储器访问在奇和偶存储体之间交替时,预充电是可能的。通过排序存储器访问来交替对相反存储体的访问,处理器12提高了SDRAM带宽。
FBUS接口28对MAC设备支持的每个端口支持Transmit(发送)和Receive(接收)标志,连同表示什么时候保证服务的Interrupt(中断)标志。FBUS接口28还包括控制器28a,它执行从FBUS 18进来的包的首部处理。控制器28a提取包首部并在SRAM中执行微可编程源/目的/协议的散列查找(用于地址滤波)。如果散列未成功解析,则将包首部送至处理器核心20用于附加的处理。FBUS接口28支持下列内部数据事务:
FBUS单元 (通过AMBA总线) 到/从处理器核心。
FBUS单元 (通过专用总线) 到/从SRAM单元。
FBUS单元 (通过M总线(Mbus)) 到/从SDRAM。
FBUS 18是标准工业总线,并包括数据总线,例如,64位宽和地址的边带控制和读/写控制。FBUS接口28使用一系列输入和输出FIFO的29a-29b提供输入大量数据的能力。从FIFO29a-29b,微引擎22a-22f从SDRAM控制器26a取得数据或命令它将数据从接收FIFO移至FBUS接口28,其中数据来自总线18上的设备。可通过存储控制器26a借助直接存储访问将数据送往SDRAM存储器16a。同样地,微引擎可将数据从SDRAM 26a移至接口28,经由FBUS接口28移出至FBUS 18。
数据功能分布在微引擎中。与SRAM 26a、SDRAM 26b和FBUS 28的连接性是经命令请求的。命令请求可以是存储器请求或FBUS请求。例如,命令请求能将数据从位于微引擎22a的寄存器移至一共享资源中,例如,SDRAM单元、SRAM单元、闪存或某些MAC地址。命令被送至每个功能单元和共享资源。但是,共享资源不需要保持数据的本地缓冲。相反地,共享资源访问位于微引擎内的分布数据。这使得微引擎22a-22f能够有权本地访问数据,而不是为在总线上的访问和对总线的风险竞争判优。由于这个特点,等待微引擎22a-22f内部的数据具有0周期延迟(cycle stall)。
连接例如存储控制器26a和26b的这些共享资源的数据总线,例如AMBA总线30、SRAM总线34及SDRAM总线38,都有足够的带宽,因此没有内部瓶颈。这样,为了避免瓶颈,处理器12具有带宽要求,即为每个功能单元提供至少内部总线最大带宽的两倍。作为例子,SDRAM可以83MHz运行64位宽的总线。SRAM数据总线能具有单独的读和写总线,例如,能够是以166MHz运行的32位宽的读总线和以166MHz运行的32位宽的写总线。本质上就是运行在166MHz的64位,它实际上是SDRAM带宽的两倍。
核心处理器20还能访问共享资源。核心处理器20具有通过总线32到SDRAM控制器26a、到总线接口24和到SRAM控制器26b的直接通信。但是,为访问微引擎22a-22f和位于任何微引擎22a-22f的传送寄存器,核心处理器20经AMBA译码器30通过总线34访问微引擎22a-22f。AMBA译码器30能够物理地驻留在FBUS接口28中,但逻辑上是不同的。AMBA译码器30执行FBUS微引擎传送寄存器单元和核心处理器地址(即AMBA总线)之间的地址翻译,因此核心处理器20能够访问属于微引擎22a-22c的寄存器。
处理器核心20包括一个在五级管线中实现的RISC核心50,它在单个周期中执行一个操作数或两个操作数的单个循环移位,提供乘法支持和32位滚动移位(barrel shift)支持。这个RISC核心50是标准的Strong Arm结构,但为了性能原因它是用五级管线实现的。处理器核心20还包括16千字节的指令高速缓存52、8千字节的数据高速缓存54和预取流缓冲器56。核心处理器20在存储器写和取指令的同时执行算术操作。核心处理器20经ARM定义的AMBA总线与其它功能单元接口。AMBA总线是32位双向总线32。
参考图3,示出多处理器12,执行网络路由功能。在一个例子中,异步传输模式(ATM)、以太网和其它类型的包进入网络接口MAC设备并被送到网络处理器12。这些包是在通用微处理器20或通过PCI总线接口(未示出)连接的另一个处理器上的应用中处理的。为了接收和发送这样的包,在该处理器20或通过PCI总线连接的处理器上运行的应用利用网络堆栈72,网络堆栈72包括网络管理、控制和信令处理器74以管理网络通信。
网络堆栈72和应用运行在控制微引擎的处理器20或另一个连接至PCI总线的处理器中。接收、发送和数据转发的路径表示包通过处理器12的传输。管理控制、信令及网络堆栈72通常不涉及数据转发。实际上,处理器20接收和发送。处理器20生成新的在网络上发送的包。处理器20可在异常情况下涉及数据转发。这包括特别不一般的包,它们可能需要特殊的操作和复杂的处理。
对于数据转发过程,使用微引擎22a-22f。在一些实例中,数据转发可能发生在通用处理器20层面上。信号Init是编程者的接口用于微引擎代码的初始化。信号Fini用于终止(将控制信息放在一已知状态中)。微引擎22a-22f提供快速、存储和转发能力。微引擎使用多层普通查找过程,它用由处理器线程支持的并行硬件来执行验证、分类、策略和过滤。异常和控制包被传递至处理器20,用于在网络堆栈72处理。三重网络堆栈(未示出)可通过PCI端口或设备端口定位在主机的芯片外。这可用来卸载处理器20或集中管理与控制于一处。在一些实施例中,微引擎是紧致的RISC处理器并能具有有限的指令空间。由于这个原因和其它原因,当运行多协议时减少指令代码的大小是所想要的。网络处理器12实现了可用于处理各种协议类型(包括现有的和将来的类型)的普通转发过程,而不超出指令存储器限制。
现在参考图4,示出存储在存储器中转发表(forwarding table)结构90的管理安排80。转发表结构管理80包括一个控制和管理结构82,这个结构82包括网络堆栈接口84和表管理器86。表管理器86管理存储在SRAM中的路由表(routing table)90,并且能包括多个表,诸如在图4中所示,包括第4层连接表(layer 4 connection table)92,第3层目的地表(layer 3 destinationtable)94,第2层网桥表(layer 2 bridge table)96和第2层连接表(layer 2connection table)98。另外,存储在存储器中的数据结构能包括一个包缓冲器100,它被存储在DRAM中。作为包数据转发处理器的微引擎从SRAM中的路由表90检索信息,并存储和转发来自DRAM中包缓冲器的包信息。多个表90是由控制管理处理器20建立的。例如,第2层连接表96能用于ATM虚电路,帧中继连接MPLS标记或者其它低层连接。第2层网桥表96能用于以太网网桥。第3层目的地表94能用于基于目的地IP地址的互联网协议(IP)转发。第4层连接表92能用于基于源与目的地端口、地址和协议的IP转发。所有这些表可能要求解封装或者封装包。
一旦表90以通用常规的方式填充了转发信息,包数据转发处理器能够接收包,执行表查找以获得信息以及按表项所要求的来转换包。控制管理进程为了解封装和封装用普通格式建立表90。
现在参考图5,示出了示例性表项,其子集包括在每个表90中。表项包括下列字段:
转发表格式
解封装标志(decap flag)。表示字节是否从包去除。如果这个标志是肯定,那么要去除的字节数在解封装字节计数(Decap Byte Count)字段中。
解封装至层(Decap To Layer)。这个字段规定首部层的解封装最多至所规定的层。层的长度以及因此解封装是通过语法分析包首部来确定的。
解封装字节计数。这个字段规定要从包的前面移除的字节数。通过调整在包缓冲器中的包起始偏移(packet start offset)来执行解封装。
当前封装(Current Encap)。这个字段规定当前包封装类型的标识符。
封装标志(Encap Flag)。表示是否应该预先挂起(prepend)字节到包。如果这个标志被声明,那么字节数在封装字节计数字段中,并且要被封装的这些字节在封装首部字段中。
封装字节计数(Encap Byte Count)。要预先挂起到包的字节数。
封装首部(Encap Header)。要预先挂起的实际字节数。
下一表类型(Next Table Type)。如果非零,这表示要求进一步的查找。这给出表类型。例如,第3层路由或者第4层连接表类型。第3层路由查找将使用最长前缀匹配查找算法,该算法使用目的地IP地址。第4层连接查找将使用104位散列算法,该算法使用源和目的地地址、源和目的地端口以及协议。
下一表地址(Next Table Addr)。能够存在多个下一表,以及同一类型的多个下一表。这个字段规定表的基本地址。
这些标志通过管理进程得到置位或清零。信令和建立连接是网络系统的一部分,它将确定通过网络的某条路径需要首部改变。能存在多种首部能改变的理由。通常首部改变在协议从一个网络域到另一个改变时使用。
现在参考图6,示出了用于封装/解封装普通协议的过程110。最初,微引擎22a-22f之一从网络接口接收112包。该包包括一或多个后面跟着有效负载的首部。微引擎,例如,22a拷贝包的有效负载部分至DRAM中的包缓冲器,且它可将包放在缓冲区偏移位置上,以便为包转发而预先挂起到包的首部留出空间。这个包的包偏移参数设置为在进入缓冲器偏移位置上确定的缺省值。微引擎读取114包的第一首部并执行第2层查找。第2层查找将读取表第2层网桥表和/或第2层连接表表。这些表将返回各种参数,诸如解封装或封装标志。过程110将确定116解封装或封装标志是否置位。如果解封装或封装标志置位,过程将把解封装字节计数添加118到包起始偏移,并将从包起始偏移中减去120封装字节计数并预先挂起封装字节到该包。过程110通过查看当前读取表中的空白字段来测试122是否有下一表要检查。如果有下一表,则过程110将分析下一首部124,获取并读下一表。过程110继续查看以测试解封装或封装标志是否置位。
但是,如果过程没有确定解封装和封装标志置位(116,上面),它将确定130解封装标志或封装标志是否置位132。如果封装标志置位,它将从起始偏移中减去120封装字节计数,以及预先挂起封装字节到该包。另一方面,如果只置位解封装标志,过程将解封装字节计数加134到缓冲器偏移,且无论如何,将检查下一表。当过程确定在检查表末端时,那么它将以常规方式分类并转发136包。也即,“否”条件表示过程能够分类和转发。转发首部能够让微引擎取到首部并发送它至处理器20或其它地方,因此它能用有效负载重新装配。转发首部还能包括转发包等。
现在参考图7。除了规定从查找表获得的字节分发计数之外,查找表可让解封装将在表中设置的字段分层。这个字段规定应该将包的前面部分解封装最多至某个层。如已知的,包被定义在OSI(开放系统互连)七层网络协议中使用的协议层中。在通过第一层的物理层之后,由网络处理器层看到的第一软件层是第二层,也被称为链路层。通过语法分析拟成为这个包的新起始的层之前的层。确定要解封装的字节的长度。这个长度被加到包起始偏移。
图7示出一个变体,其中在表中未规定解封装长度,但通过读包本身来确定。换句话说,这将是一组能被插入到图6的处理中的例行程序,将来自包的已封装字节计数代替到偏移中。
确定这个偏移的过程140示于图7。过程140包括读表142、确定解封装至包层位144是否已经置位,如果置位,通过分析首部146和将长度加到包起始偏移148来检索要移除的层的长度。如果解封装层没有置位,那么过程简单地跳过。无论如何,此过程能预先挂到结合图6所述的过程中。
解封装至层位的典型用途是规定解封装最多至第3层IP首部。如果包封装是通过ATM网络诸如RFC 1483标准的多协议,则第2层首部长度是通过使用RFC 1483长度规则将层分析成首部本身来确定的。不过,如果包封装是标准IP,则通过按照标准IP层长度规则来确定第2层长度。通过从来自那个端口的预先挂起的定制首部的、其参与的端口类型可知道包封装,或者可从当前封装字段中第一查找表中获得包封装。
不是为每个网络协议定义单独的协议转换,本技术提供一种通用的方法。这个方法节约代码空间和软件开发到上市的时间。在一个可替换的实施例中,能将本技术实现为软件库例行程序,例如,用于解封装/封装的通用软件构造模块,其中消费者能插入其专有的首部封装,并且消费者的销售商不必涉及消费者的当有协议设计。
已描述了许多本发明的实施例。不过,可以理解能作出各种修改而不脱离本发明的精神和范围。因而,其它实施例也在下列权利要求范围内。
Claims (31)
1.一种转发网络包的方法,包括:
读取一表,所述表包含多个标志以确定所述多个标志的哪一个被置位或清零;以及
在包上执行一操作,按照所述标志的值解封装或封装该包。
2.如权利要求1所述的方法,其特征在于,用转发信息填充所述表。
3.如权利要求1所述的方法,其特征在于,所述转发表结构包括一控制和管理结构,所述控制和管理结构包括一网络堆栈接口和表管理器。
4.如权利要求1所述的方法,其特征在于,所述表管理器管理路由表,以及能包括多个表,所述多个表包括一第4层连接表、一第3层目的地表、一第2层网桥表和一第2层连接表。
5.如权利要求1所述的方法,其特征在于,所述表包括一标志和一字段,所述标志表示字节是否应该从包去除的标志,所述字段表示要去除的字节数。
6.如权利要求1所述的方法,其特征在于,所述表包括一字段,所述字段规定首部层的解封装最多到所述规定的层。
7.如权利要求1所述的方法,其特征在于,所述表包括一字段,所述字段规定当前包封装类型的标识符。
8.如权利要求1所述的方法,其特征在于,所述表包括一标志和一字段,所述标志表示字节是否应当预先挂到所述包,所述字段规定要封装的字节数和字节。
9.如权利要求1所述的方法,其特征在于,所述表包括一Next TableType(下一表类型)字段,所述字段表示需要进一步查找以及识别表类型。
10.一种封装/解封装包的方法包括:
接收一包;
读取所述包的第一首部,并执行一第2层查找,读取返回参数的连接表;
确定所述表是否返回解封装或封装标志。
11.如权利要求10所述的方法,其特征在于,如果解封装或封装标志置位,
将解封装字节计数加到包起始偏移,以及从包起始偏移减去封装字节计数;以及
预先挂起封装字节到所述包。
12.如权利要求10所述的方法还包括:
通过查看当前读取表中的空白字段确定是否有要检查的下一表。
13.如权利要求12所述的方法,其特征在于,如果有下一表,
分析下一首部,获取并读取下一表。
14.如权利要求11所述的方法,其特征在于,如果没有置位解封装或封装标志,
确定解封装标志或者封装标志是否置位。
15.如权利要求11所述的方法,其特征在于,如果封装标志置位,
从起始偏移减去封装标志字节计数,以及预先挂起封装字节到该包。
16.如权利要求11所述的方法,其特征在于,如果解封装标志置位,则将解封装字节计数加到缓冲器偏移,以及并检查下一表。
17.如权利要求11所述的方法,其特征在于,所述包包括一个或多个后面跟着有效负载的首部,所述方法还包括:
拷贝所述包的有效负载部分至包缓冲器。
18.如权利要求17所述的方法,其特征在于,所述拷贝可将所述包放在缓冲器偏移处以产生空间,用于为包转发而预先挂到包的任何新的首部。
19.一种用于转发网络包的驻留在计算机可读介质上的计算机程序产品,包括指令以使计算机:
读取一表,所述表包含多个标志以确定所述多个标志的哪一个被置位或清零;以及
在包上执行一操作,按照所述标志的值解封装或封装该包。
20.如权利要求19所述的计算机程序产品,其特征在于,用转发信息填充所述表。
21.如权利要求19所述的计算机程序产品,其特征在于,所述转发表结构包括一控制和管理结构,所述控制和管理结构包括一网络堆栈接口和表管理器。
22.一种用于转发网络包的驻留在计算机可读介质上的计算机程序产品,包括指令以使计算机:
接收一包;
读取所述包的第一首部,并执行一第2层查找,读取返回参数的连接表;
确定所述表是否返回解封装或封装标志。
23.如权利要求22所述的计算机程序产品,其特征在于,如果解封装或封装标志置位,所述计算机程序执行指令以:
将解封装字节计数加到包起始偏移,以及从包起始偏移减去封装字节计数;以及
预先挂起封装字节到所述包。
24.如权利要求22所述的计算机程序产品还包括指令以:
通过查看当前读取表中的空白字段确定是否有要检查的下一表。
25.如权利要求24所述的计算机程序产品,其特征在于,如果有下一表,所述计算机程序执行指令以:
分析下一首部,获取并读取下一表。
26.如权利要求22所述的计算机程序产品,其特征在于,所述包包括了一或多个后面跟着有效负载的首部,所述计算机程序产品还执行指令以:
拷贝所述包的有效负载部分至包缓冲器。
27.如权利要求22所述的计算机程序产品,其特征在于,所述拷贝的指令将所述包放在缓冲器偏移处以产生空间,用于为包转发而预先挂到该包的任何新的首部。
28.一种处理网络包的处理器包括:
一计算机存储介质,存储指令以使计算机:
读取一表,所述表包含多个标志以确定所述多个标志的哪一个被置位或清零;以及
在该包上执行一操作,按照所述标志的值解封装或封装该包。
29.如权利要求28所述的处理器,其特征在于,所述表包含转发信息。
30.一种解封装网络包的方法包括:
读取一表,所述表包含多个标志以确定所述多个标志的哪一个被置位或清零;以及
按照所述标志的值在该包上执行解封装操作。
31.如权利要求30所述的方法,其特征在于,所述表包含转发信息。
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-
2001
- 2001-09-28 US US09/966,349 patent/US7126952B2/en not_active Expired - Fee Related
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2002
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Publication number | Priority date | Publication date | Assignee | Title |
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CN101471817B (zh) * | 2007-12-27 | 2011-11-30 | 华为技术有限公司 | 一种在无连接ip网络中的流量监测方法、系统及设备 |
Also Published As
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KR100647949B1 (ko) | 2006-11-17 |
WO2003030461A1 (en) | 2003-04-10 |
TWI239164B (en) | 2005-09-01 |
CN1593041B (zh) | 2011-06-29 |
US7126952B2 (en) | 2006-10-24 |
EP1430658B1 (en) | 2007-07-04 |
EP1430658A1 (en) | 2004-06-23 |
CA2460530C (en) | 2008-06-17 |
ATE366494T1 (de) | 2007-07-15 |
US20030067934A1 (en) | 2003-04-10 |
DE60221030T2 (de) | 2008-03-20 |
HK1067821A1 (en) | 2005-04-15 |
KR20040019037A (ko) | 2004-03-04 |
DE60221030D1 (de) | 2007-08-16 |
CA2460530A1 (en) | 2003-04-10 |
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