CN1536679A - 半导体结构 - Google Patents

半导体结构 Download PDF

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CN1536679A
CN1536679A CNA031332331A CN03133233A CN1536679A CN 1536679 A CN1536679 A CN 1536679A CN A031332331 A CNA031332331 A CN A031332331A CN 03133233 A CN03133233 A CN 03133233A CN 1536679 A CN1536679 A CN 1536679A
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material layer
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semiconductor material
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CN100446270C (zh
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葛崇祜
王昭雄
黄健朝
李文钦
胡正明
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H—ELECTRICITY
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    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

一种半导体结构，包含具有压缩应力的第一半导体材料层，以及具有伸张应力的第二半导体材料层。利用第一半导体材料层与第二半导体材料层的搭配，可用来调节半导体元件中的通道应力，从而形成受应变的通道。

Description

半导体结构
技术领域
本发明涉及半导体结构，特别涉及受应变的半导体元件。
背景技术
半导体是一种导电能力介于导体与非导体之间的材料，而所谓半导体元件就是以半导体材料所特有的特性所制造出来的电子元件，因为半导体元件属于固态元件(Solid State Device)，其体积可以缩小到很小的尺寸。近来，称为金属氧化半导体(Metal-Oxide-Semiconductor；MOS)的晶体管，因为具有耗电量少并且适合高集成度等优点，在半导体元件中具有广泛的应用。MOS晶体管的基本结构除了具备由金属层、氧化层与半导体层所构成的电容器外，还包含两个位于MOS电容器两旁，其电性与硅基材相反的半导体区：源极(Source)与漏极(Drain)。
MOS可分为n型金属氧化半导体(NMOS)和p型金属氧化半导体(PMOS)，其中NMOS以电子来传输，PMOS以空穴来传输，由于电子在电场下的迁移率比空穴高，所以在同样的设计下，NMOS元件的速度将比PMOS的速度快，因此为了提高元件的操作速度，早期的MOS元件都是以NMOS晶体管为主来设计。
由于半导体元件尺寸的不断缩微(Scaled Down)，使得超大规模集成电路的速度持续地提升。然而，当进入次微米世代，半导体元件的缩微由于不同的物理及技术上限制而变得困难重重。此外，在CMOS电路中，由于空穴迁移率(Hole Mobility)小于电子的迁移率，为了让CMOS中的PMOS及NMOS的电流驱动能够匹配，因此通常将PMOS的面积设计成NMOS的2～3倍。然而，这样的设计使的元件的整合及速度都受到影响。因此，为了要进一步改善集成电路的速度，就必须提出新的元件结构或使用新的材料。
发明内容
为了制造高速度的次微米CMOS元件，因此，本发明的目的为提供一种半导体结构，利用具压缩应力与伸张应力的半导体材料层的搭配，可应用于一般基材或绝缘层上硅晶基材中，借以调整通道应力。
根据以上所述的目的，本发明的半导体结构可包括：具压缩应力的第一半导体材料层，以及堆栈于第一半导体材料层上的具伸张应力的第二半导体材料层。此第一半导体材料层与第二半导体材料层分别具有不同晶格常数，因此会在第一半导体材料层压缩且第二半导体材料层伸张的情况下，借以互相牵制而调整应力。上述半导体可应用于一般无绝缘层的基材或者绝缘层上硅晶基材。
本发明的半导体结构，至少包括：至少一第一半导体材料层；以及至少一第二半导体材料层位于该第一半导体材料层上，其中该第一半导体材料层与该第二半导体材料层具有不同性质的应力，并且该第一半导体材料层与该第二半导体材料层相互堆栈，借以在该第一半导体材料层与该第二半导体材料层分别压缩与伸张或伸张与压缩的情况下，互相牵制造成应变。
将本发明的结构应用在电子元件中，由于可调整通道应力以改善载子迁移率，从而提升现有集成电路技术。
附图简要说明
下面结合附图对本发明的具体实施方式作进一步详细的描述。
附图中，
图1为本发明半导体结构应用于绝缘层上硅基材的剖面示意图；
图2为本发明半导体结构一实施例剖面图；
图3为本发明半导体结构另一实施例剖面图；以及
图4为本发明半导体结构再一实施例剖面图。
具体实施方式
为了制造高速度次微米CMOS元件，必须增加通道的载子迁移率(CarrierMobility)并降低源极与漏极的寄生电容(Parasitic Capacitance)。硅材料中的载子迁移率，特别是空穴迁移率，会因为次微米CMOS元件的应变速率(SwitchingSpeed)的发展限制而非常低。为了克服这样的问题，本发明揭露一种受应变的半导体结构，利用具有不同应力的半导体材料层间的互相影响，以进行通道的应力调整。
本发明揭露一种半导体结构，利用具压缩应力(Compressive Stress)的半导体材料与伸张应力(Tensile Stress)的半导体材料相互堆栈而形成一半导体结构。其中，由于一半导体材料具有压缩应力，而沉积在上的另一半导体材料具有伸张应力，两者的晶格常数并不相同。因此，在一半导体材料压缩且另一半导体材料伸张的情况下，互相牵制而形成张力通道(Strained-Channel)，从而可增加电子或空穴迁移率。
上述的具压缩应力的半导体材料以及具伸张应力的半导体材料都可选自于合金半导体(Alloy Semiconductor)、元素半导体(Element Semiconductor)或是化合物半导体(Compound Semiconductor)材料。一般合金半导体材料例如有锗化硅(SiGe)、镓化硅(SiGa)或碳化硅(SiC)等；元素半导体材料则有硅和锗等等；而化合物半导体则例如有砷化镓(GaAs)、砷铝化镓(GaAlAs)或磷化铟(InP)等分别由III V族或II VI族化合物所构成的半导体材料等。上述材料可互相搭配利用，本发明不限于此。
本发明的半导体结构可先利用具压缩应力或具伸张应力的半导体材料为基材，再将另一具相反应力的半导体材料沉积于其上。或者，可在一般基材或绝缘层上硅基材(Silicon-On-Insulator；SOI)结构上，形成本发明的半导体结构，本发明不限于此。
图1为本发明半导体结构应用于绝缘层上硅基材结构的剖面示意图。请参照图1，绝缘层上硅基材一般由硅基材100以及绝缘层102所构成，并且在绝缘层上具有含硅薄膜层(未绘示)。但是，本发明在此利用第一半导体材料层106以及位于第一半导体材料层106上的第二半导体材料层108，来取代一般的含硅薄膜层。其中，第一半导体材料层106具有压缩应力，而第二半导体材料层108具有伸张应力，由于第一半导体材料层106与第二半导体材料层108的互相影响，从而可调整第一半导体材料层106与第二半导体材料层108中的通道应力。
在本发明较佳实施例中，上述绝缘层102由埋入氧化层所构成，一般为二氧化硅材质，而第一半导体材料层106由锗化硅材料所构成，第二半导体材料层108则由硅材料所构成。并且，第一半导体材料层106与第二半导体材料层108的较佳厚度都小于400。值得注意的是，本发明上述材料与厚度仅为举例，可根据实际产品与所调整的应力值加以改变，本发明不限于此。
另外，当本发明的半导体结构仅使用一般的硅基材100时，第一半导体材料层106则直接位于硅基材100上方，而第二半导体材料层108再位于第一半导体材料层106上。此时，第一半导体材料层会与一主动区域(Active Area)(未绘示)连接，并与硅基材之间，以空气隧道(Air Tunnel)来进行绝缘。
不论上述本发明半导体结构、位于绝缘层上硅基材的结构或位于一般硅基材的结构，都可进行后续制造而形成半导体元件。本发明以数个实施例来进行说明。
在本发明一实施例中，在上述半导体结构中形成数个绝缘区域110，如图2所示。一般来说，这些绝缘区域110可为浅沟渠隔离结构，但这些绝缘区域110位于第一半导体材料层106或第二半导体材料层108中时，可选择让期待有不同的应力，而分别导致这些半导体材料层具有更多的相同应力。例如，当绝缘区域110具有压缩应力，则会导致第一半导体材料层106具有更多的压缩应力；而绝缘区域110具有伸张应力，会导致第二半导体材料层108具有更多的伸张应力。
或者在本发明另一实施例中，还在图2的结构中形成电性与基材100相反的半导体区，源极112与漏极114，如图3所示。并且同样的，如上述的绝缘区域100，若源极112与漏极114具有压缩应力，则会导致第一半导体材料层106具有更多的压缩应力；若源极112与漏极114具有伸张应力，则会导致第二半导体材料层108具有更多的伸张应力。
而在本发明再一实施例中，还在图3的结构上形成例如由含硅化合物所构成的沉积层116等等，如图4所示。也是同样的，若沉积层116具有压缩应力，则会使得第一半导体材料层106具有压缩应力，则会导致第一半导体材料层106具有更多的压缩应力；若沉积层116具有伸张应力，则会导致第二半导体材料层106具有更多的伸张应力。
值得注意的是，上述本发明的半导体结构并非仅限于单一第一半导体材料层与单一第二半导体材料层的相互堆栈，可根据产品或工艺需要而以更多数量相互堆栈而成，本发明不限于此。
本发明的特点在于，以具有压缩应力的材料与具有伸张应力的材料的互相搭配，因此可根据需要而调节所制造的半导体元件的通道应力，从而形成受应变的通道。由于本发明的半导体结构可增加电子或空穴的迁移率，因此不论在NMOS或PMOS晶体管中，都可具有较现有半导体元件高的操作速度。而这些优点，对现有半导体技术来说，实为一大进步。
可以理解的是，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明所附的权利要求的保护范围。

Claims (20)

1、一种半导体结构，至少包括：
至少一第一半导体材料层；以及
至少一第二半导体材料层位于该第一半导体材料层上，其中该第一半导体材料层与该第二半导体材料层具有不同性质的应力，并且该第一半导体材料层与该第二半导体材料层相互堆栈，借以在该第一半导体材料层与该第二半导体材料层分别压缩与伸张或伸张与压缩的情况下，互相牵制造成应变。
2、根据权利要求1所述的半导体结构，其特征在于，上述的第一半导体材料层由合金半导体所构成，并且该第一半导体材料层的材料选自于由锗化硅、碳锗化硅与碳化硅所组成的一族群。
3、根据权利要求1所述的半导体结构，其特征在于，上述的第二半导体材料层由合金半导体所构成，并且该第二半导体材料层的材料选自于由锗化硅、碳锗化硅与碳化硅所组成的一族群。
4、根据权利要求1所述的半导体结构，其特征在于，上述的第一半导体材料层由元素半导体所构成，并且该第一半导体材料层的材料选自于由硅与锗所组成的一族群。
5、根据权利要求1所述的半导体结构，其中上述的第二半导体材料层由元素半导体所构成，并且该第二半导体材料层的材料选自于由硅与锗所组成的一族群。
6、根据权利要求1所述的半导体结构，其特征在于，上述的第一半导体材料层由化合物半导体所构成，并且该第一半导体材料层的材料选自于由砷化镓、砷铝化镓与磷化铟等IIIV族与IIVI族化合物所组成的一族群。
7、根据权利要求1所述的半导体结构，其特征在于，上述的第二半导体材料层由化合物半导体所构成，且该第二半导体材料层的材选自于由砷化镓、砷铝化镓与磷化铟等IIIV族与IIVI族化合物所组成的一族群。
8、根据权利要求1所述的半导体结构，其特征在于，还包括数个绝缘区域。
9、根据权利要求8所述的半导体结构，其特征在于，上述的绝缘区域具有伸张应力，并导致该第一半导体材料层具有更多压缩应力。
10、根据权利要求8所述的半导体结构，其特征在于，上述的绝缘区域具有压缩应力，并导致该第二半导体材料层具有更多伸张应力。
11、根据权利要求1所述的半导体结构，其特征在于，还包括至少一源极区域与至少一漏极区域。
12、根据权利要求11所述的半导体结构，其中上述的源极区域或漏极区域具有伸张应力，并导致该第一半导体材料层具有更多压缩应力。
13、根据权利要求11所述的半导体结构，其特征在于，上述的源极区域或漏极区域具有压缩应力，并导致该第二半导体材料层具有更多伸张应力。
14、根据权利要求11所述的半导体结构，其特征在于，还包括一沉积层位于该源极区域或该漏极区域上，其中该沉积层具有压缩应力，并导致该第一半导体材料层具有更多压缩应力。
15、根据权利要求11所述的半导体结构，其特征在于，还包括一沉积层位于该源极区域或该漏极区域上，其中该沉积层具有伸张应力，并导致该第二半导体材料层具有更多伸张应力。
16、根据权利要求11所述的半导体结构，其特征在于，还包括一硅化合物位于该源极区域或该漏极区域上，其中该硅化合物具有伸张应力，并导致该第一半导体材料层具有更多压缩应力。
17、根据权利要求11所述的半导体结构，其特征在于，还包括一硅化合物位于该源极区域或该漏极区域上，其中该硅化合物具有压缩应力，并导致该第二半导体材料层具有更多伸张应力。
18、根据权利要求1所述的半导体结构，其特征在于，还包括一绝缘层位于该基材与该第一半导体材料层之间。
19、根据权利要求1所述的半导体结构，其特征在于，上述的绝缘层由一埋入氧化层所构成。
20、根据权利要求1所述的半导体结构，其特征在于，上述的第一半导体材料层连接一主动区，并与该基材之间以空气隧道作为绝缘。
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US7029994B2 (en) 2006-04-18
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US20050233552A1 (en) 2005-10-20
US20040195623A1 (en) 2004-10-07

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