CN1519931A - 半导体器件、电子设备及它们的制造方法和电子仪器 - Google Patents

半导体器件、电子设备及它们的制造方法和电子仪器 Download PDF

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Publication number
CN1519931A
CN1519931A CNA2004100032352A CN200410003235A CN1519931A CN 1519931 A CN1519931 A CN 1519931A CN A2004100032352 A CNA2004100032352 A CN A2004100032352A CN 200410003235 A CN200410003235 A CN 200410003235A CN 1519931 A CN1519931 A CN 1519931A
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mentioned
semiconductor
bearing substrate
semiconductor chip
subassembly
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CN100479152C (zh
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泽本俊宏
中山浩久
青栁哲理
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

一种半导体器件、电子设备及它们的制造方法和电子仪器，所述半导体器件通过承载基板(11)上设置的连接台(12c)上分别结合突出电极(26)，(36)，在半导体芯片(13)上分别配置承载基板(21)，(31)的端部，在承载基板(11)上分别安装承载基板(21)，(31)。根据本发明，实现不同种类组件的三维安装结构。

Description

半导体器件、电子设备及它们的制造方法和电子仪器
发明领域
本发明涉及半导体器件、电子设备、电子仪器、半导体器件的制造方法和电子设备的制造方法。尤其适用于半导体组件等的层叠结构中。
背景技术
已有半导体器件中，为实现半导体芯片安装时的空间节省，例如特开平10-284683所示，有边插入同种承载基板边三维安装半导体芯片的方法。
但是，边插入同种承载基板边三维安装半导体芯片的方法中，难以层叠不同种类组件，由于难以层叠不同种类组件，出现节省空间的有效性不高的问题。
发明内容
因此，本发明的目的是提供可实现不同种类组件的三维安装结构的半导体器件、电子设备、电子仪器、半导体器件的制造方法和电子设备的制造方法。
为解决上述问题，根据本发明的一个形态的半导体器件，其特征在于包含：搭载第一半导体芯片的第一半导体组件；端部配置在上述第一半导体芯片上、支持在上述第一半导体组件上的第二半导体组件。
由此，即便第一半导体组件的大小和第二半导体组件的大小不同的情况下，搭载第一半导体芯片的第一半导体组件上可层叠第二半导体组件。因此，即便第一半导体组件和第二半导体组件的种类不同的情况下，可实现三维安装结构，可实现不同种类芯片的层叠，从而可提高节省空间的有效性。
根据本发明的一个形态的半导体器件，其特征在于还包含端部配置在上述第一半导体芯片上、支持在上述第一半导体组件上的第三半导体组件。
由此，可在第一半导体芯片上配置第二半导体组件和第三半导体组件，可在同一第一半导体芯片上配置多个半导体组件，从而可更进一步缩小安装面积。
根据本发明的一个形态的半导体器件，其特征在于上述第二半导体组件和上述第三半导体组件彼此分离。
由此，即便在第一半导体芯片上配置第二半导体组件和第三半导体组件的情况下，从第一半导体芯片产生的热可从第二半导体组件和第三半导体组件之间的间隙中逃离，可提高从第一半导体芯片产生的热的散发性。因此，可抑制第一半导体芯片的可靠性恶化，并且可在同一第一半导体芯片上配置多个半导体组件，可抑制动作不良，并且缩小安装面积。
根据本发明的一个形态的半导体器件，其特征在于上述第二半导体组件和上述第三半导体组件大小、厚度或材质中至少一个不同。
由此，同一半导体芯片上可配置多个不同种类组件，可进一步缩小安装面积，同时可抵消组件之间产生的翘曲，可提高组件之间的连接可靠性。
根据本发明的一个形态的半导体器件，其特征在于上述第二半导体组件和上述第三半导体组件之间的间隙、第一半导体组件和上述第二半导体组件之间的间隙或第一半导体组件和上述第三半导体组件之间的间隙中至少一个间隙中填充有树脂。
由此，由半导体组件之间的间隙中填充的树脂，可缓和半导体组件中产生的应力。因此，可提高多个半导体组件的耐冲击性，即便层叠多个半导体组件时，也可确保半导体组件的可靠性。
根据本发明的一个形态的半导体器件，其特征在于上述第一半导体组件包括倒片安装上述第一半导体芯片的第一承载基板，上述第二半导体组件包括第二半导体芯片、安装上述第二半导体芯片的第二承载基板、结合在上述第一承载基板上并在上述第一半导体芯片上保持上述第二承载基板的突出电极、密封上述第二半导体芯片的密封件。
由此，通过在第一承载基板上结合突出电极，可抑制高度增加，并且可层叠不同种类组件，可缩小安装面积。
根据本发明的一个形态的半导体器件，其特征在于上述第一半导体组件是在上述第一承载基板上倒片安装上述第一半导体芯片的球栅阵列，上述第二半导体组件是模压密封在上述第二承载基板上搭载的上述第二半导体芯片的球栅阵列或芯片大小组件。
由此，使用通用组件的情况下，可层叠不同种类组件，可抑制生产效率恶化，并且缩小安装面积。
另外，根据本发明的一个形态的半导体器件，其特征在于上述突出电极避开上述第一半导体芯片的搭载区域，配置在上述第二承载基板的至少4个角上。
由此，在第一半导体芯片上配置第二半导体组件的端部的情况下，通过调整突出电极的配置位置，都可在第一半导体组件上稳定保持第二半导体组件，可抑制层叠结构的复杂化，并且缩小安装面积。
根据本发明的一个形态的半导体器件，其特征在于上述第一半导体芯片是逻辑运算元件，上述第二半导体芯片是存储元件。
由此，可抑制安装面积的增加，并且实现各种功能，同时可容易实现存储元件的堆叠结构，容易增加存储容量。
根据本发明的一个形态的半导体器件，其特征在于包含：搭载第一半导体芯片的第一半导体组件；端部配置在上述第一半导体芯片上、支持在上述第一半导体组件上的第二半导体芯片。
由此，即便在半导体芯片的种类或大小不同的情况下，可不在第一半导体芯片和第二半导体芯片之间插入承载基板，将第二半导体芯片配置在第一半导体芯片上，将第二半导体芯片倒片安装在第一半导体组件上。由此，可抑制半导体芯片层叠时的高度增加，并且缩小安装面积，可提高节省空间的有效性。
根据本发明的一个形态的半导体器件，其特征在于上述第二半导体芯片包含三维安装结构。
由此，可将多个种类或大小不同的第二半导体芯片层叠在第一半导体芯片上，可具有各种功能，并且实现半导体芯片安装时的节省空间。
根据本发明的一个形态的电子设备，其特征在于包括：搭载电子部件的第一组件；端部配置在上述电子部件上、支持在上述第一组件上的第二组件。
由此，即便第一组件和第二组件种类不同的情况下，也可实现三维安装结构，可实现不同种类部件的层叠，从而可提高节省空间的有效性。
根据本发明的一个形态的电子仪器，其特征在于包括：搭载半导体芯片的第一半导体组件；端部配置在上述半导体芯片上、支持在上述第一半导体组件上的第二半导体组件；安装了上述第二半导体组件的母基板。
由此，可实现搭载半导体芯片的不同种类组件的三维安装结构，可提高电子仪器的功能性，并且实现电子仪器的小型化、轻量化。
另外，根据本发明的一个形态的半导体器件的制造方法，其特征在于包括：在第一承载基板上安装第一半导体芯片的工序；在第二承载基板上安装第二半导体芯片的工序；在上述第二承载基板上形成第一突出电极的工序；上述第二承载基板的端部配置在上述第一半导体芯片上、将上述第一突出电极结合于第一承载基板上的工序。
由此，即便第一承载基板的大小与第二承载基板的大小不同的情况下，通过将第一突出电极结合于第一承载基板，可将第二承载基板层叠在安装了第一半导体芯片的第一承载基板上。因此通过调整第一突出电极的配置位置可层叠不同种类芯片，可抑制制造工序的复杂化，并且提高节省空间的有效性。
另外，根据本发明的一个形态的半导体器件的制造方法，其特征在于还包括：在第三承载基板上安装第三半导体芯片的工序；在上述第三承载基板上形成第二突出电极的工序；第三承载基板的端部配置在上述第一半导体芯片上、上述第二突出电极结合于第一承载基板的工序。
由此，通过调整第一突出电极和第二突出电极的配置位置可在同一半导体芯片上配置多个半导体组件，可抑制制造工序的复杂化，并且进一步缩小安装面积。
另外，根据本发明的一个形态的半导体器件的制造方法，其特征在于还包括：从上述第二承载基板和上述第三承载基板之间的间隙、上述第一承载基板和上述第二承载基板之间的间隙或上述第一承载基板和上述第三承载基板之间的间隙中的至少一个间隙中注入树脂的工序。
由此，可高效地在半导体组件之间的间隙中填充树脂，可将半导体组件之间的间隙变窄。因此，可提高半导体组件的耐冲击性，并且提高半导体组件的安装密度，可确保半导体组件的可靠性，并且缩小安装面积。
另外，根据本发明的一个形态的半导体器件的制造方法，其特征在于还包括：用第一密封件密封安装了上述第二半导体芯片的第二承载基板的工序；用第二密封件密封安装了上述第三半导体芯片的第三承载基板的工序；在使上述第一密封件和上述第二密封件彼此分离的状态下，使上述第一密封件的表面和上述第二密封件的表面与平坦面接触的工序；通过从上述第一突出电极和上述第二突出电极的形成面侧注入树脂，将树脂填充到上述第一密封件和上述第二密封件之间的间隙的工序。
由此，即便在第一承载基板上安装的第二承载基板与第三承载基板彼此分离的情况下，也可将在上部配置的半导体组件的上面平坦化。这样，通过吸附垫可稳定进行半导体垫片的拾取，可将半导体组件高精度地安装到母基板上。
根据本发明的一个形态的电子设备的制造方法，其特征在于包括：在第一承载基板上安装第一电子部件的工序；在第二承载基板上安装第二电子部件的工序；在上述第二承载基板上形成突出电极的工序；上述第二承载基板的端部配置在上述第一电子部件上、上述突出电极结合于第一承载基板的工序。
由此，通过调整突出电极的配置位置，可在第一电子部件上配置第二电子部件，可抑制制造工序的复杂化，并且可缩小安装面积。
附图说明
图1是表示第一实施例的半导体器件的结构的截面图；
图2是表示第一实施例的半导体器件的结构的平面图；
图3是表示第二实施例的半导体器件的制造方法的截面图；
图4是表示第三实施例的半导体器件的制造方法的截面图；
图5是表示第四实施例的半导体器件的结构的截面图；
图6是表示第五实施例的半导体器件的结构的截面图；
图7是表示第六实施例的半导体器件的结构的截面图；
图8是表示第七实施例的半导体器件的结构的截面图；
图9是表示第八实施例的半导体器件的结构的截面图；
图10是表示第九实施例的半导体器件的结构的截面图。
具体实施方式
下面参考附图说明本发明的实施例的半导体器件、电子设备及其制造方法。
图1是表示本发明的第一实施例的半导体器件的结构的截面图，图2是表示本发明的第一实施例的半导体器件的简要结构的平面图。并且，该第一实施例中，在通过ACF结合安装了半导体芯片(或半导体模)的半导体组件PK11上，分别层叠线焊连接堆叠结构的半导体芯片(或半导体模)23a～23c的半导体组件PK12和线焊连接堆叠结构的半导体芯片(或半导体模)33a～33c的半导体组件PK13。
图1中，半导体组件PK11上设置承载基板11，承载基板11的两面上分别形成连接台12a，12c，同时承载基板11内形成内部布线12b。并且，承载基板11上倒片安装半导体芯片13，半导体芯片13上设置有用于倒片安装的突出电极14。并且，半导体芯片13上设置的突出电极14经各向异性导电片15，ACF(Anisotropic Conductive Film)结合于连接台12c上。另外，在承载基板11的背面上设置的连接台12a上，设置用于将承载基板11安装在母基板上的突出电极16。
这里，通过ACF结合把半导体芯片13安装在承载基板11上，使得不需要用于线焊、模压密封的空间，可实现三维安装时的空间节省，并且可实现将半导体芯片13结合在承载基板11上时的低温化，可降低实际使用时的承载基板11的翘曲。
另一方面，半导体组件PK12、PK13上分别设置有承载基板21，31。并且，承载基板21，31的背面上分别形成连接台22a，22a’，32a，32a’，同时承载基板21，31的表面上分别形成连接台22c，32c，承载基板21，31内分别形成有内部布线22b，32b。这里，连接台22a，32a上分别配置突出电极26，36，连接台22a’，32a’不配置突出电极26，36，原样留下来。
并且，承载基板21，31上分别经粘合层24a，34a各自面朝上安装半导体芯片23a，33a，半导体芯片23a，33a分别经导电性线25a，35a各自线焊连接连接台22c，32c。另外，半导体芯片23a，33a上避开导电性线25a，35a分别面朝上安装半导体芯片23b，33b，半导体芯片23b，33b分别经粘合层24b，34b各自固定在半导体芯片23a，33a上，同时分别经导电性线25b，35b各自线焊连接连接台22c，32c。此外，半导体芯片23b，33b上避开导电性线25b，35b分别面朝上安装半导体芯片23c，33c，半导体芯片23c，33c分别经粘合层24c，34c各自固定在半导体芯片23b，33b上，同时分别经导电性线25c，35c各自线焊连接连接台22c，32c。
在承载基板21，31的背面分别设置的连接台22a，32a上，分别设置将承载基板21，31分别保持在半导体芯片13上、分别将承载基板21，31安装在承载基板11上的突出电极26，36。这里，突出电极26，36最好存在于承载基板21，31的至少4个角上。例如图2所示，突出电极26，36按コ字装排列。
由此，承载基板21，31的端部分别配置在半导体芯片13上、承载基板21，31分别安装在承载基板11上的情况下，可在承载基板11上稳定保持承载基板21，31。
另外，通过将未配置突出电极26，36的剩余下来的连接台22a’，32a’分别设置在承载基板21，31上，可调整突出电极26，36的配置位置。因此，即便变更承载基板11上安装的半导体芯片13的种类和大小的情况下，可不变更承载基板21，31的构成，重新配置突出电极26，36，可实现承载基板21，31的通用化。
并且，通过在承载基板11上设置的连接台12c上分别结合突出电极26，36，可将承载基板21，31的端部分别配置在半导体芯片13上，将承载基板21，31分别安装在承载基板11上。由此，可在同一半导体芯片13上配置多个半导体组件PK12，PK13，可缩小安装面积，并且实现不同种类半导体芯片13，23a～23c，33a～33c的三维安装。
这里，作为半导体芯片13，例如是CPU等的逻辑运算元件，作为半导体芯片23a～23c，33a～33c，例如是DRAM，SRAM，EEPROM，闪存储器等的存储元件。由此，可抑制安装面积的增大，并且实现各种功能，同时可容易实现存储元件的堆叠结构，容易增加存储容量。
将承载基板21，31分别安装在承载基板11上的情况下，承载基板21，31的背面可紧密结合于半导体芯片13上，承载基板21，31的背面可离开半导体芯片13。
另外，承载基板21和承载基板31可以是侧壁紧密结合，也可以是侧壁离开。这里，通过紧密结合承载基板21和承载基板31的侧壁，可提高半导体组件PK11上安装的半导体组件PK12，PK13的安装密度，实现节省空间。另一方面，通过分离承载基板21和承载基板31的侧壁，可使半导体芯片13产生的热从半导体组件PK12，PK13之间的间隙逃离，提高半导体芯片13产生的热的散热性。
另外，在半导体芯片23a～23c，33a～33c的安装面侧的承载基板21，31的整个一面上分别设置密封树脂27，37，通过该密封树脂27，37分别密封半导体芯片23a～23c，33a～33c。用密封树脂27，37分别密封半导体芯片23a～23c，33a～33c时，例如可通过利用环氧树脂等的热固化树脂的模压成型等进行。
作为承载基板11，21，31，例如可使用两面基板、多层布线基板、加强基板、带基板或膜基板等，作为承载基板11，21，31的材质，可使用例如聚酰亚胺树脂、玻璃环氧树脂、BT树脂、芳族聚酰胺和环氧树脂的共聚物或陶瓷等。作为突出电极16，26，36，可使用例如用Au块、焊锡材料等覆盖的Cu块，Ni块或焊锡球等，作为导电性线25a～25c、35a～35c，可使用例如Au线、Al线等。上述实施例中，说明了为将承载基板21，31分别安装在承载基板11上，而将突出电极26，36分别安装在承载基板21，31的连接台22a，32a上的方法，但可将突出电极26，36设置在承载基板11的连接台12c上。
上述实施例中，说明了通过ACF结合将半导体芯片13安装在承载基板11上的方法，但可使用例如NCF(非导电膜)结合等的其他粘合剂结合，也可使用焊锡结合和合金结合等的金属结合。另外，说明了将半导体芯片23a～23c，33a～33c分别安装在承载基板21，31上的情况下，使用线焊连接方法，但可将半导体芯片23a～23c，33a～33c倒片安装在承载基板21，31上。另外，上述实施例中，举例说明了在承载基板11上仅安装1个半导体芯片13的方法，但可在承载基板11上安装多个半导体芯片。
图3是表示本发明的第二实施例的半导体器件的制造方法的截面图。该第二实施例中，端部放置在半导体芯片43上、安装在半导体组件PK21上的半导体组件PK22、PK23之间的间隙、半导体组件PK21、PK22之间的间隙和半导体组件PK21、PK23之间的间隙中，注入树脂65。
图3(a)中，半导体组件PK21上设置承载基板41，承载基板41的两面上分别形成有连接台42a，42b。并且，承载基板41上倒片安装半导体芯片43，半导体芯片43上设置用于倒片安装的突出电极44。并且，半导体芯片43上设置的突出电极44经各向异性导电片45，ACF结合在连接台42b。
另一方面，半导体组件PK22，PK23上分别设置承载基板51，61，承载基板51，61的背面上分别形成连接台52，62，连接台52，62上分别设置焊锡球等的突出电极53，63。承载基板51，61上分别安装半导体芯片，安装了半导体芯片的承载基板51，61的整个一面分别用密封树脂54，64密封。承载基板51，61上可安装线焊连接的半导体芯片，可倒片安装半导体芯片，可安装半导体芯片的层叠结构。
并且，半导体组件PK21上分别层叠半导体组件PK22，PK23的情况下，向承载基板41的连接台42b上方供给焊剂焊药(flux)或焊锡膏。
接着如图3(b)所示，在半导体组件PK21上彼此分离地安装半导体组件PK22、PK23，进行回流处理，使得将突出电极53，63分别结合于连接台42b上。
由此，通过调整承载基板51，61上配置的突出电极53，63的配置位置，可在同一半导体芯片43上配置多个半导体组件PK22，PK23，抑制制造工序的复杂化，并且缩小安装面积。另外，通过在半导体组件PK21上分别层叠半导体组件PK22、PK23，可仅选择安装检查过的合格品的半导体组件PK21，PK22，PK23，提高制造成品率。
接着如图3(c)所示，通过从半导体组件PK21，PK22，PK23之间的间隙注入树脂65，将树脂65填充到半导体组件PK21，PK22，PK23之间的间隙中。这里，将树脂65填充到半导体组件PK21，PK22，PK23之间的间隙中时，可从半导体组件PK21和半导体组件PK22之间的间隙、半导体组件PK21和半导体组件PK23之间的间隙、半导体组件PK22和半导体组件PK23之间的间隙中的任何方向注入树脂65。
由此，可有效地将树脂65填充到半导体组件PK21，PK22，PK23之间的间隙中，提高半导体组件PK21，PK22，PK23的耐冲击性。因此，即便突出电极53，63的根基上集中残余应力的情况下，可防止突出电极53，63中诱发裂纹，提高半导体组件PK21，PK22，PK23的可靠性。
接着如图3(d)所示，在设置在承载基板41的背面的连接台42a上，形成用于将承载基板41安装在母基板上的突出电极46。
图4是表示本发明的第三实施例的半导体器件的制造方法的截面图。该第三实施例是将设置有突出电极83，93的半导体组件PK32，PK33反置在底平坦的容器85内并使之分离地配置，从突出电极83，93的形成面侧向半导体组件PK32，PK33之间的间隙中注入树脂95。
图4中，在半导体组件PK31上设置有承载基板71，承载基板71的两面上分别形成有连接台72a，72b。并且，承载基板71上倒片安装半导体芯片73，半导体芯片73上设置有用于倒片安装的突出电极74。并且，在半导体芯片73上设置的突出电极74经各向异性导电片75，ACF结合在连接台72b上。
另一方面，半导体组件PK32、PK33上分别设置承载基板81，91，承载基板81，91的背面上分别形成连接台82，92，连接台82，92上分别设置有焊锡球等的突出电极83，93。另外，承载基板81，91上分别安装有半导体芯片，安装了半导体芯片的承载基板81，91的整个一面分别被密封树脂84，94密封。
并且，如图4(a)所示，将设置了突出电极83，93的半导体组件PK32，PK33反置在底平坦的容器85内并使之分离地配置。而且，从突出电极83，93的形成面侧向半导体组件PK32，PK33之间的间隙中注入树脂95，使树脂95固化。替代容器85可使用低平坦的模子等。
接着，如图4(b)，4(c)所示，在半导体组件PK32，PK33之间的间隙中注入树脂95后，从容器85取出填充了树脂95的半导体组件PK32，PK33。并且，将填充了树脂95的半导体组件PK32，PK33安装在半导体组件PK31上，进行回流处理，从而将突出电极83，93分别结合于连接台72b上。然后，通过经半导体组件PK31，PK32，PK33之间的间隙从侧向注入树脂96，将树脂96填充到半导体组件PK31，PK32，PK33之间的间隙中。
接着，如图4(d)所示，在承载基板71的背面设置的连接台72a上，形成用于将承载基板71安装在母基板上的突出电极76。
由此，即便半导体组件PK32，PK33彼此分离地安装在半导体组件PK31上时，也可将半导体组件PK32，PK33的上面平坦化。因此，通过吸附垫可稳定进行半导体组件PK31，PK32，PK33的安装结构的拾取，可高精度地将半导体组件PK31，PK32，PK33的安装结构安装在母基板上。
另外，图4的实施例中，说明了分别在半导体组件PK32，PK33上形成突出电极83，93后向半导体组件PK32，PK33之间的间隙填充树脂95的方法，但可以是在向半导体组件PK32，PK33之间的间隙填充树脂95后分别在半导体组件PK32，PK33上形成突出电极83，93。
图5是表示本发明的第四实施例的半导体器件的制造方法的截面图。该第四实施例将大小彼此不同的多个半导体组件PK42，PK43安装到半导体组件PK41上。
图5中，半导体组件PK41上设置有承载基板111，承载基板111的两面上分别形成有连接台112a，112b。并且，承载基板111上倒片安装半导体芯片113，半导体芯片113上设置有用于倒片安装的突出电极114。而且，半导体芯片113上设置的突出电极114经各向异性导电片115，ACF结合于连接台112b上。
另一方面，半导体组件PK42、PK43上分别设置有大小彼此不同的承载基板121，131，承载基板121，131的背面上分别形成连接台122，132，连接台122，132上分别设置有焊锡球等的突出电极123，133。另外，承载基板121，131上分别安装半导体芯片，安装了半导体芯片的承载基板121，131的整个一面分别用密封树脂124，134密封。
并且，通过在承载基板111上设置的连接台112b上分别结合突出电极123，133，承载基板121，131的端部分别配置在半导体芯片113上，大小彼此不同的多个半导体组件PK42，PK43安装在半导体组件PK41上。
由此，可将搭载了不同种类芯片的半导体组件PK42，PK43配置在同一半导体芯片113上，缩小安装面积的同时，可抵消半导体组件PK41，PK42，PK43之间产生的翘曲，可提高半导体组件PK41，PK42，PK43之间的连接可靠性。
另外，图5的实施例中，说明了将大小彼此不同的多个半导体组件PK42，PK43安装在半导体组件PK41上的方法，但也可将厚度、材质或形状彼此不同的半导体组件安装在半导体组件PK41上。此外，半导体组件PK41上安装的每个半导体组件PK42，PK43可改变突出电极的配置位置、配置间隔、排列数或配置方法(例如格子排列或岛状排列)等。
图6是表示本发明的第五实施例的半导体器件的结构的截面图。该第五实施例向端部位于半导体芯片213上且安装在半导体组件PK51上的半导体组件PK52，PK53之间的间隙中，注入树脂241。
图6中，半导体组件PK51上设置有承载基板211，承载基板211的两面上分别形成有连接台212a，212b。并且，承载基板211上倒片安装半导体芯片213，半导体芯片213上设置有用于倒片安装的突出电极214。而且，半导体芯片213上设置的突出电极214经各向异性导电片215，ACF结合于连接台212b上。
另一方面，半导体组件PK52、PK53上分别设置承载基板221，231，承载基板221，231的背面上分别形成连接台222，232，连接台222，232上分别设置有焊锡球等的突出电极223，233。另外，承载基板221，231上分别安装半导体芯片，安装了半导体芯片的承载基板221，231的整个一面分别由密封树脂224，234进行密封。
并且，通过在设置于承载基板211上的连接台212b上分别结合突出电极223，233，承载基板221，231的端部分别配置在半导体芯片213上，多个半导体组件PK52，PK53安装在半导体组件PK51上。
另外，向半导体组件PK51上安装的半导体组件PK52、PK53之间的间隙中填充有树脂241。由此，可由树脂241吸收施加在半导体组件PK52，PK53上的应力，提高半导体组件PK52，PK53的可靠性。
另外，向半导体组件PK52、PK53之间的间隙中填充树脂241时，树脂241可溢出到半导体组件PK52、PK53和半导体芯片213之间的间隙中。由此，即便是仅在半导体组件PK52，PK53一端上分别配置突出电极223，233的情况下，可经树脂241分别支撑半导体组件PK52，PK53的另一端，可将半导体组件PK52、PK53稳定安装在半导体组件PK51上。
图7是表示本发明的第六实施例的半导体器件的结构的截面图。该第六施例分割安装半导体组件PK63的下部的半导体组件PK61，PK62。
图7中，半导体组件PK61，PK62上分别设置承载基板311，321，承载基板311，321的背面上分别形成连接台312a，322a，同时承载基板311，321的两面上分别形成有连接台312b，322b。并且，承载基板311，321上分别倒片安装半导体芯片313，323，半导体芯片313，323上设置用于倒片安装的突出电极314，324。而且，半导体芯片313，323上分别设置的突出电极314，324经各向异性导电片315，325分别ACF结合于连接台312b，322b上。
另一方面，在半导体组件PK63上设置承载基板331，承载基板331的背面上分别形成连接台332a，332b，连接台332a，332b上分别设置有焊锡球等的突出电极333a，333b。另外承载基板331上安装半导体芯片，将安装了半导体芯片的承载基板331的整个一面用密封树脂334密封。
并且，通过在承载基板311，321上设置的连接台312b，322b上分别结合突出电极333a，333b，承载基板331配置在半导体芯片313，323上，半导体组件PK63被安装在半导体组件PK61，PK62上。
由此，多个半导体组件PK61，PK62上可配置同一半导体组件PK63，可缩小安装面积，并且实现不同种类芯片的三维安装。
图8是表示本发明的第七实施例的半导体器件的结构的截面图。该第七施例中，半导体芯片421，431的端部分别配置在半导体芯片413上，半导体芯片413，421，431分别倒片安装在承载基板411上。
图8中，在承载基板411的两面上分别形成连接台412a，412c，同时承载基板411内形成有内部布线412b。并且，承载基板411上倒片安装半导体芯片413，半导体芯片413上设置有用于倒片安装的突出电极414。而且，半导体芯片413上设置的突出电极414，经各向异性导电片415，ACF结合于连接台412c上。另外，将半导体芯片413安装在承载基板411上时，除了使用ACF结合的方法，此外也可使用例如NCF结合等的其他粘合剂结合，可使用焊锡结合、合金结合等的金属结合。另外承载基板411背面上设置的连接台412a上设置有将承载基板411安装在母基板上的突出电极416。
另一方面，半导体芯片421，431上分别设置电极垫422，432的同时，以电极垫422，432分别露出的方式分别设置有绝缘膜423，433。并且，电极垫422，433上分别设置有半导体芯片421，431的端部分别保持在半导体芯片413上、分别倒片安装半导体芯片421，431用的突出电极424，434。
这里，突出电极424，434可分别避开半导体芯片413的搭载区域来配置，例如，将突出电极424，434分别按コ字状排列。并且承载基板411上设置的连接台412c上分别结合突出电极424，434，半导体芯片421，431的端部分别配置在半导体芯片413上，半导体芯片421，431分别倒片安装在承载基板411上。
由此，即便在半导体芯片413，421，431的种类或大小不同的情况下，可不在半导体芯片413，421，431之间插入承载基板，将半导体芯片421，431倒片安装在半导体芯片413上。因此，可抑制半导体芯片413，421，431层叠时的高度增加，并且缩小安装面积，提高节省空间的有效性。
另外，将半导体芯片421，431安装在承载基板411上时，半导体芯片421，431可紧密结合于半导体芯片413上，半导体芯片421，431也可从半导体芯片413离开。另外，将半导体芯片421，431安装在承载基板411上时，可使用例如ACF结合、NCF结合等的粘合剂结合，也可使用焊锡结合、合金结合等的金属结合。另外作为突出电极414，416，424，434，例如可使用金块、用焊锡等覆盖的Cu块、Ni块或焊锡球等。此外半导体芯片421，431和承载基板411之间的间隙中可填充密封树脂。
图9是表示本发明的第八实施例的半导体器件的结构的截面图。该第八实施例中，堆叠结构的半导体芯片521a～521c，531a～531c的端部分别配置在半导体芯片513上，堆叠结构的半导体芯片521a～521c，531a～531c倒片安装在承载基板511上。
图9中，承载基板511两面上分别形成连接台512a，512c的同时，承载基板511内形成有内部布线512b。并且，承载基板511上倒片安装半导体芯片513，半导体芯片513上设置有用于倒片安装的突出电极514。而且，半导体芯片513上设置的突出电极514经各向异性导电片515，ACF结合于连接台512c上。此外，将半导体芯片513安装在承载基板511上时，除了使用ACF结合的方法，此外也可使用例如NCF结合等的其他粘合剂结合，可使用焊锡结合、合金结合等的金属结合。承载基板511背面上设置的连接台512a上设置有将承载基板511安装在母基板上的突出电极516。
另一方面，半导体芯片521a～521c，531a～531c上分别设置电极垫522a～522c，532a～532c的同时，各电极垫522a～522c，532a～532c分别露出的方式，分别设置有绝缘膜523a～523c，533a～533c。并且，半导体芯片521a～521c，531a～531c上例如对应各电极垫522a～522c，532a～532c的位置分别形成贯通孔524a～524c，534a～534c，各贯通孔524a～524c，534a～534c内分别经绝缘膜525a～525c，535a～535c和导电膜526a～526c，536a～536c各自形成贯通电极527a～527c，537a～537c。并且分别形成了贯通电极527a～527c，537a～537c的半导体芯片521a～521c，531a～531c分别经贯通电极527a～527c，537a～537c层叠，在半导体芯片521a～521c，531a～531c之间的间隙中分别注入有树脂528a，528b，538a，538b。
并且，半导体芯片521a，531a上分别形成的各贯通电极527a，537a上分别设置有，用于半导体芯片521a～521c，531a～531c的层叠结构的端部分别保持在半导体芯片513上、分别倒片安装半导体芯片521a～521c，531a～531c的层叠结构的突出电极529，539。
这里，突出电极529，539可避开半导体芯片513的搭载区域配置，例如将突出电极529，539分别按コ字状排列。并且承载基板511上设置的连接台512c上分别结合突出电极529，539，通过堆叠结构的半导体芯片521a～521c，531a～531c的端部分别配置在半导体芯片513上，堆叠结构的半导体芯片521a～521c，531a～531c分别倒片安装在承载基板511上。
由此，可不在半导体芯片521a～521c，531a～531c的层叠结构和半导体芯片513之间插入承载基板，将半导体芯片521a～521c，531a～531c的层叠结构分别倒片安装在半导体芯片513上，可抑制层叠时高度增加，并且可层叠多个和半导体芯片种类不同的半导体芯片521a～521c，531a～531c。
将半导体芯片521a～521c、531a～531c的层叠结构安装在承载基板511上时，可使用例如ACF结合、NCF结合等的粘合剂结合，也可使用焊锡结合、合金结合等的金属结合。作为突出电极514、516、529、530，可使用例如金块、用焊锡材料等覆盖的Cu块或Ni块、或焊锡球等。上述实施例中，说明了将半导体芯片521a～521c、531a～531c的3层结构分别安装在承载基板511上的方法，但在承载基板511上安装的半导体芯片的层叠结构可以是2层或4层以上。另外，半导体芯片521a、531a和承载基板511之间的间隙中可填充密封树脂。
图10是表示本发明的第九实施例的半导体器件的结构的截面图。该第九实施例是通过将多个W-CSP(晶片级-芯片大小组件)的端部分别配置在半导体芯片613上，把W-CSP安装在承载基板611上。
图10中，在半导体组件PK71上设置承载基板611，在承载基板611两面上分别形成连接台612a、612c的同时，承载基板611内形成有内部布线612b。并且，承载基板611上倒片安装半导体芯片613，半导体芯片613上设置用于倒片安装的突出电极614。而且，半导体芯片613上设置的突出电极614经各向异性导电片615，ACF结合于连接台612c上。另外，承载基板611背面上设置的连接台612a上设置有用于将承载基板611安装在母基板上的突出电极616。
另一方面，在半导体组件PK72、PK73上分别设置半导体芯片621、631，各半导体芯片621、631上分别设置电极垫622、632的同时，各电极垫622、632分别露出，分别设置绝缘膜623、633。并且，各半导体芯片621、631上，各电极垫622、632分别露出，分别形成应力缓和层624、634，各电极垫622、632上分别形成有在应力缓和层624、634上分别延伸的再配置布线625、635。并且各再配置布线625、635上分别形成焊接抗蚀剂膜626，636，各焊接抗蚀剂膜626，636上在各应力缓和层624，634中分别形成使再配置布线625，635露出的开口部627，637。并且经各开口部627，637分别露出的再配置布线625，635上分别设置有，将半导体芯片621，631的端部分别保持在半导体芯片613上、各半导体芯片621，631分别面朝下安装在承载基板611上的突出电极628，638。
这里，突出电极628、638可避开半导体芯片613的搭载区域配置，例如将突出电极628，638分别按コ字状排列。并且承载基板611上设置的连接台612c上分别结合突出电极628，638，半导体芯片621，631的端部分别配置在半导体芯片613上，从而使半导体组件PK72，PK73分别安装在承载基板611上。
由此，可将W-CSP层叠在倒片安装半导体芯片613的承载基板611上，即便在半导体芯片613，621，631的种类或大小不同的情况下，也不用在半导体芯片613，621，631之间插入承载基板，可将半导体芯片621，631三维安装在半导体芯片613上。因此，可抑制半导体芯片613，621，631层叠时高度增加，并且缩小安装面积，提高节省空间的有效性。
另外，将半导体组件PK72，PK73安装在承载基板611上时，半导体组件PK72，PK73可紧密结合于半导体芯片613，半导体组件PK72，PK73也可从半导体芯片613离开。此外，将半导体组件PK72，PK73安装在承载基板611上时，可使用例如ACF结合、NCF结合等的粘合剂结合，也可使用焊锡结合、合金结合等的金属结合。作为突出电极614，616，628，638，可使用金块、用焊锡等覆盖的Cu块或Ni块、或焊锡球等。
上述的半导体器件和电子设备可适用于例如液晶显示装置、便携电话、便携信息终端、摄像机、MD(Mini Disc)播放器等的电子仪器，可提高电子仪器的性能，并且实现电子仪器的小型化、轻量化。
上述实施例中，举例说明了安装半导体芯片或半导体组件的方法，但本发明不限定于安装半导体芯片或半导体组件的方法，例如可安装弹性表面波(SAW)元件等的陶瓷元件、光调制器和光开关等的光学元件、磁传感器和生物传感器等的各种传感器类等。

Claims (18)

1.一种半导体器件，其特征在于包含：
搭载第一半导体芯片的第一半导体组件；
端部配置在上述第一半导体芯片上、支持在上述第一半导体组件上的第二半导体组件。
2.根据权利要求1所述的半导体器件，其特征在于还包含端部配置在上述第一半导体芯片上、支持在上述第一半导体组件上的第三半导体组件。
3.根据权利要求2所述的半导体器件，其特征在于上述第二半导体组件和上述第三半导体组件彼此分离。
4.根据权利要求2或3所述的半导体器件，其特征在于上述第二半导体组件和上述第三半导体组件大小、厚度或材质中的至少一个不同。
5.根据权利要求3或4所述的半导体器件，其特征在于上述第二半导体组件和上述第三半导体组件之间的间隙、第一半导体组件和上述第二半导体组件之间的间隙或第一半导体组件和上述第三半导体组件之间的间隙中的至少一个间隙中填充树脂。
6.根据权利要求1～5的任意1项所述的半导体器件，其特征在于上述第一半导体组件包括倒片安装上述第一半导体芯片的第一承载基板；上述第二半导体组件包括第二半导体芯片、安装了上述第二半导体芯片的第二承载基板、结合在上述第一承载基板上并在上述第一半导体芯片上保持上述第二承载基板的突出电极、密封上述第二半导体芯片的密封件。
7.根据权利要求6所述的半导体器件，其特征在于上述第一半导体组件是在上述第一承载基板上倒片安装上述第一半导体芯片的球栅阵列，上述第二半导体组件是模压密封在上述第二承载基板上搭载的上述第二半导体芯片的球栅阵列或芯片大小组件。
8.根据权利要求6或7所述的半导体器件，其特征在于上述突出电极避开上述第一半导体芯片的搭载区域，配置在上述第二承载基板的至少4个角上。
9.根据权利要求6至8的任意一项所述的半导体器件，其特征在于上述第一半导体芯片是逻辑运算元件，上述第二半导体芯片是存储元件。
10.一种半导体器件，其特征在于包含：
搭载第一半导体芯片的第一半导体组件；
端部配置在上述第一半导体芯片上、支持在上述第一半导体组件上的第二半导体芯片。
11.根据权利要求6至10的任意一项所述的半导体器件，其特征在于上述第二半导体芯片包含三维安装结构。
12.一种电子设备，其特征在于包括：
搭载电子部件的第一组件；
端部配置在上述电子部件上、支持在上述第一组件上的第二组件。
13.一种电子仪器，其特征在于包括：
搭载半导体芯片的第一半导体组件；
端部配置在上述半导体芯片上、支持在上述第一半导体组件上的第二半导体组件；
安装了上述第二半导体组件的母基板。
14.一种半导体器件的制造方法，其特征在于包括：
在第一承载基板上安装第一半导体芯片的工序；
在第二承载基板上安装第二半导体芯片的工序；
在上述第二承载基板上形成第一突出电极的工序；
上述第二承载基板的端部配置在上述第一半导体芯片上、上述第一突出电极结合于第一承载基板的工序。
15.根据权利要求14所述的半导体器件的制造方法，其特征在于还包括：
在第三承载基板上安装第三半导体芯片的工序；
在上述第三承载基板上形成第二突出电极的工序；
第三承载基板的端部配置在上述第一半导体芯片上、上述第二突出电极结合于第一承载基板的工序。
16.根据权利要求15所述的半导体器件的制造方法，其特征在于还包括：
从上述第二承载基板和上述第三承载基板之间的间隙、上述第一承载基板和上述第二承载基板之间的间隙或上述第一承载基板和上述第三承载基板之间的间隙中至少一个间隙中注入树脂的工序。
17.根据权利要求15所述的半导体器件的制造方法，其特征在于还包括：
用第一密封件密封安装了上述第二半导体芯片的第二承载基板的工序；
用第二密封件密封安装了上述第三半导体芯片的第三承载基板的工序；
在使上述第一密封件和上述第二密封件彼此分离的状态下，使上述第一密封件的表面和上述第二密封件的表面与平坦面接触的工序；
通过从上述第一突出电极和上述第二突出电极的形成面侧注入树脂，将树脂填充到上述第一密封件和上述第二密封件之间的间隙的工序。
18.一种电子设备的制造方法，其特征在于包括：
在第一承载基板上安装第一电子部件的工序；
在第二承载基板上安装第二电子部件的工序；
在上述第二承载基板上形成突出电极的工序；
上述第二承载基板的端部配置在上述第一电子部件上、上述突出电极结合于第一承载基板的工序。
CNB2004100032352A 2003-02-07 2004-02-02 半导体器件、电子设备及它们的制造方法和电子仪器 Expired - Fee Related CN100479152C (zh)

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