CN1503937B - 扩展精度累加器 - Google Patents
扩展精度累加器 Download PDFInfo
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- CN1503937B CN1503937B CN02808633.3A CN02808633A CN1503937B CN 1503937 B CN1503937 B CN 1503937B CN 02808633 A CN02808633 A CN 02808633A CN 1503937 B CN1503937 B CN 1503937B
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
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- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
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- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
- G06F7/724—Finite field arithmetic
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- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
- G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
- G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
- G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA
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- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
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Abstract
Description
Claims (31)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/788,685 | 2001-02-21 | ||
US09/788,685 US7181484B2 (en) | 2001-02-21 | 2001-02-21 | Extended-precision accumulation of multiplier output |
PCT/US2002/004414 WO2002069081A2 (en) | 2001-02-21 | 2002-02-15 | Extended precision accumulator |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1503937A CN1503937A (zh) | 2004-06-09 |
CN1503937B true CN1503937B (zh) | 2013-05-08 |
Family
ID=25145251
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN02808633.3A Expired - Lifetime CN1503937B (zh) | 2001-02-21 | 2002-02-15 | 扩展精度累加器 |
Country Status (6)
Country | Link |
---|---|
US (3) | US7181484B2 (zh) |
EP (1) | EP1374034B1 (zh) |
JP (3) | JP2005505023A (zh) |
CN (1) | CN1503937B (zh) |
DE (1) | DE60226222T2 (zh) |
WO (1) | WO2002069081A2 (zh) |
Cited By (1)
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TWI695315B (zh) * | 2015-05-04 | 2020-06-01 | 南韓商三星電子股份有限公司 | 用於執行除法的設備、方法以及系統單晶片 |
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JP2013080487A (ja) | 2013-05-02 |
EP1374034A2 (en) | 2004-01-02 |
EP1374034A4 (en) | 2006-05-17 |
JP5231336B2 (ja) | 2013-07-10 |
JP2005505023A (ja) | 2005-02-17 |
US20060190519A1 (en) | 2006-08-24 |
DE60226222D1 (de) | 2008-06-05 |
WO2002069081A2 (en) | 2002-09-06 |
WO2002069081A3 (en) | 2002-11-07 |
CN1503937A (zh) | 2004-06-09 |
EP1374034B1 (en) | 2008-04-23 |
US7225212B2 (en) | 2007-05-29 |
US20020178203A1 (en) | 2002-11-28 |
US7181484B2 (en) | 2007-02-20 |
DE60226222T2 (de) | 2009-05-20 |
JP2009266239A (ja) | 2009-11-12 |
US7860911B2 (en) | 2010-12-28 |
US20020116432A1 (en) | 2002-08-22 |
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