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Publication numberCN1492314 A
Publication typeApplication
Application numberCN 02126160
Publication date28 Apr 2004
Filing date1 Dec 1995
Priority date2 Dec 1994
Also published asCN1094610C, CN1173230A, CN1326033C, CN1492315A, CN100412786C, CN101211255A, CN101211255B, CN102841776A, CN102841776B, EP0795153A1, EP0795153A4, EP1265132A2, EP1265132A3, US5802336, US5881275, US6119216, US6516406, US7966482, US8190867, US8495346, US8521994, US8601246, US8639914, US8793475, US8838946, US9015453, US9116687, US9141387, US9182983, US9223572, US9361100, US9389858, US20030115441, US20030131219, US20060236076, US20110093682, US20110219214, US20120198210, US20130117537, US20130117538, US20130117539, US20130117540, US20130117547, US20130124830, US20130124831, US20130124832, US20130124833, US20130124834, US20130124835, WO1996017291A1
Publication number02126160.1, CN 02126160, CN 1492314 A, CN 1492314A, CN-A-1492314, CN02126160, CN02126160.1, CN1492314 A, CN1492314A
InventorsA・皮莱格, A皮莱格, , Y雅列, 门纳梅尔, M米陶尔, LM门纳梅尔, B艾坦
Applicant英特尔公司
Export CitationBiBTeX, EndNote, RefMan
External Links: SIPO, Espacenet
Microprocessor capable of compressing composite operation number
CN 1492314 A
Abstract  translated from Chinese
一个处理器包括用于存储第一压缩数据的第一寄存器(209),解码器(202)和功能单元(203)。 A processor includes a first register for storing the first compressed data (209), the decoder (202) and functional unit (203). 解码器有一个控制信号输入(207),用以接收第一控制信号和第二控制信号。 The decoder has a control signal input (207) for receiving a first control signal and a second control signal. 第一控制信号用以指示压缩操作,而第二控制信号用以指示拆开操作。 The first control signal to indicate the compression operation, while the second control signal is used to open the operating instructions. 功能单元连接到解码器(202)和寄存器(209)上。 Functional unit connected to the decoder (202) and register (209). 功能单元除执行移动操作外还使用第一压缩数据执行压缩操作和拆开操作。 In addition to the functional units move operation also uses the first compressed data to perform compression operations and open operations.
Claims(49)  translated from Chinese
1.一种方法,包括:接收第一指令,所述第一指令包括一个操作码字段,一个第一字段表示具有第一组多个数据元的第一操作数,一个第二字段表示具有第二组多个数据元的第二操作数,第一组多个数据元和第二组数据元的每个第一数据元的长度是N/2比特;响应于所述第一指令存储长度为至少N比特的第一压缩数据到目标位置,所述第一压缩使用包括每个第一组多个数据元和每个第二组多个数据元的反转形式,每个所述反转形式是长度小于N比特的多比特数据元。 1. A method, comprising: receiving a first instruction, the first instruction includes a first operand opcode field, a first field having a first plurality of data representation element, and a second field represents a first two sets of a plurality of data elements of the second operand, the length of each of the first data element of the first plurality of data elements and a second set of data elements is N / 2-bit; in response to the first instruction memory length at least N bits of the first compressed data to the target location, the first compressed using include each of the first plurality of data elements and each of the second plurality of data elements in the reverse form, each of said reverse form is shorter than N-bit multi-bit data elements.
2.根据权利要求1的方法,其中所述第一指令是压缩指令。 2. A method according to claim 1, wherein said first instruction is a compressed instruction.
3.根据权利要求1的方法,其中还包括步骤:用所述第一压缩数据覆盖所述第一操作数的第一组多个数据元。 3. The method of claim 1, further comprising the step of: using a first plurality of the first compressed data covering the first operand data element.
4.根据权利要求1的方法,其中每个所述反转形式的长度是N/2比特。 4. The method according to claim 1, wherein each of said inverted form of length N / 2 bits.
5.根据权利要求4的方法,其中每个所述反转形式包括各个数据元的N/2个最低有效位。 5. The method according to claim 4, wherein each of said inverted form of each data element of N / 2 least significant bits.
6.根据权利要求4的方法,其中存储所述数据元的反转形式的步骤包括:如果没有达到饱和,则复制所述数据元的多个比特;如果达到饱和,则使用有符号的饱和箝位从所述数据元产生所述反转形式。 6. The method according to claim 4, wherein the data storage element comprises inverted form: If not reached saturation, the copying of a plurality of bits of the data element; if saturated, unsaturated signed using forceps generation is the reverse of the data elements from.
7.根据权利要求4的方法,其中存储所述数据元的反转形式的步骤包括:如果没有达到饱和,则复制所述数据元的多个比特;如果达到饱和,则使用没有符号的饱和箝位从所述数据元产生所述反转形式。 7. The method according to claim 4, wherein the data storage element comprises inverted form: If not reached saturation, the copying of a plurality of bits of said data elements; if it reaches saturation, using unsigned saturation clamp generation is the reverse of the data elements from.
8.根据权利要求1的方法,其中存储一个数据元的反转形式的步骤包括:判断所述数据元的值是否在一个反转形式之外;如果所述数据元的值在一个反转形式之外,设置所述反转形式到一个箝位值;如果所述数据元的值不在一个反转形式之外,则防止所述数据元的多个比特以形成所述反转形式。 If the value of the data element in the form of an inverted; determining whether the value of the data element in the form of an inverted outside: 8. The method according to claim 1, wherein the storage of a data element comprises inverted form outside, set the reverse of a clamp value; if the value of the data element is not in a form other than reverse, then prevent multiple bits of the data elements to form the inverted form.
9.根据权利要求8的方法,其中每个反转部分代表一个16比特的字数据和每个数据元代表一个32比特的双字数据。 9. A method according to claim 8, wherein each section represents a reversal of the 16-bit data words and each data element representing a 32-bit double-word data.
10.根据权利要求8的方法,其中使用有符号的饱和箝位驱动每个反转形式。 10. The method according to claim 8, wherein saturated inversion driving each clamping signed form.
11.根据权利要求2的方法,其中每个反转形式代表一个8比特字节数据。 11. The method according to claim 2, wherein each of the inverted form of the data represents one 8-bit byte.
12.根据权利要求11的方法,其中每个数据元代表一个16比特的字数据。 12. The method according to claim 11, wherein each data element represents a 16-bit data word.
13.根据权利要求11的方法,其中使用有符号的饱和箝位驱动每个反转形式。 13. The method according to claim 11, wherein the use of saturated inversion driving each clamping signed form.
14.根据权利要求8的方法,其中使用没有符号的饱和箝位驱动每个反转形式。 14. The method according to claim 8, wherein there is no sign of saturation clamp inversion driving each form.
15.根据权利要求2的方法,其中还包括:用每个第一组多个数据元的反转形式覆盖第一组多个数据元的一个或者多个低阶数据元。 15. The method according to claim 2, further comprising: covering a first plurality of data elements or data element with a plurality of low-level inversion form each of the first plurality of data elements.
16.根据权利要求15的方法,其中还包括:用每个第二组多个数据元的反转形式覆盖第一组多个数据元的一个或者多个高阶数据元。 16. The method of claim 15, further comprising: using the reverse of each of the second plurality of data elements covering one or more of the first plurality of data elements of the higher-order data elements.
17.根据权利要求2的方法,其中所述目标操作数是由所述压缩指令的第一字段表示的。 17. The method according to claim 2, wherein the destination operand is a field of the first instruction in the compressed representation.
18.根据权利要求17的方法,其中所述压缩指令包括3个或者更多个字节,所述第一字段是所述3字节压缩指令的第三-第五比特构成的,其中第二字段是所述3字节压缩指令的第0-第2比特构成的。 18. The method according to claim 17, wherein the compressed instruction includes three or more bytes, the first field is the 3-byte instruction compressed third - fifth bit configuration, wherein the second Fields is the first 3-byte compressed instruction 0- second bit configuration.
19.根据权利要求4的方法,其中所述第一组多个数据元包括第一操作数第一数据元和与所述第一操作数第一数据元相邻的第一操作数第二数据元,所述第二组多个数据元包括第二操作数第一数据元和与所述第二操作数第一数据元相邻的第二操作数第二数据元,其中存储第一压缩数据的步骤包括:响应于第一指令,将从第一操作数第一数据元推导得出的一个目标第一数据元存储在第一目标位置部分;响应于第一指令,将从第一操作数第二数据元推导得出的一个目标第二数据元存储在与所述第一目标位置部分相邻的第二目标位置部分;响应于第一指令,将从第二操作数第一数据元推导得出的一个目标第三数据元存储在第三目标位置部分;响应于第一指令,将从第二操作数第二数据元推导得出的一个目标第四数据元存储在与所述第三目标位置部分相邻的第四目标位置部分。 19. The method of the first operand of claim 4, wherein said first plurality of data elements comprises a first operand data element of the first operand and the first element adjacent to the first data and the second data Yuan, said second plurality of data elements includes a second operand of the first data element and the second operand first data element adjacent second operand second data element, which stores the first compressed data comprises: in response to a first instruction, the first operand from the first data element to derive a target derived data element is stored in a first position a first portion of the target; in response to a first instruction, from the first operand second data element of a target deduced second data element stored in the first target position adjacent to the part of the second portion of the target position; in response to the first instruction, the second operand from the first data element is derived In the third part of the target position of a target drawn third data element is stored; in response to the first instruction, the second from the second operand data element deduced a goal fourth data element stored in the third target position adjacent to the fourth part part of the target location.
20.一种装置,包括:接收第一指令的解码器,所述第一指令代表具有第一组多个数据元的第一操作数和具有第二组多个数据元的第二操作数,所述第一组多个数据元和第二组多个第二数据元中每一个的长度是N比特;与所述解码器耦接的一个功能单元,响应于所述解码器解码的第一指令,存储长度为2N比特的第一压缩数据,所述第一压缩数据包括含有对应于第一组多个数据元和第二组多个数据元中的每一个的反转的数据元的多个反转数据元,每个反转数据元是长度小于N比特的多比特元。 20. An apparatus, comprising: receiving a first instruction decoder, the first instruction having a first operand on behalf of a first group of the plurality of data elements and a second operand having a second plurality of data elements, said first plurality of data elements and a second plurality of data elements in each of the second length is N bits; a functional unit coupled to the decoder, in response to said first decoder decodes instructions, memory length of the first compression 2N bits of data, comprising the first compressed data includes a first plurality of data elements and a second plurality of data corresponding to the elements of each of the inverted data elements more a reverse data elements, each data element is shorter than inverted N-bit multi-bit elements.
21.根据权利要求20的装置,其中所述第一指令是压缩指令。 21. The apparatus of claim 20, wherein said first instruction is a compressed instruction.
22.根据权利要求20的装置,其中所述第一组多个数据元包括第一操作数第一数据元和第一操作数第二数据元,所述第二组多个数据元包括第二操作数第一数据元和第二操作数第二数据元,其中所述功能单元响应于所述第一指令在一个目标操作数的连续相邻的部分存储用于第一操作数第一数据元的反转数据元、用于第一操作数第二数据元的反转数据元、用于第二操作数第一数据元的反转数据元、用于第一操作数第二数据元的反转数据元。 22. The apparatus of claim 20, wherein said first set of data elements comprises a first plurality of a first operand data element and the second data element of the first operand, the second set comprising a second plurality of data elements operand first data element and the second operand second data element, wherein the functional unit in response to the first instruction in a destination operand of a continuous portion adjacent to the first operand storing the first data element The inverted data element, for the first operand data element inverted second data element for the second operand data element inverted first data element, for the first operand data element second counter transfer data elements.
23.根据权利要求22的装置,其中所述们操作数是由第一操作数限定的,其中所述功能第一覆盖所述第一组多个数据元。 23. The apparatus of claim 22, wherein said they operand is defined by a first operand, wherein the first function of covering the first plurality of data elements.
24.根据权利要求20的装置,其中所述功能单元用于在一个目标操作数中按第一操作数中的顺序彼此相邻地写入用于每个第一组多个数据元的反转元和在所述目标操作数中按第二操作数中的顺序彼此相邻地写入用于每个第二组多个数据元的反转元。 24. The apparatus of claim 20, wherein the functional unit is used in a destination operand by the first operand is written sequentially adjacent to each other for inverting each of the first plurality of data elements Yuan and the destination operand by the second operand is written sequentially adjacent to each other for each of the second plurality of data elements is reversed yuan.
25.根据权利要求21的装置,其中所述压缩指令具有包含3个或者更多个字节的整数操作码格式,所述3字节的第三字节允许一个第一3字节源目标寄存器地址和一个第二3字节源寄存器地址。 25. The apparatus of claim 21, wherein the compression comprises instructions having three or more byte integer opcode format, the third byte of the three bytes of the first 3-byte source allows a target register 3-byte address and a second source register address.
26.根据权利要求25的装置,其中所述第一操作数对应于第一3字节源寄存器地址。 26. The apparatus of claim 25, wherein the first operand corresponding to a first source register address of 3 bytes.
27.根据权利要求25的装置,其中所述第二操作数对应于第二3字节源目标寄存器地址。 27. The apparatus of claim 25, wherein the second operand corresponding to the second 3-byte source address of the destination register.
28.根据权利要求20的装置,其中所述功能单元,用于在所述数据元的值在一个反转数据元范围之外时产生用于所述数据元的反转数据元的一个箝位值,且在所述数据元的值在所述反转数据元范围之内时,则复制所述数据元的多个比特以产生所述反转数据元。 28. A clamping device according to claim 20, wherein the functional unit for generating the data for a reversal is outside the range of the data element values of meta data element inverted data element value, and the value of the data elements in the data at the time of the reversal in the dollar range, then copy the data element of a plurality of bits to generate the inverted data element.
29.根据权利要求21的装置,其中还包括:一个保持压缩指令的存储器,所述压缩指令具有包含三个或者更多个字节的整数操作码的格式,所述三个字节之一允许一个第一3字节源目标寄存器地址和一个第二3字节源寄存器地址;和一个保持一个软件的存储装置,所述软件向所述存储器提供所述压缩指令以供执行。 29. The apparatus of claim 21, further comprising: an instruction memory holding compressed, the compressed instruction format having comprising three or more byte integer opcode, one of the three bytes allowed a first 3-byte source address and a second target register 3-byte source address register; and a storage device holding a piece of software, the software provided to the memory of the compression instruction for execution.
30.一种微处理器,包括:保持第一压缩数据的第一源寄存器,所述第一压缩数据具有包含第一压缩数据元和第二压缩数据元的第一组多个压缩数据,每个第一压缩数据元和第二压缩数据元的长度是N比特;保持第二压缩数据的第二源寄存器,所述第二压缩数据具有包含第三压缩数据元和第四压缩数据元的第二组多个压缩数据,每个第三压缩数据元和第四压缩数据元的长度是N比特;被耦接的电路,用于从第一源寄存器接收第一压缩数据和从第二源寄存器接收第二压缩数据,并响应于一个压缩指令以通过压缩第一压缩数据元和第二压缩数据元的第一部分到目标寄存器中和压缩第三数据元和第四数据元的第二部分到目标寄存器中来压缩所述第一压缩数据和所述第二压缩数据,每个第一和第二部分的长度是N/2比特。 30. A microprocessor, comprising: maintaining a first compressed data of the first source register, the first compressed data element having a compressed data comprising a first and a second compressed data element of the first plurality of compressed data, each the length of a first compressed data element and the second element of the compressed data is N bits; second compressed data holding a second source register, the second compressed data having a compressed data comprises a third element and the fourth element of the first compressed data two sets of a plurality of compressed data, the compressed data of each third element and the fourth compression data element length is N bits; circuit being coupled for receiving a first compressed data from the first source register and a source register from the second receiving a second compressed data, and in response to a compression instruction to compress data by compressing the first element and the second element of the first part of the compressed data to the destination register and the third compressed data elements and data elements of the second part of the fourth to target register to compress the first compressed data and the second compressed data, each of the first length and the second part is N / 2 bits.
31.根据权利要求30的微处理器,其中所述第一压缩数据元的第一部分被压缩到目标寄存器的低阶数据元,所述第四压缩数据元的第二部分被压缩到目标寄存器的高阶数据元。 31. The microprocessor according to claim 30, wherein the first portion of the first compressed data element is compressed to target low-level register data element, the fourth element of the second part of the compressed data is compressed to the destination register higher-order data elements.
32.根据权利要求31的微处理器,其中所述第二压缩数据元的第一部分被压缩到目标寄存器中与第三压缩数据元的第二部分相邻的地方。 32. The microprocessor according to claim 31, wherein the first portion of the second compressed data element is compressed to the destination register and the third element of the second part of the compressed data adjacent areas.
33.根据权利要求30的微处理器,其中所述目标寄存器是第一源寄存器,所述第一源寄存器的至少一部分被所述第三压缩数据元的第二部分覆盖。 33. A microprocessor according to claim 30, wherein the target register is a first source register, at least a portion of the first source register is the second portion covers the third compression data elements.
34.根据权利要求33的微处理器,其中所述第一源寄存器的至少一部分通过压缩第二压缩数据元的第一部分而被覆盖,其中第一部分和第二部分对应于每个数据元的相同部分的比特。 34. The same microprocessor according to claim 33, wherein at least a portion of the first source register by compressing the second compressed data element is covered by a first portion, wherein the first portion and a second portion corresponding to each data element bit portion.
35.根据权利要求30的微处理器,其中所述压缩指令具有包含三个或者更多个字节的整数操作码的格式,所述三个字节之一允许一个识别第一源寄存器的第一3比特源目标寄存器地址。 35. A microprocessor according to claim 30, wherein the compressed instruction format having integer opcode comprises three or more bytes, one of the first three bytes allow an identification of the first source register a 3-bit source destination address.
36.根据权利要求35的微处理器,其中所述第一3比特寄存器地址还识别目标寄存器。 36. A microprocessor according to claim 35, wherein said first 3-bit register address also identifies the destination register.
37.根据权利要求36的微处理器,其中所述第一3字节寄存器地址是所述3个或者更多个字节的第三字节的第三-第五比特。 37. A microprocessor according to claim 36, wherein said first address register 3 is the third byte of the three bytes or more third byte - the fifth bit.
38.根据权利要求37的微处理器,其中所述3个或者更多个字节的第三字节表示识别第二源寄存器的第二3比特寄存器地址,所述第二3比特寄存器地址位于所述3个或者更多个字节的第三字节的第0-第2比特。 38. A microprocessor according to claim 37, wherein said three or more bytes of the third byte indicates a second source register to identify a second 3-bit register address, the second 3-bit register address is located The three or more bytes of the first byte of the third second bit 0-.
39.根据权利要求37的微处理器,其中所述电路通过在没有达到饱和时复制所述数据元的预定部分的比特和在达到饱和时使用有符号的饱和箝位来压缩数据元的第一和第二部分。 39. The microprocessor according to claim 37, wherein the circuit by copying bits of a predetermined portion of the data elements in the absence of the use of saturated and unsaturated signed on reaching saturation clamp to compress the data elements of the first and a second portion.
40.根据权利要求37的微处理器,其中所述电路通过在没有达到饱和时复制所述数据元的预定部分的比特和在达到饱和时使用没有符号的饱和箝位来压缩数据元的第一和第二部分。 40. The microprocessor according to claim 37, wherein the circuit by copying bits of a predetermined portion of the data elements in the absence of the use of saturated and there is no sign of saturation is reached saturation clamped to compress the data elements of the first and a second portion.
41.一个包含机器可读媒质的物体,所述媒质包含表示一个指令的数据,所述指令在被所述机器执行时使所述机器执行以下的操作:从含有N比特元A1和A2的第一MN比特压缩数据源和含有N比特元B1和B2的第二MN比特压缩数据源产生第一N/2比特结果,包括A1的任选饱和第一部分和B1的任选饱和第二部分;在MN比特的目标中存储第一组N/2比特结果。 41. A machine-readable medium that contains the object, said medium comprising an instruction data indicates, the instructions cause the machine to perform the following operations when executed by the machine: the first element comprises N bits A1 and A2 an M N bits of compressed data element source containing N bits B1 and B2 of the second M N-bit source generating a first compressed data N / 2-bit results, including optionally saturated, optionally saturated section A1 and B1 of the first portion Second part; storing a first set N / 2-bit result in M N bits objectives.
42.根据权利要求41的物体,其中所述多个操作包括:产生第二组N/2比特结果,包括A2的任选饱和第一部分和B2的任选饱和第二部分;和在MN比特的目标中存储第二组N/2比特结果作为压缩数据。 42. The object according to claim 41, wherein said plurality of operations comprising: generating a second set of N / 2-bit result, a first portion comprising an optionally unsaturated and optionally saturated A2 B2 of the second portion; and a M N bits are stored in the second set of target N / 2-bit data as a result of compression.
43.根据权利要求42的物体,其中所述多个操作还包括:从所述指令标明的结构寄存器访问第一MN比特数据源;用第一和第二组N/2比特结果覆盖所述指令识别的结构寄存器中的第一MN比特压缩数据源的至少一部分。 43. The object according to claim 42, wherein said plurality of operations further comprising: instruction from the first access register structure indicated M N bit data sources; used for covering the first and second set of N / 2-bit results said instruction to identify a first configuration register M N bits at least part of the compressed source data.
44.根据权利要求42的物体,其中所述第一MN压缩数据源还包括另外的N比特元A3、A4,所述第二MN压缩数据源还包括N比特元B3、B4;且其中所述操作还包括:产生第三组N/2比特结果,包括A3的任选饱和第一部分和B3的任选饱和第二部分;产生第四组N/2比特结果,包括A4的任选饱和第一部分和B4的任选饱和第二部分;存储所述第三和第四组N/2比特结果作为MN比特目标中的压缩数据元。 44. The object according to claim 42, wherein said M N first compressed data source further comprises an additional N-bit cell A3, A4, the M N second compressed data element source further comprises N bits B3, B4; and wherein said operations further comprising: generating a third set of N / 2-bit results, including a first portion A3 optionally saturated and optionally a second portion of saturated B3; generating a fourth set of N / 2-bit results, including any of A4 selected from saturated, optionally, a first portion and a second portion of saturated B4; storing said third and fourth set of N / 2-bit M N bits as a result of compression target data element.
45.根据权利要求41的物体,其中所述第一和第二部分的每一个是由有符号的饱和箝位任选饱和的。 45. The object according to claim 41, wherein said first and second portions each of which is signed by the clamping optionally saturated saturated.
46.根据权利要求41的物体,其中所述第一和第二部分的每一个是由没有符号的饱和箝位任选饱和的。 46. The object according to claim 41, each of the symbols is not saturated, optionally, wherein said first clamping portion and a second saturated.
47.一种计算机系统,适于处理数字运动视频信号,包括:一个存储器,用于存储由第一组M个压缩N比特数据元构成的MN比特的第一MN比特数据,和由第二组M个压缩N比特数据元构成的MN比特的第二MN比特数据;一个与所述存储器耦接的处理器,用于访问是第一和第二MN比特数据,和响应于具有第一格式的指令产生第三组2M个压缩的N/2比特结果,所述第一格式可操作以识别对应于第一MN比特数据的第一源和对应于第二MN比特数据的第二源,对应于来自对应的第一和第二组M压缩N比特数据元的2M饱和N/2比特数据的第三组2M个压缩的N/2比特结果;一个与所述处理器耦接的总线,用于发送输入信号到处理器和从处理器发送输出信号;一个将所述总线与一个或者多个视频装置耦接的接口,所述视频装置选自由视频数字化装置、视频采集装置、网络电缆和视频记录装置组成的组中;和一个与所述总线耦接的光盘驱动器,用于接收能存储数字运动视频数据的光盘。 47. A computer system adapted for processing a digital motion video signal, comprising: a memory for storing a first group of M N-bit data element constituting the compressed M N bits of the first M N bit data, and compressed by the second group of M N-bit data element M N bits of the second M N bit data constituted; a processor coupled to the memory, for accessing the first and the second M N bits data, and in response to an instruction having a first format to produce a third set of compression of 2M N / 2-bit result, the first format is operable to identify a first source corresponds to a first M N-bit data corresponding to the The third group 2M compression of N N second source of the second M-bit data corresponding to the first and second sets of M from the corresponding N-bit compressed data elements 2M saturated N / 2-bit data / 2-bit results ; a processor coupled to said bus, for transmitting an input signal to the processor and transmitting an output signal from the processor; a bus with the one or more video devices coupled to the interface, the video device is selected from the group consisting of a video digitizer, a video capture device, a network cable and consisting of a video recording apparatus; and an optical disk drive coupled to said bus for receiving a digital motion video data can be stored in the disc.
48.根据权利要求47的计算机系统,其中所述第一和第二部分的每一个是由有符号的饱和箝位任选饱和的。 48. The computer system of claim 47, wherein said first and second portions each of which is signed by the clamping optionally saturated saturated.
49.根据权利要求47的物体,其中所述第一和第二部分的每一个是由没有符号的饱和箝位任选饱和的。 49. The object according to claim 47, wherein each of said first and second portions are clamped by the unsigned saturation optionally saturated.
Description  translated from Chinese
可以对复合操作数进行压缩操作的微处理器 Composite operands can compress operation microprocessor

发明领域本发明包括使用单个控制信号处理多个数据元素而执行操作的一种装置和方法。 Field of the Invention The present invention includes an apparatus and method for performing the operation using a single control signal process multiple data elements. 本发明允许对压缩数据类型执行移动、压缩和拆开的操作。 The present invention allows the implementation of mobile data type of compression, compression and disassembly operations.

背景技术 Background

当今,大多数个人计算机系统的工作机制是使用一个指令产生一个结果。 Today, most personal computer systems working mechanism is to use a command to produce a result. 通过增加指令的执行速度和处理器指令的复杂程度以及并行执行多个指令来增加处理器性能,这种计算机称为复杂指令集计算机(CISC)。 By increasing the complexity of the instruction execution speed and processor instructions and to execute multiple instructions in parallel to increase processor performance, such computer called complex instruction set computer (CISC). 例如加里福尼亚州Santa Clara的INTEL公司的INTEL80386TM微处理器就属于CISC类型的处理器。 For example, California's Santa Clara's INTEL80386TM INTEL microprocessor belongs to CISC type processors.

先前的计算机系统结构经过优化以利用CISC概念。 Previous computer system architecture has been optimized to take advantage of CISC concept. 这样的系统通常具有32位宽的数据总线。 Such systems typically have a 32-bit wide data bus. 然而,针对计算机支持的协作(CSC-电话会议与混合媒体数据操作集成)、2维/3维图像、图像处理、视频压缩/解压、识别算法和音频处理方面的应用增加了对更高性能的需求。 However, for computer-supported cooperative (CSC- conference call with mixed media data manipulation integration), 2-D / 3-D graphics, image processing, video compression / decompression, recognition algorithms and audio processing applications increased respect for higher performance needs. 但是,执行速度和指令复杂性的增加只是一种解决方案。 However, the execution speed and complexity increase instruction is a solution.

这些应用的一个共同的特征是它们常常操作大量的数据,其中只有少数位是重要的。 A common feature of these applications is that they often operate large amounts of data, which only a few bits are important. 也就是说,是有关位用比数据总线大小少得多的位表示的数据。 In other words, the data on the data bus size bit used much less than the bits. 例如,处理器的许多操作是就8位和16位数据执行的(例如视频图像中的像素彩色分量),但是具有宽得多的数据总线和寄存器。 For example, many of the operations are on eight processors and 16-bit data execution (such as video image pixel color component), but has a much wider data bus and registers. 因此,具有32位数据总线和寄存器并且执行这样一种算法的处理器可能损失多达75%的数据处理、运载和存储能力,因为只有前8位数据是重要的。 Thus, a 32-bit data bus and registers and the implementation of such an algorithm processor may lose as much as 75% of data processing, carrying and storage capacity, because only the first 8-bit data is important.

因此,希望有一个处理器,它通过更加有效地利用表示被操作数据需要的位数和处理器实际数据运载和存储容量之间的差,从而提高其性能。 It is therefore desirable to have a processor that through more efficient use of data representing the difference by the operating needs of the actual data bits and the processor between carrying and storage capacity, thereby improving its performance.

发明内容 DISCLOSURE

本文说明一种改进了数据处理操作的处理器。 This article describes an improved data processing operation processor.

一种处理器,它包括存储第一压缩数据的第一寄存器,一个解码器和一个功能单元。 A processor, comprising a first register storing a first compressed data, a decoder and a functional unit. 解码器有一个控制信号输入。 The decoder has a control signal input. 控制信号输入用于接收第一控制信号和第二控制信号。 Control signal input for receiving a first control signal and a second control signal. 第一控制信号用于指示一个压缩操作。 The first control signal is used to indicate a compression operation. 第二控制信号用于指示一个拆开操作。 The second control signal is used to indicate a disconnect operation. 功能单元连接到解码器和寄存器。 Functional unit connected to the decoder and register. 功能单元使用第一压缩数据执行压缩和拆开操作。 Functional unit using the first compressed data to perform compression and open operations. 处理器还支持移动操作。 The processor also supports the move operation.

虽然在说明书和附图中包含了大量的细节,但是,本发明由权利要求的范围限定。 While contains a lot of detail in the specification and drawings, but the present invention is defined by the scope of the claims. 只有在这些权利要求中提到的限制适用于本发明。 Only restrictions noted in these claims, the present invention applies.

附图说明 Brief Description

本发明用附图中的、但不限于附图中的实例说明,相同的参考标号表示相似的元件。 The present invention is used in the drawings, but is not limited to the examples described in the drawings, like reference numerals refer to like elements.

图1表示使用本发明的方法和装置的计算机系统的一个实施例;图2表示本发明的处理器的一个实施例;图3是说明由本发明的处理器使用的操作寄存器文件中的数据的总步骤的流程图;图4a说明存储器数据类型;图4b、图4c和图4d说明整数数据的寄存器内表示;图5a表示压缩数据类型;图5b,图5c和图5d说明压缩数据的寄存器内表示;图6a表示在该计算机系统中使用的指示使用压缩数据的控制信号格式;图6b表示第二控制信号格式,它可以用于该计算机系统指示使用压缩数据或者整数数据;图7表示由处理器在对压缩数据执行压缩操作时所遵循的方法的一个实施例;图8a表示能够对压缩字节数据实现压缩操作的电路;图8b表示能够对压缩字数据实现压缩操作的电路;图9表示由处理器在对压缩数据执行拆开操作时所遵循的方法的一个实施例;图10表示能够对压缩数据实现拆开操作的电路。 Figure 1 shows an embodiment of the method and apparatus of the present invention using the example of a computer system; Figure 2 shows an embodiment of the processor of the present invention; Figure 3 is always operating the register file by the processor of the present invention is used in the data flowchart; Figure 4a illustrates memory data type; Figures 4b, 4c and 4d illustrate the integer register data representation; Figure 5a shows the compressed data type; FIG. 5b, FIG. 5c and 5d the description of compressed data register indicates ; Figure 6a shows indicate that use of the computer system in the format of the data compression control signal; Fig. 6b shows the second control signal format, which may be used in the computer system indicates data or integer data compression; Fig. 7 shows the processor In one embodiment the compressed data when the compression operation followed perform the method; Fig. 8a shows the compressed byte data can achieve compression operation circuit; Fig. 8b shows the compressed digital data can achieve compression operation circuit; FIG. 9 is represented by Processors in the compressed data to perform an embodiment of the operation when the open method followed cases; Figure 10 shows the compressed data can achieve open circuit operation.

具体实施方式 DETAILED DESCRIPTION

本文叙述了对多个数据元素进行移动、压缩和拆开操作的处理器。 This paper describes the movement of a plurality of data elements, compression and open operation of the processor. 在下面的说明中,叙述了大量的诸如电路等这样的细节,以便提供对本发明彻底的了解。 In the following description, describes the amount of detail such as circuits, etc., in order to provide a thorough understanding of the present invention. 在另外的场合,为避免不必要地冲淡对本发明的理解,对熟知的结构和技术未作详细的叙述。 In another case, in order to avoid unnecessarily dilute the understanding of the present invention, for well-known structures and techniques have not been described in detail.

定义为了对理解本发明的实施例的说明提供基础,提供下面的定义。 In order to understand the definition of an embodiment of the present invention to provide an explanatory basis, following definitions are provided.

位X到位Y:定义二进制数的一个子字段。 Bit X in place Y: a subfield define a binary number. 例如字节001110102(以2为基表示)的位6到位0表示子字段1110102,二进制数后面的2表示以2为基。 Bits 6 0 001 110 102 sub-fields such as byte (base 2 representation) of 1,110,102, represent a binary number 2 behind the base two. 因此,10002等于810,而F16等于1510。 Therefore, 10002 equals 810, and F16 equal to 1510.

Rx:是一个寄存器。 Rx: is a register. 寄存器是能够存储和提供数据的任何设备。 Register is any device capable of storing and providing data. 寄存器的另外的功能下面说明。 Another function registers will be described below. 一个寄存器不一定是处理器组件的一部分。 A register is not necessarily part of the processor assembly.

DEST:是一个数据地址。 DEST: is a data address.

SRC1:是一个数据地址。 SRC1: it is a data address.

SRC2:是一个数据地址。 SRC2: it is a data address.

Result:要存储在由DEST寻址的寄存器中的数据。 Result: To store the data addressed by the DEST register.

Source1:存储在由SRC1寻址的寄存器中的数据。 Source1: data is stored in the SRC1 addressable registers.

Source2:存储在由SRC2寻址的寄存器中的数据。 Source2: data is stored in the SRC2 addressed register.

计算机系统参考图1,可以实现本发明的实施例的计算机系统作为计算机系统100表示。 Computer System Referring to Figure 1, an embodiment of the present invention may be implemented in a computer system as the computer system 100 represents. 计算机系统100包括总线101或者其它传输信息的通信硬件和软件以及与总线101连接的处理信息的处理器109。 The computer system 100 includes a bus 101 or other communications hardware and software for transmitting information and a processor 101 connected to bus 109 for processing information. 计算机系统100另外还包括一个随机存取存储器(RAM)或者其它动态存储设备(称为主存储器104),它连接到总线101上,用于存储信息和要由处理器109执行的指令。 The computer system 100 also includes a random access memory (RAM) or other dynamic storage device (referred to as main memory 104), which is connected to the bus 101, storing information and instructions to be executed by the processor 109 for. 主存储器104也可以用于暂存变量或者其它在处理器109执行指令时期的中间信息。 The main memory 104 can also be used for temporary storage variables or other intermediate information in the processor 109 performs the instruction period. 计算机系统100还包括连接在总线101上的只读存储器(ROM)106,和/或其它静态存储设备,用于存储静态信息和处理器109要执行的指令。 The computer system 100 also includes a bus 101 connected to the read-only memory (ROM) 106, and / or other static storage device to store static information and instructions to processor 109 for execution. 数据存储设备107连接到总线101上用于存储信息和指令。 Data storage device 107 is connected to for storing information and instructions on bus 101.

另外,数据存储设备107,例如磁盘或光盘以及它们相应的驱动器,可以连接到计算机100上。 In addition, the data storage device 107, such as magnetic or optical disk and their corresponding drive, you can connect to the computer 100. 计算机系统100也可以通过总线101连接到一个显示设备121上,以便显示信息给计算机用户。 The computer system 100 may also be connected to a display device 121 via bus 101 to display information to a computer user. 显示设备121可以包括一个帧缓冲器,专用图形处理设备,一个阴极射线管(CRT),和/或一个平面面板显示器。 The display device 121 may include a frame buffer, specialized graphics processing apparatus, a cathode ray tube (CRT), and / or a flat panel display. 通常一个包括字母数字和其它键的字母数字输入设备122连接到总线101上,用于给处理器109传输信息和命令选择。 Usually an alphanumeric input device 122 including alphanumeric and other keys connected to the bus 101 for transmitting information to a processor 109 and command options. 另一类型的用户输入设备是光标控制设备123,例如鼠标、轨迹球、光笔、触摸屏、或者光标指示键,用于给处理器109传输方向信息和命令选择以及控制光标在显示设备121上的移动。 Another type of user input device is cursor control device 123, such as a mouse, trackball, light pen, touch screen, or the cursor keys to processor 109 for transmission direction information and command selections and control the cursor on the display on the mobile device 121 . 这种输入设备通常在两个轴上有两个自由度,第一轴(例如x轴)和第二轴(例如y轴),它们允许光标控制设备在一个平面内指定位置。 This input device typically has two degrees of freedom in two axes, a first axis (e.g., x-axis) and second axis (e.g., y axis), a cursor control device which allows a specified location in a plane. 然而本发明不应该局限于只有两个自由度的输入设备。 However, the present invention should not be limited to only two degrees of freedom input device.

另一个可以连接到总线101上的设备是硬拷贝设备124,它可能用于在诸如纸、胶片、或者类似类型介质上打印指令、数据或者其它信息。 Another device can be connected to bus 101 is hard copy device 124 which may be used such as paper, film, or similar types of media on print instruction, data, or other information. 另外计算机系统100可以连接到声音记录和/或回放设备125上,例如连接到一个麦克风上记录信息的音频数字转换器。 In addition the computer system 100 may be connected to and / or sound playback device 125 records, such as connecting to a microphone recording audio digitizer information. 另外,该设备还可能包括一个连接到数/模(D/A)转换器的扬声器,用于回放数字化的声音。 Further, the apparatus may also include a connection to the digital / analog (D / A) converter speaker for playing back the digitized sounds.

还有,计算机系统100可以是一个计算机网络(例如一个局域网)的一个终端。 Also, computer system 100 may be a computer network (e.g., a local area network) is a terminal. 这样,计算机系统100便是包括若干连网设备的一个计算机系统的一个计算机子系统。 Thus, the computer system 100 is a computer subsystem comprising a plurality of computer systems networked device. 计算机系统100可以包括视频数字化设备126。 The computer system 100 may include a video digitizing device 126. 视频数字化设备126可以用于获取视频图像,而传输给网络中的其它设备。 Video digitizing device 126 can be used to obtain video image transmitted to the other devices in the network.

计算机系统100对于支持计算机支持的协作(CSC-电话会议与混合介质数据操作的集成)、2维/3维图形、图像处理、视频压缩/解压、识别算法和音频操作十分有用。 The computer system 100 for supporting computer-supported collaborative (CSC- conference call with the integration of mixed-media data manipulation), 2-D / 3-D graphics, image processing, video compression / decompression, recognition algorithms and audio operation very useful.

处理器图2表示处理器109的详图。 Figure 2 shows the processor 109 of the processor detail. 处理器109可以在使用一层或多层诸如BiCMOS、CMOS和NMOS等工艺技术的基底上实现。 Processor 109 may be implemented on one or more layers such as technology BiCMOS, CMOS and NMOS and other substrates.

处理器109包括一个解码由处理器109使用的控制信号和数据的解码器202。 Processor 109 includes a decoder 109 used by the processor control signals and data decoder 202. 然后数据可以通过内部总线205存储在寄存器文件204中。 Then the data through the internal bus 205 can be stored in the register file 204. 显然,一个实施例的寄存器不应该局限于特定类型的电路,相反,一个实施例的寄存器只需要能够存储和提供数据,以及执行这里叙述的功能。 Obviously, an embodiment of the register should not be limited to a particular type of circuit, on the contrary, a register of an embodiment need only capable of storing and providing data, and performing the functions described herein.

根据不同的数据类型,数据可能存储在整数寄存器组201、寄存器组209、状态寄存器组208或者指令指针寄存器211中。 Depending on the type of data, the data set may integer registers 201, registers 209, status registers 208 or instruction pointer register group 211 is stored in. 其它的寄存器例如浮点寄存器可以包含在寄存器文件204中。 Other registers such as floating-point registers can be included in the register file 204. 在一个实施例中,整数寄存器组201存储32位整数数据。 In one embodiment, the integer register file 201 stores 32-bit integer data. 在一个实施例中寄存器209组包括8个寄存器,R0212a到R7212h。 In one embodiment, the register 209 set includes eight registers implementation, R0212a to R7212h. 寄存器组209中的每一个寄存器为64位长。 Register bank 209 each register is 64 bits long. R1212a、R2212b和R3212c是寄存器组209中单个寄存器的例子。 R1212a, R2212b and R3212c register group 209 is an example of a single register. 寄存器组209中的一个寄存器的32位可以移动到整数寄存器组201中的一个整数寄存器中。 Register 209 in a register 32 can be moved to 201 in the integer register set an integer registers. 类似地,一个整数寄存器中的值可以移动到寄存器组209中的一个寄存器的32位中。 Similarly, an integer value in the register can be moved to a 32-bit register 209 in a register.

状态寄存器组208指示处理器109的状态。 Status 208 indicates the processor status register group 109. 指令指针寄存器211存储下一要执行的指令的地址。 Address of the instruction pointer register 211 stores the next instruction to be executed. 整数寄存器组201、寄存器组209、状态寄存器组208、和指令指针寄存器211都连接到内部总线205上。 Integer register set 201, register 209, the status register group 208, and the instruction pointer register 211 are connected to the internal bus 205. 任何另外的寄存器也都应该连接到内部总线205上。 Any additional registers also should be connected to the internal bus 205.

在另一个实施例中,这种寄存器中的某一些可以用于两种类型的数据。 Some of these registers can be used for two types of data in another embodiment. 例如,寄存器组209和整数寄存器组201可以组合,其中每一个寄存器既可以存储整数数据也可以存储压缩数据。 For example, the integer register set 209 and register set 201 may be combined, wherein each register can store either integer data to be stored compressed data. 在另一个实施例中,寄存器组209可以用作浮点寄存器组。 In another embodiment, the register bank 209 can be used as floating-point register set. 在这一实施例中,压缩数据或者浮点数据可以存储在寄存器组209中。 In this embodiment, the compressed data or floating point data can be stored in the register group 209. 在一个实施例中,组合寄存器为64位长,而整数用64位表示。 In one embodiment, the combination of registers is 64 bits long, and the integer represented by 64. 在该实施例中,在存储压缩数据和整数数据时,寄存器不需区分这两种数据类型。 In this embodiment, when storing the compressed data and integer data, the registers do not need to distinguish between these two types of data.

功能单元203执行由处理器109执行的操作。 Functional unit 203 executes operations executed by the processor 109. 这样的操作包括移位、加法、减法和乘法等。 Such operations include shifting, addition, subtraction and multiplication. 功能单元203连接到内部总线205。 Function unit 203 is connected to the internal bus 205. 高速缓冲存储器206是处理器109的一个选件,可以用于缓冲存储例如来自主存储器104的数据和/或控制信号。 Cache memory 206 is an optional processor 109, buffer memory may be used such as data and / or control signals from the main memory 104. 高速缓冲存储器206连接到解码器202以接收控制信号207。 The cache memory 206 is connected to the decoder 202 to receive control signal 207.

图3表示处理器109的总操作。 Figure 3 shows the total operating processor 109. 也就是说,图3表示处理器109在对压缩数据执行操作、对未压缩数据执行操作或者执行某个其它操作时遵循的步骤。 That is, FIG. 3 shows the compressed data processor 109 in executing operations, for failure to perform data compression operations or perform some other steps to follow operation. 例如这样的操作包括用从高速缓冲存储器206、主存储器104、只读存储器(ROM)106或者数据存储设备107的数据加载寄存器文件204中的一个寄存器的加载操作。 For example, such an operation includes 206 from the cache memory, data in the main memory 104, read only memory (ROM) 106 or data storage device 107 loads register file load operation 204 a register. 在本发明的一个实施例中,处理器109支持由加里福尼亚州圣大克拉热INTEL公司的INTEL80486TM支持的大多数指令。 In one embodiment of the present invention, the processor 109 is supported by the California Santa carat hot INTEL company INTEL80486TM support of most of the instructions. 在本发明另一个实施例中,处理器109支持由加里福尼亚州圣大克拉热INTEL公司的INTEL 80486TM支持的全部操作。 Embodiment, the processor 109 is supported by the California Santa carat hot INTEL INTEL 80486TM support the company's overall operation in another embodiment of the present invention. 在本发明的再一个实施例中,处理器109支持由加里福尼亚州圣大克拉热INTEL公司制造的奔腾处理器、INTEL 80486TM处理器、80386TM处理器、INTEL 80286TM处理器、和INTEL 8086TM处理器支持的全部操作。 Pentium processor in the present invention, a further embodiment, the processor 109 supports manufactured by California, Santa carat hot INTEL company, INTEL 80486TM processor, 80386TM processor, INTEL 80286TM processor, and the processor INTEL 8086TM It supports all operations. 在本发明的另一个实施例中,处理器109支持由加里福尼亚州Santa Clara的INTEL公司定义的IATM-INTEL结构支持的全部操作(参见“微处理器”,INTEL数据丛书卷1和卷2,1992年和1993年,加里福尼亚州Santa Clara INTEL公司出版)。 In another embodiment of the present invention, the processor 109 supports IATM-INTEL structure supported by California's Santa Clara INTEL company defined the entire operation (see "microprocessor", INTEL Data Series Volume 1 and Volume 2 , 1992 and 1993, California Santa Clara INTEL company published). 一般来说,处理器109可以支持奔腾处理器的当前指令集,但是也可以修改为支持未来指令以及这里叙述的指令集的集合。 In general, the processor 109 can support current Pentium processor instruction set, but can also be modified to support future instruction set and instruction set described here. 重要的是,处理器109除这里叙述的操作外,可以支持先前所用的操作。 Importantly, the processor 109 in addition to the operation described herein, but may be used to support operations previously.

在步骤301,解码器202从高速缓冲存储器206或者总线101接收一个控制信号207。 In step 301, the decoder 202 receives from the cache memory 206 or the bus 101 a control signal 207. 解码器202解码控制信号以判定要执行的操作。 The decoder 202 decodes the control signal to determine the operation to be performed.

在步骤302,解码器202访问寄存器204或者存储器中的一个存储单元。 In step 302, the decoder 202 access register 204 or a memory storage unit. 根据在控制信号207中指定的寄存器地址访问寄存器文件204中的寄存器或在存储器中的存储单元。 According to the control signal 207 in the specified register addresses to access the register file 204 registers or memory cells in the memory. 例如,为对压缩数据进行操作,控制信号207可以包括SRC1、SRC2和DEST寄存器地址。 For example, compressed data operation, the control signal 207 may include SRC1, SRC2 and DEST register addresses. SRC1是第一源寄存器地址。 SRC1 is the first source register address. SRC2是第二源寄存器地址。 SRC2 is the second source register address. 在一些情况下,SRC2地址是可选项,因为并非所有的操作需要两个源地址。 In some cases, SRC2 address is optional, since not all operations require two source addresses. 如果一个操作不需要SRC2地址,则只使用SRC1地址。 If an operation is not required SRC2 address, only the SRC1 address. DEST是存储结果数据的目的寄存器的地址。 DEST is the address of the result data storage destination register. 在一个实施例中,SRC1或SRC2也用作DEST。 In one embodiment, SRC1 or SRC2 also used as DEST. SRC1、SRC2和DEST将结合图6a和图6b更充分地说明。 SRC1, SRC2 and DEST conjunction with Figure 6a and 6b more fully described below. 存储在相应寄存器中的数据分别称为Source1、source2和Result。 Data stored in the respective registers are called Source1, source2 and Result. 它们每一个为64位长。 Each of which is 64 bits long.

在本发明的另一个实施例中,SRC1、SRC2和DEST中的任何一个或者全部可以定义为处理器109中的可寻址存储器空间的一个存储单元。 Example, SRC1, SRC2 and DEST any one or all of which may be defined as a memory cell processor 109 addressable memory space in another embodiment of the invention. 例如,SRC1可能确定在主存储器104中的一个存储单元,而SRC2确定在整数寄存器组201中的第一寄存器,以及DEST确定寄存器组209中的第二寄存器。 For example, SRC1 may identify a main memory 104 in the storage unit, and SRC2 integer register set 201 to determine a first register, and DEST register group 209 is determined in the second register. 这里为说明简单起见,参考标号是对寄存器文件204的访问标注的,然而这些访问也可以对存储器进行。 For simplicity of description herein, reference numeral 204 is a register file access to the label, however, these may also be access to the memory.

在本发明的另一个实施例中,操作码只包含两个地址,SRC1和SRC2。 In another embodiment of the present invention, the operation code contains only two addresses, SRC1 and SRC2. 在该实施例中,运算结果存储在SRC1或SRC2寄存器中,也就是说,SRC1(或SRC2)用作DEST。 In this embodiment, the calculation result is stored in the SRC1 or SRC2 register, that is, SRC1 (or SRC2) used as DEST. 这种类型的寻址与前面只具有两个地址的CISC指令兼容。 CISC instruction addressing this type previously only compatible with two addresses. 这简少了解码器202的复杂性。 This simple and less complex decoder 202. 注意,在这一实施例中,如果在SRC1寄存器中包含的数据不准备破坏,则在执行操作前必须首先把该数据复制到另一个寄存器中。 Note that in this embodiment, if the data contained in the SRC1 register is not ready to destroy, you must first copy the data before performing the operation to another register. 这一复制需要一个另外的指令。 This replication requires a further instructions. 这里为说明简单起见,将使用三地址寻址模式(亦即SRC1、SRC2和DEST)。 For simplicity of description herein, we will use a three-address addressing mode (ie SRC1, SRC2 and DEST). 然而应当记住,在一个实施例中,控制信号可能只包括SRC1和SRC2,以及SRC1(或SRC2)标识目的寄存器。 It should be remembered, however, in one embodiment, the control signal may include only SRC1 and SRC2, and SRC1 (or SRC2) identifies the destination register.

在控制信号需要一个操作时,在步骤303,允许功能单元203对来自寄存器文件204的被访问的数据执行该项操作。 When the control signal is required an operation, in step 303, it allows the functional unit 203 is accessed from the data register file 204 perform the operation. 一旦功能单元203执行完这一操作,在步骤304,则根据控制信号207的要求把结果回存到寄存器文件204中。 Once the function unit 203 executed this operation, in step 304, the control signal in accordance with the requirements of 207 the results back into the register file 204.

数据和存储格式图4a表示可以用于图1的计算机系统的一些数据格式。 Data storage format and some of the data format of FIG. 4a shows a computer system of Figure 1 may be used. 这些数据格式是定点格式。 The data format is fixed format. 处理器109可以操作这些数据格式。 Processor 109 can operate the data format. 多媒体算法常常使用这些数据格式。 Often multimedia algorithms use the data format. 一个字节401包含8个信息位。 Byte 401 contains eight information bits. 一个字402包含16个信息位,或者两个字节。 An information word 402 contains 16 bits, or two bytes. 一个双字403包含32个信息位,或者4个字节。 A double word 403 contains 32 information bits, or 4 bytes. 于是,处理器109执行可能操作这些存储器数据格式中任何一个的控制信号。 Thus, processor 109 may perform any of these memory data formats a control signal operation.

在下面的说明中,对位、字节、字、和双字的子字段加参考标号。 In the following description, subfields bit, byte, word, and double word plus reference numerals. 例如,字节001110102(以2为基表示)的位6到位0表示子字段1110102。 For example, the byte 001,110,102 (base 2 shown) bits 6 0 subfield 1,110,102.

图4b到图4d表示本发明的实施例中使用的寄存器内表示。 Figure 4b to 4d shows an embodiment of the present invention within the registers used representation. 例如无符号字节寄存器内表示410可以表示存储在整数寄存器组201中的一个寄存器中的数据。 For example, it represents an unsigned byte register 410 may represent data stored in a register in integer registers 201 in the group. 在一个实施例中,整数寄存器组201中的一个寄存器为64位长。 In one embodiment, the integer register file 201 is a register is 64 bits long. 在另一个实施例中,整数寄存器组201中的一个寄存器为32位长。 In another embodiment, the integer register file 201 a register is 32 bits long. 为说明简单起见,下面叙述64位的整数寄存器,然而也可以使用32位的整数寄存器。 For simplicity of description, the following description of a 64-bit integer registers, but also can use a 32-bit integer registers.

无符号字节的寄存器内表示410示出处理器109在整数寄存器组201中存储一个字节401,在该寄存器中的头8位,即位7到位0用于该数据字节401。 An unsigned byte register representation 410 shows a processor 109 is stored in the integer register file 201 in a byte 401 in the register of the first eight, came to the throne in place 0 7 401 for the data byte. 这些位表示为{b}。 These bits are represented as {b}. 为适当地表示这一字节,其余的56位必须为0。 Appropriately represents the byte, the remaining 56 must be zero. 对于一个有符号字节的寄存器内表示411,整数寄存器组201在头7位,即位6到位0存储该数据,为数据部分,第7位表示符号位,图中表示为{S}。 For a signed byte register 411 represents the integer register file 201 in the first seven, came to the throne in place 0 6 stores the data for the data portion, bit 7 represents the sign bit, the figure represented as {S}. 其余的位63到位8为该字节的符号的延续。 The remaining 8 bits in place for the continuation of the 63-byte symbol.

无符号字的寄存器内表示412存储在整数寄存器组201中的一个寄存器中。 An unsigned word register 412 is stored in the register represent an integer register file 201 in. 位15到位0包含一个无符号字402。 Bit 15 to Bit 0 contain an unsigned word 402. 这些位表示为{w}。 These bits are represented as {w}. 为适当地表示该字,其余的位63到位16必须为0。 To properly represent the character, the rest of the 63-place 16 must be zero. 带符号的字402存储在位14到位0,如带符号字的寄存器内表示413所示。 Word 402 stores the bit unsigned 14 bit 0, such as a register signed letter of representation shown in 413. 其余的位64到位15是符号字段。 The remaining bits 64 to 15 of a symbolic field.

双字403可以作为无符号双字的寄存器内表示414存储,或者作为带符号双字的寄存器内表示415存储。 Double word 403 can be used as an unsigned double word registers represent 414 stores, or as an internal unsigned double word register 415 indicates storage. 无符号双字的寄存器内表示414的位31到位0为数据。 An unsigned double word register 414 indicates a data bit 31 bit 0. 这些位表示为{d}。 These bits are represented as {d}. 为适当表示该无符号双字,其余的位63到位32必须为0。 An appropriate representation of the unsigned double word, the rest of the 63-place 32 must be zero. 整数寄存器组201在其位30到位0存储一个带符号双字的寄存器内表示415,其余的位63到位31是符号字段。 201 denotes an integer register file 415 in its 30-bit signed bit 0 store a double word register, the remaining bits 63 to 31 is a symbolic field.

如上面图4b到图4d所示,一些数据类型在64位宽的寄存器中的存储是一种低效的存储方法。 As above, as shown in Figure 4b to Figure 4d, some data types are stored in 64-bit wide registers is an inefficient method of storing. 例如,为存储一个无符号字节的寄存器内表示410,位63到位8必须为0,而只有位7到位0可能包含非0位。 For example, the memory an unsigned byte register representation 410, 63-Bit 8 must be zero, and only bits 7 to 0 may contain a non-0. 因此,在一个64位寄存器中存储一个字节的处理器只使用寄存器容量的12.5%。 Thus, a byte is stored in a 64-bit register in the processor registers used only 12.5% of capacity. 相似地,由功能单元203执行的操作只有前几位是重要的。 Similarly, the operations performed by the functional unit 203 is only the first of several important.

图5a表示压缩数据的数据格式。 Figure 5a shows the data format of the compressed data. 每一压缩数据包括多于一个独立的数据元素。 Each compressed data includes more than one independent data element. 图中说明3种压缩数据格式:压缩字节501,压缩字502和压缩双字503。 Illustrated in FIG. 3 kinds of compressed data format: 501 byte compression, compression word 502 and 503 compression double word. 在本发明的一个实施例中,压缩字节为64位长,包含8个数据元素,每一个数据元素为一字节长。 In one embodiment of the present invention, the compression is 64 bytes long and contains eight data elements, each data element is one byte long. 一般来说,一个数据元素是一个单个的数据,它与具有同样长度的其它数据元素存储在一个单一寄存器中(或存储单元)。 Generally, a data element is an individual data, which is stored with the other data elements having the same length in a single register (or memory cells). 在本发明的一个实施例中,存储在一个寄存器中的数据元素的数目等于64除以数据元素的位长。 In one embodiment of the present invention, the number of data elements stored in a register is equal to 64 divided by the bit length of the data element.

压缩字502为64位长,包含4个字402数据元素。 Packed word 502 is 64 bits long, contains four word 402 data elements. 每一个字402数据元素包含16个信息位。 Each word 402 data element contains 16 bits of information.

压缩双字503为64位长,包含两个双字403数据元素。 503 compression double word 64 bits long and consists of two double word 403 data element. 每一个双字403数据元素包含32个信息位。 Each double word 403 data element contains 32 bits of information.

图5b到图5d表示寄存器内压缩数据存储表示。 Figure 5b to Figure 5d represents the compressed data stored in the register represent. 无符号压缩字节的寄存器内表示510示出压缩字节501在寄存器组R0212a到寄存器组Rn212af中的一个寄存器中的存储方式。 An unsigned packed byte representation 510 illustrates the register 501 in the register of compressed bytes to the register set group R0212a Rn212af a register storage. 每个字节数据元素的信息对于字节0存储在位7到位0,对于字节1存储在位15到位8,对于字节2存储在位23到位16,对于字节3存储在位31到位24,对于字节4存储在位39到位32,对于字节5存储在位47到位40,对于字节6存储在位55到位48,对于字节7存储在位63到位56。 Information for each byte data element stored in the bit 7 for byte 0 bit 0, byte 1 is stored in bits 15 to 8 in place, the byte 2 stored in the bit 23 in place 16, 31 stored in the bit for byte 3 place 24, 39 stored in the bit for byte 4 in place 32, 47 stored in the bit for byte 5 in place 40, 55 stored in the bit for byte 6 in place 48, stored in the bit for byte 7 63 56 place. 因此寄存器中所有可用的位都被使用。 So register all available bits are used. 这种存储安排增加了处理器的存储效率。 This storage arrangement increases the storage efficiency of the processor. 另外,通过访问8个数据元素,现在可以同时对8个数据元素执行操作。 In addition, you can now perform operations by accessing eight data elements simultaneously on eight data elements. 带符号压缩字节的寄存器内表示511类似地存储在寄存器组209中的一个寄存器中。 A register signed packed byte representation 511 similarly stored in the register 209 in a register. 注意,每一字节数据元素只有第8位是必须的符号位,其它位可以用于或者可以不用于指示符号。 Note that each byte data element is only the first eight must sign bit, the other bits can be used or may not be used to indicate the sign.

无符号压缩字的寄存器内表示512示出字3到字0是怎样存储在寄存器组209中的一个寄存器中的。 An unsigned packed word in-register representation 512 shows a character from 3 to 0 is a register of how word stored in the register 209 in the group. 位15到位0包含对于字0的数据元素信息,位31到位16包含对于字1的数据元素信息,位47到位32包含对于字2的数据元素信息,而位63到位48包含对于字3的数据元素信息。 Bit 15 to Bit 0 contains the data elements of the message word 0, bit 31 in place 16 contains data elements for an information word, bit 47 for word 2 place 32 includes data elements of information, while 63-place 48 contains data for word 3 element information. 带符号压缩字的寄存器内表示513类似于无符号压缩字的寄存器内表示512。 A register signed packed word representation 513 is similar to unsigned packed word in-register representation 512. 注意,每一字数据元素只有第16位包含必要的符号指示符。 Note that each word data element, only the first 16 contain the necessary sign indicator.

无符号压缩双字的寄存器内表示514表示寄存器组209怎样存储两个双字数据元素。 An unsigned packed doubleword register 514 indicates that the register 209 indicates how to store two double word data elements. 双字0存储在寄存器的位31到位0。 Double word 0 0 stored in the register in place of 31-bit. 双字1存储在寄存器的位63到位32。 1 double word 63 bits stored in the register 32 in place. 带符号压缩双字的寄存器内表示515类似于无符号压缩双字的寄存器内表示514。 A register signed packed doubleword representation 515 is similar to unsigned packed doubleword in-register representation 514. 注意,必要的符号位是该双字数据元素的第32位。 Note that the necessary sign bit is the first 32 of the double-word data elements.

如前所述,寄存器组209既可以用于压缩数据,也可以用于整数数据。 As described above, both the register group 209 used to compress the data to be used for integer data. 在本发明的这一实施例中,可以要求单个程序处理器109跟踪一个被寻址的寄存器,例如R1212a,是否正在存储压缩数据或者简单整数/定点数据。 In this embodiment of the present invention, the processor 109 may be required to follow a single procedure to be addressed register, for example R1212a, whether it is stored in the compressed data or simple integer / fixed-point data. 在另一可选实施例中,处理器109可以跟踪存储在寄存器组209中的单个寄存器中的数据类型。 In an alternative embodiment, the processor 109 can track a single register set stored in the register 209 in the data type. 因此,如果例如试图对简单/定点整数数据施行一个压缩的加法运算的话,这一可选实施例可能产生错误。 Thus, if, for example trying to Simple / fixed-point integer data compression purposes of a summation, then, this alternative embodiment, errors may occur.

控制信号格式下面说明处理器109所用操作压缩数据的控制信号格式的一个实施例。 Control signal processor 109 format described below with the operation of a control signal compressed data format examples. 在本发明的一个实施例中,控制信号用32位表示。 In one embodiment of the invention, the control signal 32 indicates. 解码器202可以从总线101接收控制信号207。 Decoder 202 may receive control signals from the bus 101 207. 在另一个实施例中,解码器202也可以从高速缓冲存储器206接收这样的控制信号。 In another embodiment, the decoder 202 may also receive such control signals from cache memory 206.

图6a表示对压缩数据进行操作的控制信号的一般格式。 Figure 6a shows compressed data, control signals general format operation. 操作字段OP601,即位31到位26,提供关于由处理器109要执行的操作的信息;例如压缩加,压缩减等。 Operation field OP601, bit 31 in place 26, provides information about the operation to be executed by the processor 109; for example compression plus compression reduction and so on. SRC1 602,即位25到位20,提供寄存器组209中的一个寄存器的源寄存器地址。 SRC1 602, ascended the throne 25 place 20, register 209 provides a source register address register. 该源寄存器包含在控制信号执行中要用的第一压缩数据,Source1。 The source register contains the first compressed data to use in the implementation of the control signal, Source1. 相似地,SRC2 603,即位19到位14,包含寄存器组209中的一个寄存器的地址。 Similarly, SRC2 603, ascended the throne 19 14 in place, including the address register 209 in a register. 这一第二源寄存器包含执行操作期间要用到的压缩数据,Source2。 This second source register contains the operation to use during execution of the compressed data, Source2. DEST605,即位5到位0包含寄存器组209中的一个寄存器的地址。 DEST605, ascended the throne in place 5 0 contains the address register 209 in a register. 该目的寄存器将存储压缩数据操作的结果压缩数据Result。 The destination register will store the compressed data operation result compressed data Result.

控制位SZ610,即位12和位13,指示在第一和第二压缩数据源寄存器中的数据元素的长度。 Control bit SZ610, ascended the throne 12 and bit 13, indicates the length of the first and second compressed data in the source register data element. 如果SZ610等于012,则压缩数据作为压缩字节501格式化。 If SZ610 equal to 012, then 501 bytes of compressed data as a compressed format. 如果SZ610等于102,则压缩数据作为压缩字502格式化。 If SZ610 equal to 102, the compressed data word 502 as compressed format. SZ610等于002或112预留,然而,在另一个实施例中,其中的一个可以用来指示压缩双字503。 SZ610 reserve equal to 002 or 112, however, in another embodiment, one of which can be used to indicate packed doubleword 503.

控制位T611,即位11,指示该操作是否以饱和方式执行。 Control bit T611, ascended the throne 11, indicating whether the operation in saturated manner. 如果T611等于1,则执行饱和操作。 If the T611 is equal to 1, the saturation operation is performed. 如果T611等于0,则执行非饱和操作。 If the T611 is equal to 0, then perform a non-saturation operation. 后面说明饱和操作。 Saturation operation will be described later.

控制位S612,即位10,指示使用带符号操作。 Control bits S612, ascended the throne 10, indicating the use of a signed operation. 如果S612等于1,则执行带符号操作;如果S612等于0,则执行无符号操作。 If S612 is equal to 1, the operation is performed with sign; if S612 is equal to 0, an unsigned operation is performed.

图6b表示操作压缩数据的控制信号的第二种一般格式。 Figure 6b shows a second general format of the operation of the data compression control signal. 该格式相应于在“奔腾处理器系列用户手册”中叙述的一般整数操作码格式,该手册由INTEL公司文献销售部出版,地址为POBox 7641,Mt.prospect,IL.60056-7641。 This format corresponds to the general integer opcode format in the "Pentium Processor Series User Manual" described in the handbook published by the INTEL company sales literature, the address is POBox 7641, Mt.prospect, IL.60056-7641. 注意,OP601,SZ610,T611,和S612都结合在一个大字段中。 Note, OP601, SZ610, T611, and S612 are combined in one large field. 对于一些控制信号,位3到位5是SRC1 602。 For some control signals, bits 5 3 place is SRC1 602. 在一个实施例中,其中有一个SRC1 602地址,则位3到位5也相应于DEST605。 In one embodiment, where there is a SRC1 602 address, then bits 3 5 corresponding to the place DEST605. 在一个可选的实施例中,其中有一个SRC2 603地址,则位0到位2也相应于DEST605。 In an alternative embodiment, wherein there is a SRC2 603 address, then bits 0 2 corresponding to the DEST605. 对于其它的控制信号,例如压缩移位立即操作,位3到位5表示操作码场的扩展。 For other control signals, such as compression shift operation immediately, place 3 place extended 5 operation code field. 在一个实施例中,这种扩展允许程序员把一个立即数与控制信号结合,例如一个移位计数值。 In one embodiment, this expansion allows the programmer to a combination of immediate and control signals, such as a shift count. 在一个实施例中,立即数跟着控制信号。 In one embodiment, the immediate follow control signals. 这在“奔腾处理器系列用户手册”一书的附录F,从F-1到F-3页有详细介绍。 This is the "Pentium Processor Series User's Manual," a book of Appendix F, from F-1 to F-3 page contains detail. 位0到位2表示SRC2603。 Bits 0 2 represents SRC2603. 这种一般格式允许寄存器到寄存器,存储器到寄存器,由存储器对寄存器,由寄存器对寄存器,由立即数对寄存器,由寄存器到存储器寻址。 This general format allows register to register, memory to register, by the memory of the register by the register to register, register by the immediate data from the register to memory addressing. 在一个实施例中,这种一般格式也可以支持整数寄存器到寄存器和寄存器到整数寄存器寻址。 In one embodiment, this general format can also support integer register to register and register to integer register addressing.

饱和/非饱和的说明如前所述,T611指示操作是否可选为饱和。 Saturated / unsaturated instructions mentioned earlier, T611 optional indicating whether the operation is saturated. 在允许饱和的场合,当一个操作的结果溢出或下溢数据的范围时,其结果被箝位。 Allowing saturation of occasions when the result of an operation overflow or underflow data range, the result is clamped. 箝位指的是如果结果超过该范围的最大或最小值时把结果设定在最大或最小值。 Clamp refers to the maximum or minimum value if the result exceeds the range of the result set at the maximum or minimum. 在下溢的场合,饱和把结果箝位在该范围的最小值,而在溢出的场合,饱和把结果箝位在最大值。 Underflow of the occasion, the result is clamped in a saturated minimum value of the range, and in the case of overflow, the result is clamped at the maximum saturation. 对于每一种数据格式允许的范围示于表1。 For each of the allowable range data format shown in Table 1.

表1如上所述,T611指示是否正在执行饱和操作。 Table 1 described above, T611 indicating whether saturation operation is being performed. 因此,使用无符号字节数据格式,如果一个运算结果=258并且允许饱和,则在该结果被存储在该操作的目的寄存器之前被箝位在255。 Therefore, using the unsigned byte data format, if an operation result = 258 and allowed to saturate, then the result is stored in the destination register before the action is clamped at 255. 类似地,如果运算的结果=-32999且处理器109使用带符号字数据格式同时允许饱和,则运算结果在被存储在该运算的目的寄存器之前被箝位在-32768。 Similarly, if the result of operation = -32999 and processor 109 using a signed word data format while allowing saturated, the result of the operation before it is stored in the operation of the destination register is clamped to -32768.

数据处理操作在本发明的一个实施例中,多媒体应用的性能不仅通过支持标准的CISC指令集(未压缩数据操作),而且通过支持对压缩数据的操作而得以改善。 Data processing operations in one embodiment of the present invention, the performance of multimedia applications, not only by supporting standard CISC instruction set (uncompressed data manipulation), but also by supporting the operation of the compressed data can be improved. 这样的压缩数据操作可能包括加法、减法、乘法、比较、移位、与和异或。 Such actions may include compressed data addition, subtraction, multiplication, comparison, shift, with, and XOR. 然而,为充分使用这些操作,已经确定,应该包括数据处理操作。 However, to make full use of these operations, it has been determined, the data processing operation should be included. 这样的数据处理操作可能包括移动、压缩和拆开。 Such data processing operations may include move, compress and open. 移位、压缩和拆开由于产生出允许程序员容易使用的格式的压缩数据而方便了其它操作的执行。 Displacement, compression and open due to the generation of the format allows programmers to easily use compressed data to facilitate the implementation of other operations.

对于其它压缩操作的进一步的背景,参见流水号为—,于—申请的“具有比较操作的微处理器”,流水号为—于—申请的“具有移位操作的新型处理器”,流水号为08/176123,于1993年12月30日申请的“处理器中使用压缩数据的方法和装置”,流水号为08/175772,于1993年12月30日申请的“在处理器中使用新型操作的方法和装置”,所有这些申请都转让给本发明的受让人。 For further background other compression operation, see serial number is - at - the application of "comparative operating microprocessor", serial number is - to - application "has the shift operation of the new processor", serial number as 08/176123, "Method and apparatus for use compressing data processor" on December 30, 1993 application, Serial No. 08/175772, on December 30, 1993 filed "in the use of new processors Method and apparatus for "action, all of these applications are assigned to the assignee of the present invention.

移动操作移动操作把数据传输给寄存器209或从寄存器209传输出数据。 Mobile operating mobile operating data transmission to the register 209 or 209 to transfer data from the register. 在一个实施例中,SRC2 603是包含源数据的地址,而DEST605是数据要传输到的地址。 In one embodiment, SRC2 603 that contains the source address of the data, and the data to be transmitted to the DEST605 address. 在该实施例中,不用SRC1 602。 In this embodiment, not SRC1 602. 在另一个实施例中,SRC1 602就是DEST605。 In another embodiment, SRC1 602 is DEST605.

为解释移动操作,要区分寄存器和存储单元这两种情况。 To explain the move operation, the register and the memory unit to distinguish these two cases. 寄存器在寄存器文件204中寻找,而存储器可以是高速缓冲存储器206、主存储器104、ROM106、数据存储设备107。 Registers in the register file 204 to find, and the memory 206 may be a cache memory, a main memory 104, ROM106, the data storage device 107.

移动操作可以从存储器到寄存器组209、从寄存器组209到存储器、和从寄存器组209中的一个寄存器到寄存器组209中的另一个寄存器移动数据。 Move operation from the memory to the register 209, from the register 209 to the memory, and from the register 209 in one register to another register mobile data register block 209. 在一个实施例中,压缩数据存储在不同于存储整数数据的寄存器中。 In one embodiment, the compressed data stored in the memory is different from the integer data registers. 在该实施例中,移动操作可以把数据从整数寄存器组201移动到寄存器组209中。 In this embodiment, the data move operation can be moved from the integer register set 201 to register set 209. 例如,在处理器109中,如果压缩数据存储在寄存器组209中而整数数据存储在整数寄存器组201中,则可以使用移动指令从整数寄存器组201移动数据到寄存器组209,反之亦然。 For example, the processor 109, if the compressed data stored in the register group 209 and integer data stored in the integer register file 201, you can use the integer register move instruction set 201 to move the data from the register 209, and vice versa.

在一个实施例中,当为移动指定一个存储器地址时,在存储单元(指示最低有效字节的存储器单元)中的数据的8个字节加载到寄存器组209中的一个寄存器或从该寄存器存储数据的8个字节到该存储单元。 In one embodiment, when a memory address specified for the mobile, the 8-byte memory cells (indicating the least significant byte of memory cells) in the data is loaded into the register 209 in a register or a memory from the register 8 bytes of data to the storage unit. 当指定寄存器组209中的一个寄存器时,该寄存器中的内容被移动到寄存器组209中的第二寄存器或从寄存器组209中的第二寄存器加载内容到该寄存器。 When specifying a register bank 209 register, the register contents are moved to register 209 in the second register or load content from the register 209 in the second register to the register. 如果整数寄存器201为64位长,且指定一个整数寄存器,则在该整数寄存器中的数据的8个字节加载到寄存器209中的一个寄存器中或从后者存储在该整数寄存器中。 If the integer register 201 is 64 bits long, and specify an integer register, the 8-byte integer registers in the data is loaded into the register 209 or from a register which is stored in the integer registers.

在一个实施例中,整数用32位表示。 In one embodiment, a 32-bit integer representation. 当从寄存器组209到整数寄存器组201执行移动操作时,则只有低32位压缩数据移动到指定的整数寄存器。 When 209 from the register set to an integer register file 201 when the move operation, only the lower 32 bits of compressed data to the specified integer register. 在一个实施例中,高阶32位被置0。 In one embodiment, the high-order 32 is set to zero. 相似地,当执行从整数寄存器组201到寄存器组209的移动时,只加载寄存器组209中的一个寄存器的低32位。 Similarly, when executed from the integer register set 201 to register set to move 209, only the low register 209 is loaded in a register 32. 在一个实施例中,处理器109支持在寄存器组209的一个寄存器到存储器之间的32位移动操作。 In one embodiment, the processor 109 in the register 209 supports a 32-bit register-to-memory move operation between. 在另一个实施例中,只有32位的移动操作是就压缩数据的高阶32位进行的。 In another embodiment, only the 32-bit compressed data move operation is to carry out the high-order 32.

压缩操作在本发明的一个实施例中,SRC1 602寄存器包含数据(Source1),SRC2 603寄存器包含数据(Source2),而DEST605寄存器包含运算的结果数据(Result)。 Results (Result) compression operation in a present invention embodiment, SRC1 602 register contains data (Source1), SRC2 603 register contains data (Source2), and the register contains DEST605 operations. 也就是说,Source1的各部分和Source2的各部分压缩在一起产生Result。 In other words, the various parts and each part Source1 Source2 compressed together to produce Result.

在一个实施例中,压缩操作通过把源压缩字(或双字)的低位字节(或字)压缩到Result的字节(或字)中而把压缩字(或双字)变换为压缩字节(或字)。 In one embodiment, the compression operation by the compression of the source word (or double word) of the low byte (or word) is compressed to Result byte (or word) and the compressed word (or double word) into a packed word section (or words). 在一个实施例中,压缩操作把四压缩字变换为压缩双字。 In one embodiment, the compression operation of the fourth compression words are converted to compressed double word. 这一操作可选使用带符号数据执行。 This operation is optional to use unsigned data execution. 另外,该操作可选使用饱和方式执行。 In addition, the alternative operation execution using saturation mode.

图7表示对压缩数据执行压缩操作的方法的实施例。 Figure 7 shows a method for compressing data compression is performed on the operation of the embodiment. 该实施例可以在图2中的处理器109中实现。 This embodiment can be processor 109 in FIG. 2 is implemented.

在步骤701,解码器202解码由处理器109接收的控制信号207。 In step 701, the decoder 202 decodes the control signal received by processor 109 207. 于是,解码器202解码:适当的压缩操作的操作码;寄存器组209中的SRC1 602、SRC2 603和DEST605的地址;饱和/非饱和、带符号/无符号、和在压缩数据中的数据元素的长度。 Thus, the decoder 202 decodes: suitable compression operation code operation; register bank 209 SRC1 602, address SRC2 603 and DEST605; the saturated / unsaturated, signed / unsigned, and the compressed data in a data element length. 如前所述,SRC1602(或SRC2 603)可以用作DEST605。 As mentioned earlier, SRC1602 (or SRC2 603) can be used as DEST605.

在步骤702,通过内部总线205,解码器202访问寄存器 In step 702, via internal bus 205, decoder 202 access register 文件204中的寄存器组209,给出SRC1 602和SRC2 603的地址。 The register file 204 209, gives the SRC1 602 and SRC2 603 addresses. 寄存器组209供给功能单元203存储在SRC1 602寄存器中的数据(Source1)和存储在SRC2 603寄存器中的数据(Source2)。 Data (Source1) 203 storage registers 209 supply functional unit SRC1 602 register SRC2 603 and stored in the register (Source2). 也就是说,寄存器组209通过内部总线205给功能单元203传输数据。 That is, the register bank 209 205 203 through the internal bus to transfer data to the functional unit.

在步骤703,解码器202允许功能单元203执行适当的压缩操作。 In step 703, the decoder 202 allows the function unit 203 performs the appropriate compression operation. 解码器202通过内部总线205进一步传输在Source1和Source2中的数据元素的饱和和大小。 Decoder 202 205 further transmission of saturated and size Source1 and Source2 data elements through the internal bus. 饱和作为选项用以使在结果数据元素中的数据取最大值。 Saturation as an option to make the data in the results data elements takes the maximum value. 如果在Source1和Source2中的数据元素的值大于或者小于在Result中的数据元素所能表示的值的范围,则相应的结果数据元素设定为其最大或最小值。 If the value in the range of values and Source2 Source1 data element is greater than or less than the Result data elements can be represented by the corresponding resultant data element is set to its maximum or minimum. 例如,如果在Source1和Source2中的字数据元素中的带符号值小于0X80(或对双字来说为0X8000),则结果字节(或字)数据元素箝位在0X80(或对双字来说为0X8000)。 For example, if the word data elements Source1 and Source2 of the symbol values with less than 0X80 (or double word, it is 0X8000), the result byte (or word) data elements clamped 0X80 (or double word He said to 0X8000). 如果在Source1和Source2中的字数据元素中的带符号值大于0X7F(或对双字来说为0X7FFF),则结果字节(或字)数据元素箝位在0X7F(或0X7FFF)。 If word data elements Source1 and Source2 of the symbol values with more than 0X7F (or double word is to 0X7FFF), the result byte (or word) data elements clamped 0X7F (or 0X7FFF).

在步骤710,数据元素的大小决定下一步要执行哪个步骤。 In step 710, the size of the data elements which determine the next steps to be performed. 如果数据元素的大小为16位(压缩字502数据),则功能单元203执行步骤712。 If the size of the data element is 16 (compressed data word 502), the function unit 203 to step 712. 然而,如果压缩数据的数据元素的大小为32位(压缩双字503数据),则功能单元203执行步骤714。 However, if the size of the compressed data is data elements 32 (packed doubleword 503 data), the function unit 203 executes step 714.

假定源数据元素的大小为16位,则执行步骤712。 Assume that the source data element size is 16, step 712 is performed. 在步骤712,执行下面的内容。 In step 712, the following content. Source1位7到0为Result位7到0。 Source1 bits 7-0 to 7-0 Result bit. Source1位23到16为Result位15到8。 Source1 bits 23-16 into a Result bits 15-8. Source1位39到32为Result位23到16。 Source1 bits 39-32 into a Result bit 23-16. Source1位63到56为Result位31到24。 Source1 bits 63-56 into a Result bits 31-24. Source2位7到0为Result位39到32。 Source2 bits 7-0 Result bits of 39-32. Source2位23到16为Result位47到40。 Source2 bits 23-16 into a Result bits 47-40. Source2位39到32为Result位55到48。 Source2 bits 39-32 into a Result bit 55-48. Source2位63到56为Result31到24。 Source2 bits 63-56 of Result31 to 24. 如果设定了饱和,则测试每一字的高阶位以判定是否要箝位Result数据元素。 If you set the saturation, the test order bit of each word in order to determine whether to clamp Result data element.

假定源数据元素的大小为32位,则执行步骤714。 Assume that the source data element size is 32, step 714 is performed. 在步骤714,执行下面的内容。 In step 714, the following content. Source1位15到0为Result位15到0。 Source1 bits 15-0 to 15-0 Result Bit. Source1位47到32为Result位31到16。 Source1 bits 47-32 into a Result bit 31-16. Source2位15到0为Result位47到32。 Source2 bits 15-0 as Result bits 47-32. Source2位47到32为Result位63到48。 Source2 bits 47-32 into a Result bit 63-48. 如果设定了饱和,则测试每一双字的高阶位以判定是否要箝位Result数据元素。 If you set the saturation, the test of each order bit double word to determine whether to clamp Result data element.

在一个实施例中,步骤712的压缩操作同时执行。 In one embodiment, step 712 of the compression operation performed simultaneously. 然而,在另一个实施例中,这一压缩操作顺序执行。 However, in another embodiment, the sequence of operations to perform this compression. 在再一个实施例中,一部分压缩操作同时执行,而一部分顺序执行。 In a further embodiment, a portion of the compression operation performed simultaneously, and a portion sequentially. 这一讨论也适用于步骤714的压缩操作。 This discussion also applies to step 714 to compress operation.

在步骤720,Result存储在DEST605寄存器中。 In step 720, Result stored in DEST605 register.

表2表示非饱和无符号字压缩操作的寄存器内表示。 Table 2 shows the non-representation within the saturation unsigned word compression operation of the device. 第一行的位为Source1的压缩数据表示。 The first row is Source1 bits of compressed data representation. 第二行的位为Source2的数据表示。 The second row is Source2 bit data representation. 第三行的位为Result的压缩数据表示。 Result - the third row of the compressed data representation. 每一数据元素位下面的数字是该数据元素的号码。 Each data element position following figures are the number of data elements. 例如,Source1数据元素3是10000002。 For example, Source1 data element 3 is 10,000,002.

表2表3表示饱和带符号双字压缩操作的寄存器内表示。 Table 2. Table 3 shows the inner saturated DOUBLE SIGNED compression operation of the device represented.

表3 TABLE 3

压缩电路在本发明的一个实施例中,为有效地执行压缩操作,使用并行方法。 Compression circuit in one embodiment of the present invention, in order to efficiently perform compression operations using parallel methods. 图8a和图8b表示能够对压缩数据执行压缩操作的一个电路的实施例。 Figure 8a and Figure 8b shows a circuit capable of performing the compression operation of the embodiment of the compressed data. 该电路可选执行饱和压缩操作。 The circuit is an optional saturate compression operation.

图8a和图8b的电路包括操作控制电路800,结果寄存器852,结果寄存器853,8个16位到8位的饱和测试电路,和4个32位到16位的饱和测试电路。 8a and 8b, the circuit includes an operation control circuit 800, the result register 852, the result registers 853,8 a 16-8 saturation test circuit, and four 32-16 saturation test circuit.

操作控制电路800从解码器202接收信息以允许压缩操作。 The operation control circuit 800 receives information from the decoder 202 to allow the compression operation. 操作控制电路800使用饱和值允许对每一饱和测试电路进行饱和测试。 Operation control circuit 800 uses the saturation value to allow for each saturation test circuit saturation test. 如果源压缩数据的大小为字压缩数据503,则输出许可信号831由操作控制电路800置位。 If the source data is compressed size of the compressed data word 503, the output enable signal 831 by the operation control circuit 800 is set. 这就允许输出寄存器852输出。 This allows the output register 852 output. 如果源压缩数据的大小是双字压缩数据504,则输出许可信号832由操作控制电路800置位。 If the size of the source of the compressed data is compressed data double word 504, the output enable signal 832 by the operation control circuit 800 is set. 这就允许输出寄存器853输出。 This allows the output register 853 output.

每一饱和测试电路可以选择测试饱和。 Each saturation test circuit can select a test saturation. 如果饱和测试被禁止,则每一饱和测试电路仅仅把低阶位传送给一个结果寄存器的相应位置。 If the saturation test is disabled, the saturation of each test circuit only transmits a result of the lower order bits to the corresponding location register. 如果饱和测试被许可,则每一饱和测试电路测试高阶位以判定是否应该对结果箝位。 If the saturation test is allowed, then each test circuit saturation test to determine whether the high order bit of the result should be clamped.

饱和测试810到饱和测试817有16位输入和8位输出。 Saturated saturation test test 810 to 817 with 16-bit input and 8 output. 8位输出是输入的低8位,或可选为一个箝位值(0X80,0X7F,或0XFF)。 8 output is low input 8, or alternatively as a clamp value (0X80,0X7F, or 0XFF). 饱和测试810接收Source1位15到0而为结果寄存器852输出位7到0。 Saturation test 810 receives Source1 bits 15-0 and 852 output bits result register 7-0. 饱和测试811接收Source1位31到16而为结果寄存器852输出位15到8。 Saturation test 811 receives Source1 bits 31-16 and 852 output bits result register 15-8. 饱和测试812接收Source1位47到32而为结果寄存器852输出位23到16。 Saturation test 812 receives Source1 bits 47-32 and 852 output bits result register 23-16. 饱和测试813接收Source1位63到48而为结果寄存器852输出位31到24。 Saturation test 813 receives Source1 bits 63-48 and 852 output bits result register 31-24. 饱和测试814接收Source2位15到0而为结果寄存器852输出位39到32。 Saturation test 814 receives Source2 bit 15-0 and 852 output bits result register 39-32. 饱和测试815接收Source2位31到16而为结果寄存器852输出位47到40。 Saturation test 815 receives Source2 31-16 and 852-bit output bit is the result registers 47-40. 饱和测试816接收Source2位47到32而为结果寄存器852输出位55到48。 Saturation test 816 receives Source2 47-32 and 852-bit output bit is the result registers 55 to 48. 饱和测试817接收Source2位63到48而为结果寄存器852输出位63到56。 Saturation test 817 receives Source2 bit 63-48 and the result register 852 output bits 63-56.

饱和测试820到823有32位输入和16位输出。 Saturation test 820-823 has 32 inputs and 16 outputs. 16位输出是输入的低16位,或可选为一个箝位值(0X8000,0X7FFF,或0XFFFF)。 16 output is low 16 entered, or alternatively a clamp value (0X8000,0X7FFF, or 0XFFFF). 饱和测试820接收Source1位31到0而为结果寄存器853输出位15到0。 Saturation test 820 receives Source1 bits 31-0 and 853 output bits result register 15-0. 饱和测试821接收Source1位63到32而为结果寄存器853输出位31到16。 Saturation test 821 receives Source1 bits 63-32 and 853 output bits result register 31-16. 饱和测试822接收Source2位31到0而为结果寄存器853输出位47到32。 Source2 saturation test 822 receives bits 31-0 and 853 output bits result register 47-32. 饱和测试823接收Source2位63到32而为结果寄存器853输出位63到48。 Saturation test 823 receives Source2 63-32 and 853-bit output bit is the result registers 63-48.

例如在表4中,执行无符号不饱和字压缩操作。 For example, in Table 4, the implementation of an unsigned unsaturated digital compression operation. 操作控制电路800许可结果寄存器852输出结果[63:0]860。 800 Licensed result register 852 outputs operation control circuit [63: 0] 860.

表4然而,如果执行无符号不饱和双字压缩操作,则操作控制电路800许可结果寄存器853输出结果[63:0]860。 Table 4. However, if you perform an unsigned unsaturated double word compression operation, the operation control circuit 800 licensed result register 853 output [63: 0] 860. 表5表示这一结果。 Table 5 shows the results.

表5拆开操作在一个实施例中,拆开操作交错放置两个源压缩数据的低阶压缩字节、字或者双字以产生结果压缩字节、字或者双字。 Table 5 open operation, in one embodiment, the open source operating staggered two lower-order compressed data compression byte, word, or double word to produce a result packed byte, word, or double word.

图9表示对压缩数据执行拆开操作的方法的实施例。 Figure 9 shows a method of compressing data to perform open operations embodiments. 该实施例可以在图2中的处理器109中实现。 This embodiment can be processor 109 in FIG. 2 is implemented.

首先执行步骤701和702。 First steps 701 and 702. 在步骤903,解码器202许可功能单元203执行拆开操作。 In step 903, a decoder 202 licensed function unit 203 performs open operation. 解码器202通过内部总线205传输Source1和Source2中的数据元素的大小。 Decoder 202 by the size of the internal bus 205 and Source2 Source1 transmission of data elements.

在步骤910,数据元素的大小决定下一步执行哪一步骤。 In step 910, the size of the data elements which determine the next steps to perform. 如果数据元素的大小为8位(压缩字节数据501),则功能单元203执行步骤712。 If the size of the data element is 8 bits (byte compressed data 501), then the function unit 203 to step 712. 然而,如果压缩数据中的数据元素的大小为16位(压缩字数据502),则功能单元203执行步骤714。 However, if the size of the compressed data in the data element is 16 (compressed word data 502), then the function unit 203 executes step 714. 然而,如果压缩数据中的数据元素的大小为32位(压缩双字数据503),则功能单元203执行步骤716。 However, if the size of the compressed data to 32 data elements (packed doubleword data 503), then the function unit 203 to step 716.

假定源数据元素的大小为8位,则执行步骤712。 Assume that the source data element size of 8, step 712 is performed. 在步骤712,执行下面的内容:Source1位7到0为Result位7到0。 In step 712, the implementation of the contents of the following: Source1 bits 7-0 to 7-0 Result bit. Source2位7到0为Result位15到8。 Source2 Bit 7-0 to 15-8 Result Bit. Source1位15到8为Result位23到16。 Source1 bits 15-8 as a Result bits 23-16. Source2位15到8为Result位31到24。 Source2 bits 15-8 to 31-24 Result bit. Source1位23到16为Result位39到32。 Source1 bits 23-16 into a Result bits 39-32. Source2位23到16为Result位47到40。 Source2 bits 23-16 into a Result bits 47-40. Source1位31到24为Result位55到48。 Source1 bits 31-24 into a Result bits 55-48. Source2位31到24为Result位63到56。 Source2 bits 31-24 into a Result bits 63-56.

假定源数据元素的大小为16位,则执行步骤714。 Assume that the source data element size is 16, step 714 is performed. 在步骤714,执行下面的内容:Source1位15到0为Result位15到0。 In step 714, the implementation of the contents of the following: Source1 bits 15-0 to 15-0 Result Bit. Source2位15到0为Result位31到16。 Source2 bits 15-0 as Result bits 31-16. Source1位31到16为Result位47到32。 Source1 bits 31-16 into a Result bits 47-32. Source2位31到16为Result位63到48。 Source2 bits 31-16 into a Result bits 63-48.

假定源数据元素的大小为32位,则执行步骤716。 Assume that the source data element size is 32, step 716 is executed. 在步骤716,执行下面的内容:Source1位31到0为Result位31到0。 In step 716, the implementation of the contents of the following: Source1 bits 31-0 to 31-0 Result Bit. Source2位31到0为Result位63到32。 Source2 bits 31-0 as Result bits 63-32.

在一个实施例中,步骤712的拆开操作同时执行。 In one embodiment, step 712 is performed simultaneously open operation. 然而,在另一个实施例中,拆开操作顺序执行。 However, in another embodiment, the sequence of operations to perform open. 在再一个实施例中,拆开操作的一部分同时执行,另一部分顺序执行。 In a further embodiment, a portion of the open operation performed simultaneously, another part of the sequence. 这一讨论也适用于在步骤714和步骤716的拆开操作。 This discussion also applies to step 714 and step 716 open operations.

在步骤720,Result存储在DEST605寄存器中。 In step 720, Result stored in DEST605 register.

表6示出字节拆开操作的寄存器内表示。 Expressed in the Table 6 shows the operation of open-byte register.

表6表7示出字拆开操作的寄存器内表示。 Expressed in the Table 6 Table 7 shows the operation of the register word apart.

表7表8示出双字拆开操作的寄存器内表示。 Table 8 shows the double word open operation of the device represented.

表8 Table 8

拆开电路在本发明的一个实施例中,为有效地执行拆开操作,使用并行方法。 Open circuit in one embodiment of the present invention, to perform open operations effectively, using parallel methods. 图10表示能够对压缩数据执行拆开操作的一个电路的实施例。 Figure 10 shows a possible embodiment, the compressed data to perform open operations of a circuit.

图10的电路包括操作控制电路800,结果寄存器1052,结果寄存器1053和结果寄存器1054。 The circuit of Figure 10 includes an operation control circuit 800, the result register 1052, register 1053 results and 1054 results register.

操作控制电路800从解码器202接收信息而许可拆开操作。 The operation control circuit 800 receives the information from the decoder 202 and the open operating license. 如果源压缩数据的大小是字节压缩数据502,则由操作控制电路800置位输出许可信号1032。 If the source of compressed data size is 502 bytes of compressed data, by the operation control circuit 800 sets output enable signal 1032. 这就允许结果寄存器1052输出。 This allows the result to the output register 1052. 如果源压缩数据的大小为字压缩数据503,则输出许可信号1033由操作控制电路800置位。 If the source data is compressed size of the compressed data word 503, the output enable signal 1033 by the operation control circuit 800 is set. 这就允许输出寄存器1053输出。 This allows the output register 1053 output. 如果源压缩数据的大小是双字压缩数据504,则输出许可信号1034由操作控制电路800置位。 If the size of the source of the compressed data is compressed data double word 504, the output enable signal 1034 by the operation control circuit 800 is set. 这就允许输出结果寄存器1054输出。 This allows the output register 1054 output.

结果寄存器1052有下列输入。 Results register 1052 has the following input. Source1位7到0为结果寄存器1052的位7到0。 Source1 bits 7-0 of the result register 1052 bits 7-0. Source2位7到0为结果寄存器1052的位15到8。 Source2 bits 7-0 bits result register 1052 15-8. Source1位15到8为结果寄存器1052的位23到16。 Source1 bits 15-8 bits result register 1052 23-16. Source2位15到8为结果寄存器1052的位31到24。 Source2 bits 15-8 1052 as the result of register bits 31-24.

Source1位23到16为结果寄存器1052的位39到32。 Source1 bits 23-16 of 1052 result register bits 39-32. Source2位23到16为结果寄存器1052的位47到40。 Source2 bits 23-16 of 1052 result register bits 47-40. Source1位31到24为结果寄存器1052的位55到48。 Source1 bits 31-24 of 1052 result register bits 55-48. Source2位31到24为结果寄存器1052的位63到56。 Source2 bits 31-24 of 1052 result register bits 63-56.

结果寄存器1053有下列输入。 Results register 1053 has the following input. Source1位15到0为结果寄存器1053的位15到0。 Source1 bits 15-0 as a result register 1053 bits 15-0. Source2位15到0为结果寄存器1053的位31到16。 Source2 bit register 15-0 as the result of 1053 bits 31-16. Source1位31到16为结果寄存器1053的位47到32。 Source1 bits 31-16 bits 47-32 result register 1053. Source2位31到16为结果寄存器1053的位63到48。 Source2 bits 31-16 bits 63-48 result register 1053.

结果寄存器1054有下列输入。 Results register 1054 has the following input. Source1位31到0为结果寄存器1054的位31到0。 Source1 bits 31-0 for the 1054-bit result register 31-0. Source2位31到0为结果寄存器1054的位63到32。 Source2 bits 31-0 bits 63-32 result register 1054.

例如,在表9中,执行一个字拆开操作。 For example, in Table 9, perform a word open operation. 操作控制电路800将允许结果寄存器1053输出结果[63:0]860。 The operation control circuit 800 will allow the results of 1053 the output register [63: 0] 860.

表9 Table 9

然而,如果执行双字拆开操作,则操作控制电路800将允许结果寄存器1054输出结果[63:0]860。 However, if you perform double word open operation, the operation control circuit 800 will allow the results of the register 1054 output [63: 0] 860. 表10表示这一结果。 The results shown in Table 10.

表10因此,移动、压缩和拆开操作可以操作多个数据元素。 Table 10 therefore move, compress and open operations can operate on multiple data elements. 在现有技术的处理器中,为执行这些类型的操作,需要多个单独的操作来执行单一压缩数据移动、压缩或者拆开操作。 In prior art processors to perform these types of operations, require multiple separate operation to perform a single compressed data movement, compression or open operation. 在一个实施例中,用于压缩数据操作的数据线都带有相关的数据。 In one embodiment, the operations for compressing the data associated with the data lines of data. 它将提高计算机系统的性能。 It will improve the performance of computer systems.

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Classifications
International ClassificationG06F9/302, G06F9/318, G06F9/315, G06F9/30
Cooperative ClassificationG06F9/30192, G06F9/30145, G06F9/30036, G06F9/30181, G06F9/30032, G06F9/30109, G06F7/49921, G06F9/3013, G06F9/30025, G06F9/30167, G06F9/30196, G06F9/30149
European ClassificationG06F9/30A1A1, G06F9/30X, G06F9/30T4T, G06F9/30A1M, G06F9/30A1F, G06F9/30A1P, G06F9/30R4A, G06F9/30R5D
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