CN1449232A - 电路部件内装模块及其制造方法 - Google Patents

电路部件内装模块及其制造方法 Download PDF

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Publication number
CN1449232A
CN1449232A CN03103381A CN03103381A CN1449232A CN 1449232 A CN1449232 A CN 1449232A CN 03103381 A CN03103381 A CN 03103381A CN 03103381 A CN03103381 A CN 03103381A CN 1449232 A CN1449232 A CN 1449232A
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China
Prior art keywords
mentioned
module
electrical insulating
circuit block
insulating property
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CN03103381A
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Inventor
菅谷康博
朝日俊行
小松慎五
山本义之
中谷诚一
祜伯圣
大谷和夫
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Publication of CN1449232A publication Critical patent/CN1449232A/zh
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H05K1/187—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding the patterned circuits being prefabricated circuits, which are not yet attached to a permanent insulating substrate, e.g. on a temporary carrier
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Abstract

一种电路部件内装模块(212)，它包含：由包含无机填料及热硬化树脂的混合物构成的电绝缘性基板(201、201a)；在电绝缘性基板(201a)的至少主面上形成了的多个布线图形(202a、202b、202c)；内装于电绝缘性基板(201、201a)中、与布线图形(202c)电连接起来的半导体芯片(203)；以及以把多个布线图形(202a、202b)电连接的方式贯穿上述电绝缘性基板(201a)而形成了的内通路(204a)。半导体芯片(203)的厚度为30μm以上、100μm以下，且非布线面为研磨面，上述电路部件内装模块(212)的厚度在80μm以上、200μm以下的范围内。由此，提供在高性能、小型化了的各种电子信息设备中优选使用的、高密度安装了的电路部件内装模块。

Description

电路部件内装模块及其制造方法
技术领域
本发明涉及电路部件内装模块及其制造方法，详细地说，涉及把半导体芯片内装于电绝缘性基板中来谋求薄型化、并通过作成多级层叠模块来实现高密度安装的电路部件内装模块及其制造方法。
背景技术
近年来，伴随着与信息通信产业惊人发展对应的各种电子信息设备的高性能、小型化，要求在这样的电子信息设备中使用的电路部件高密度化、高功能化及短布线化，为了实现这些特性，进一步增强了对于内装了电路部件或电子元件的模块、即电路部件内装模块的极薄化的要求。
为了谋求电路部件的极薄化，由于在把电路部件安装到基板表层内的技术中存在着极限，故提出了通过在基板中设置凹部、在凹部中配置半导体芯片以使基板薄型化来谋求电路部件高密度安装的技术(特开平5-259372号公报、特开平11-103147号公报及特开平11-163249号公报)。在这种技术中，在把半导体芯片等有源部件安装到基板的凹部中之后，为了保护半导体芯片与基板的连接部及半导体芯片，在上述凹部中涂布树脂并进行密封。
此外，还提出了通过对电路基板进行多级化来谋求高密度安装的技术。在现有的、在使玻璃纤维交叉点浸渍了环氧树脂的基板(玻璃环氧基板)等上通过钻孔来形成贯穿通孔结构的技巧中，由于在向高密度化的对应方面存在着极限，故存在着在LSI(大规模集成电路)间或部件间的布线图形不能以最短距离连接起来的问题。然而，为了解决这样的问题，提出了内通路孔连接技术(特开昭63-47991号公报及特开平6-268345号公报)。上述那样的内通路孔连接技术可以只连接特定的层叠层间，在半导体芯片的安装性方面也是优越的。
进而，在特开平11-220262号公报中，作为电路部件内装模块之一例，提出了在具备高热传导性的电路基板中内装了半导体芯片、把上述电路基板分级层叠起来的，散热性能高的模块。
作为另一周知例，提出了ICEP Proceeding Stacking SemiconductorPackages，2001，P16-21。使用图12A及图12B，说明该一例。层叠挠性50～100μm的、安装了半导体芯片1001的玻璃环氧基板1002(图12A)，形成谋求了高密度安装的多级层叠存储器封装体1003(图12B)。图12A中，1004为半导体芯片1001的凸起电极，1005为玻璃环氧基板1002的表面电极，1006为密封树脂，1007为玻璃环氧基板，1008为通路，1009为布线，1010为凹部空间。
然而，在电路基板中设置凹部空间1010并在1010中配置半导体芯片1001的技术中，即使采用陶瓷基板、树脂系列基板中的某一种基板，在基板上加工凹部的工序中也需要巨额成本，还存在着生产成品率降低的问题。另外，在玻璃环氧基板中使用密封树脂来配置半导体芯片的技术中，使用了通孔电镀成通路孔的连接技术，但因作为基板所使用的材料为通常的玻璃环氧等树脂，故基板本身的热传导率低，模块的散热性能不足，损坏了可靠性。
进而，在把电路基板多级层叠起来的电路部件内装模块中，在把多个半导体芯片在纵向上层叠起来的形态的情况下，模块整体的厚度变得过大，在高密度安装方面存在着极限。在把SRAM(静态随机存取存储器)、快速存储器等种类不同的存储器半导体芯片在纵向上层叠起来的存储器模块中，为了谋求薄型化半导体芯片的厚度受到限制，整个模块的层叠数顶多为3～4层，不能充分进行高密度安装。
另一方面，在晶片上进行了研磨之后进行切块、再把半导体芯片安装到基板中的技术的开发也变得活跃起来，但这样的薄型半导体芯片的操作性差，由朝向基板的安装性来代表的生产效率低。
此外，在对如图12A-B所示那样的薄型半导体芯片进行了层叠的多级层叠存储器封装体1003中，基板1002的厚度是决定性的，在特定的模块厚度的范围内，例如设置8级左右的层叠是困难的。此外，在该多级层叠模块中，作为层间连接方法一般采用通过电镀构成的通路，为了提高层间的粘着性需要复杂的工序。而且，把半导体芯片装入基板1002中变成了困难，在半导体芯片周围产生了空隙，例如在吸湿时的回流工序中存在着水蒸汽爆炸的危险性等，损坏了所得到的模块的可靠性。
在这样的薄型多级层叠模块中，为了提高基板1002的强度例如在使用了玻璃环氧基板的情况下，把半导体芯片内装于基板1002中是困难的，例如如图13所示，必须把L(电感)、C(电容器)及R(电阻)等片状部件1104安装在模块的最表层面上，在把高密度安装作为目标的、包含电路部件的最佳配置的电路基板结构设计方面产生了限制。
发明内容
本发明解决了现有技术中的这样的问题，其目的在于提供在厚度薄、且高性能、小型化了的各种电子信息设备中使用的、高密度安装了的电路部件内装模块及其制造方法。
为了达到上述目的，本发明的一种电路部件内装模块，它包含：由包含无机填料及热硬化树脂的混合物构成的电绝缘性基板、及在上述电绝缘性基板的至少主面上形成了的多个布线图形；
内装于上述电绝缘性基板中、与上述布线图形电连接起来的半导体芯片；以及
以把上述多个布线图形电连接的方式贯穿上述电绝缘性基板而形成了的内通路，该模块的特征在于，
上述半导体芯片的厚度为30μm以上、100μm以下，且非布线面为研磨面，
上述电路部件内装模块的厚度在80μm以上、200μm以下的范围内。
其次，本发明的一种电路部件内装模块的制造方法，该模块包含：由包含无机填料及热硬化树脂的混合物构成的第1电绝缘性基板、及在上述电绝缘性基板的至少主面上形成了的多个布线图形；
内装于上述电绝缘性基板中、与上述布线图形电连接起来的半导体芯片；以及
以把上述多个布线图形电连接的方式贯穿上述电绝缘性基板而形成了的内通路，该制造方法的特征在于包含：
准备在上述电绝缘性基板上开设贯穿孔、在该孔中填充了热硬化导电性物质的板状体的工序；
把半导体芯片安装到在脱模载体上形成了的布线图形上的工序；
研磨上述半导体芯片的非布线面，将其作成厚度为30μm以上、100μm以下的工序；
在上述脱模载体的形成了布线图形的面上以使在上述贯穿孔中填充了导电性物质的部分与上述布线图形一致的方式对上述板状体进行位置重合，通过这样来进行重叠及加压，把上述半导体芯片埋入上述板状体中的工序；
通过加热上述埋入体，使上述混合物与上述导电性物质同时硬化得到厚度在80μm以上、200μm以下的电路部件内装模块的工序；以及
剥离上述脱模载体的工序。
附图的简单说明
图1为示出本发明实施形态1中的电路部件内装模块的剖面图。
图2A～F为示出本发明实施形态1中的电路部件内装模块的制造方法的工序剖面图。
图3A～D为示出本发明实施形态2中的电路部件内装模块的剖面图。
图4A～C为示出本发明实施形态2中的电路部件内装模块的制造方法的工序剖面图。
图5为示出本发明实施形态3中的电路部件内装模块的剖面图。
图6A～E为示出本发明实施形态3中的电路部件内装模块的制造方法的工序剖面图。
图7A～B为示出本发明实施形态4中的多级层叠模块的制造方法的工序剖面图。
图8A～D为示出本发明实施形态5中的多级层叠模块的制造方法的工序剖面图。
图9A～B为示出本发明实施形态5中的多级层叠模块的制造方法的工序剖面图。
图10A～D为示出本发明实施形态6中的多级层叠模块的制造方法的工序剖面图。
图11A～C为示出本发明实施形态6中的多级层叠模块的制造方法的工序剖面图。
图12A～B为示出现有技术的多级层叠模块的剖面图。
图13为示出现有技术的另一多级层叠模块的剖面图。
本发明的具体实施方式
本发明的半导体部件内装模块的特征在于，把半导体芯片安装于在脱模载体上形成了的布线图形上，再把半导体芯片理入电绝缘性基板内，利用贯穿上述电绝缘性基板而形成了的内通路、把从上述半导体芯片表面取出的布线图形与上述内通路电连接起来。由此，电路部件内装模块能够薄型化，得到高性能且小型化了的，实现了高密度安装的多级层叠模块。
在本发明方法中，在安装了半导体芯片之后，把上述半导体芯片研磨加工成30μm以上、100μm以下的厚度。为了得到薄型化且小型化了的多级层叠模块，只要是上述范围内的厚度就是优选的。此外，即使把半导体芯片的非布线面研磨成上述范围内的厚度，在性能上也没有问题。
此外，只要上述电路部件内装模块的厚度是80-200μm，在薄型化且小型化方面就是优选的。
上述半导体芯片是晶片级的芯片比例封装(CSP)半导体，是较为理想的。这是因为除了薄型化且小型化外，质量保证方面是优选的。
把上述半导体芯片埋入板状体中的工序是使用2个形成了上述布线图形的脱模载体夹住上述板状体进行位置重合，通过这样来进行重叠及加压，把2个半导体芯片在使其上表面互相对置的状态下、在厚度方向上埋入上述板状体中的工序，是较为理想的。这是因为不造成浪费的空间，在薄型化且小型化方面是优选的。
也可以进而在上述电绝缘性基板的另一主面上也形成上述布线图形，在上述电绝缘性基板中，在将其上表面互相对置起来的状态下、在上述电绝缘性基板的厚度方向上内装了2个上述半导体芯片，上述2个半导体芯片中的一个与在上述电绝缘性基板的主面上形成了的布线图形电连接起来，另一个与在上述电绝缘性基板的另一主面上形成了的布线图形电连接起来。这是因为该方法也不造成浪费的空间，在薄型化且小型化方面是优选的。
在上述电绝缘性基板的至少主面上形成了的布线图形是在上述电绝缘性基板上层叠了的多层布线基板的表层上的布线图形的一部分，是较为理想的。通过使用多层布线基板不但可实现高集成化及高性能，而且还能提高强度、还提高了操作性。
进而把无源部件内装于上述电绝缘性基板中，把上述无源部件与上述多个布线图形的某一个电连接起来，是较为理想的。如果把无源部件同时内装，就能够实现高性能。上述无源元件是从例如电感、电容器及电阻(以下，也称为LCR)中选择的至少一种。
利用底填树脂、电绝缘性膜(NCF)、或包含导电性粒子的各向异性导电膜(ACF)增强了上述半导体芯片与上述布线图形的连接部，是较为理想的。在此，所谓底填材料表示密封树脂，例如由无机填料及环氧树脂构成、作为液状树脂组成物利用注入的方法来使用。
也可以层叠4～8层上述电路部件内装模块来形成多级层叠模块。此时，由上述内通路把相邻的电路部件内装模块电连接起来，是较为理想的。如果这样做，就能够以任意的级数来层叠。
把具备内通路的电绝缘性基板配置在上述相邻的电路部件内装模块间，把上述电绝缘性基板作成与构成上述电路部件内装模块的电绝缘性基板为同一组成物，是较为理想的。如果作为同一组成物，则即使形成多级层叠模块也能够使每层间的物理特性保持相同。
在层叠4～8层上述电路部件内装模块来形成多级层叠模块时，也可以把具备内通路的电绝缘性基板配置在相邻的电路部件内装模块间，把薄膜状的无源元件配置在上述电绝缘性基板上。
上述脱模载体为金属片或树脂片，是较为理想的。
此外，上述树脂片为从聚酰亚胺、聚对苯二甲酸乙二酯、聚乙烯萘、聚苯撑亚硫酸盐、聚乙烯、聚丙烯、及氟树脂中选择的至少一种树脂膜，是较为理想的。脱模载体较为理想的厚度为30～100μm。氟树脂例如为聚四氟乙烯(PTFE)、四氟乙烯-全氟烃基乙烯醚共聚物(PFA)、四氟乙烯-六氟丙烯共聚物(FEP)、聚氟化乙烯、聚氟化乙烯叉等。
上述金属片也可以是铜箔。此外，也可以：上述脱模载体是铜箔，金属布线图形是铜箔，上述脱模载体与上述布线图形间的剥离层由铬电镀层来形成。
此外，在作为脱模载体使用具有30μm以上厚度的金属箔、例如铜箔等的情况下，也可以通过金属电镀层、例如铬电镀层、镍电镀层来形成铜箔布线图形。可以这样来形成布线图形，例如在把铜箔粘着到脱模载体上之后，经过光刻工序而形成。如果这样做，则与作为载体使用了树脂膜的情况相比较，能够使载体剥离后的铜箔表面更加清洁。即，由于直接把电场电镀界面露出，故更加能够使未氧化、有光泽、未处理的铜箔界面露出。
在把上述半导体芯片及上述无源元件埋入第一板状体中之前进行导通检验，是较为理想的。如果预先这样做了，制品的成品率则提高。当然，在电路部件内装模块制造后进行检验，也是较为理想的。
以下，一边参照附图，一边说明本发明的实施形态。
(实施形态1)
图1示出本实施形态的电路部件内装模块112的剖面图。电路部件内装模块112是把半导体芯片103内装于电绝缘性基板101中的结构。102b及102c为在电绝缘性基板101的主面上形成了的布线图形，102a为在电绝缘性基板101的另一主面上形成了的布线图形。备布线图形由铜箔或导电性树脂组成物构成。通过贯穿电绝缘性基板101而形成了的内通路104，把布线图形102a与102b电连接起来。通过凸点105，把半导体芯片103与布线图形102c电连接起来。利用电绝缘性片106密封并增强了半导体芯片103与布线图形102c的连接部。除了电绝缘性片106以外，还可以利用底块材料等密封树脂、电绝缘性膜(NCF)、或包含导电粒子的各向异性导电膜(ACF)来增强上述连接部。
电路部件内装模块112内的半导体芯片103的厚度为30～100μm是必要的，较为理想的是30～50μm。超过100μm时，不能谋求电路部件内装模块的薄型化，在作成多级层叠模块的情况下不能实现充分的高密度安装。此外，电路部件内装模块112的厚度为80～200μm。
在本实施形态中，除了有源部件、即晶体管、IC(集成电路)、LSI(大规模集成电路)等半导体芯片以外，还可以把无源部件、即1005、0603尺寸的具有各种L(电感)、C(电容器)、R(电阻)功能的片状部件、表面弹性波(SAW)器件、或通过印刷形成的具有电容器、电阻功能的薄膜状元件与布线图形102c连接而将其内装于电路部件内装模块112中。
电绝缘性基板101由包含无机填料及热硬化树脂的混合物构成。作为无机填料，例如可以使用Al2O3、MgO、BN、ALN、SiO2等。此外，作为热硬化树脂可以使用环氧树脂、苯酚树脂、氰酸盐树脂、或聚苯撑醚树脂。再有，环氧树脂因其耐热性高而特别理想。
无机填料对混合物的含量为70～95重量％，是较为理想的。此外，由于无机填料可提高电绝缘性基板的热传导性等，故将其以高密度填充是较为理想的。例如，为了降低基板的介电常数使用SiO2(二氧化硅填料)，如果使其含量为80重量％以上，则热传导率为1w/m.k以上。此外，为了提高基板的热传导性作为无机填料使用AlN(氮化铝)填料，如果使其含量为95重量％，则热传导率约为10w/m.k。此外，如果使Al2O3的含量为88重量％，则热传导率约为3～4w/m.k。
无机填料的平均粒子直径在0.1～100μm范围内是较为理想的。再有，在混合物中，除了无机填料以外，也可以根据需要而包含分散剂、着色剂、交联剂、脱模剂等。
内通路104由导电性树脂组成物的硬化物构成。该导电性树脂组成物由金属粒子85～92重量％与热硬化树脂8～15重量％的混合物构成，即可。作为金属粒子可使用例如导电性高的金、银、铜、镍等，或它们的混合物。铜因其迁移小，尤为理想。作为热硬化树脂可使用环氧树脂、苯酚树脂、氰酸盐树脂、或聚苯撑醚树脂。环氧树脂因其耐热性高，尤为理想。
凸点105是电镀凸点、柱凸点都可以，但从提高它与布线图形102的连接可靠性的观点出发，柱凸点较为理想。
按照该结构，由于把30～100μm的半导体芯片内装于电绝缘性基板中、且由在基板贯穿孔中填充的内通路把模块的布线图形连接起来，故能够把电路部件内装模块充分薄型化。此外，把半导体芯片内装于电绝缘性基板中将其与外部空气隔开，可防止潮气所引起的恶化，提高电路部件内装模块的可靠性。而且，再布线及质量检验也变得容易，减轻了电路基板结构设计上的限制，能够制造各种结构的LGA(接合栅格阵列)电极了。
一边参照图2A～图2E，一边说明本实施形态的电路部件内装模块112的制造方法之一例。
首先，如图2A所示，使用形成了布线图形202c的脱模载体207，通过凸点205在布线图形202c上对厚度为200～400μm的半导体芯片203进行倒装芯片安装。作为脱模载体207可使用聚酯薄膜、聚对苯二甲酸乙二酯、聚苯撑亚硫酸盐、氟树脂等有机树脂薄膜，也可以使用铜箔或铝箔等各种金属箔。此外，也可以在脱模载体207上通过涂覆适当的有机膜来形成剥离层。
可以在脱模载体207的表面上电解电镀厚度约为9～35μm的铜来形成布线图形202c。此外，也可以在把铜箔粘着到脱模载体207的表面上之后，经过光刻工序来形成该布线图形。为了提高布线图形202c与合成片201的粘着性，使微细金属粒子析出等以对其表面进行粗糙化是较为理想的。布线图形202c也可以是没有防锈层的未处理的铜箔，或者也可以是为了提高粘着性或耐氧化性而对其表面进行了交联处理。布线图形202c也可以是除了铜以外，电场电镀钖、锌、镍、金等来形成，或者也可以是对其表面进行由锡-铅合金构成的焊锡电镀或锡-银-铋等无铅的焊锡电镀。
在本实施形态中，在倒装芯片安装时，使电绝缘性片206介于半导体芯片203与布线图形202c之间，来增强半导体芯片203与布线图形202c的连接部。然后，进行加热、加压，如图2B所示，通过凸点205使半导体芯片203与布线图形202c的连接完成。也可以使用导电性粘着剂来代替凸点205。作为这种导电性粘着剂可以使用例如把金、银、铜或银-钯合金等与热硬化树脂混练而形成的粘着剂。也可以在半导体芯片203上形成利用金丝键合法制造的金凸点或焊锡凸点，通过热处理熔化这些凸点而连接起来，来代替导电性粘着剂。也可以并用导电性粘着剂及焊钖凸点。
也可以把底填材料等密封树脂注入到布线图形202c与半导体芯片203之间，来代替使用电绝缘性片206。如果用密封树脂来增强连接部，则用整个密封树脂来吸收因半导体芯片203与合成片201的热膨胀率之差所产生的应力，能够有效地抑制应力集中，当把半导体芯片203埋入合成片201中时能够防止在半导体芯片203与布线图形202c之间发生间隙。除了密封树脂以外，可根据需要而使用电绝缘性膜(NCF)或包含导电粒子的各向异性导电膜(ACF)。
其次，如图2c所示，利用表层由金刚石磨粒构成的砂轮等研磨半导体芯片203，一直研磨到图中的研磨线为止，将其加工成厚度为30～100μm，较为理想的是30～50μm。在此，利用了研磨法，但除此之外，还可以利用抛光等研磨法、放电加工法进行加工。但是，在以高速进行加工的情况下，把脱模载体固定在金属模卡具等上、利用研磨法来进行是较为理想的。按照该方法，能够不引起损伤、以高速、把厚度约为200～400μm的半导体芯片容易地加工成约为50～100μm。
接着，如图2D所示，一边加以注意以使贯穿孔204的位置及形状不失真，一边对于安装了半导体芯片203的脱模载体207与具有贯穿孔204的合成片201进行位置重合，这样来进行重叠。通过混合无机填料与未硬化状态的热硬化树脂而作成膏状混合物、将该混合物成形为一定厚度的板状体，来制造合成片201。此外，在贯穿孔204中预先填充了包含金属粒子及未硬化的热硬化树脂的导电性树脂组成物。
其次，进行加压，如图2E所示，在把半导体芯片203埋入合成片201中之后，在合成片201的混合物及贯穿孔204中的导电性树脂硬化的温度以上的温度(例如150°～260℃)下进行加热。由此，合成片201成为电绝缘性基板201a，贯穿孔204成为内通路204a。此外，此时，布线图形202a、202b与电绝缘性基板201a牢固地粘着起来。再有，通过在加热时以10～200kg/cm2进行加压，能够提高布线图形向所得到的电路部件内装模块212的转移性及通路连接的可靠性。
其后，如图2F所示，把脱模载体207从电绝缘性基板201a机械地剥离，把布线图形202b、202c转印到电绝缘性基板201a上而得到电路部件内装模块212。
再有，此后，可以在电路部件内装模块212的主面及另一主面上印刷抗蚀剂、把布线图形202a、202b固定到电路部件内装模块212上，或者也可以通过在布线图形部中注入底填材料或在电路部件内装模块212上层叠未硬化树脂片、来密封布线图形202a、202b。
按照该制造方法，由于把安装在脱模载体上的半导体芯片加工成薄型的，故能够稳定地制造厚度为80～200μm的薄型电路部件内装模块。
此外，由于作为电绝缘性基板使用了无机填料及热硬化树脂的混合物，故不需要象陶瓷基板那样在高温下烧成，基板的制造变得容易。
进而，由于电绝缘性基板中包含无机填料，故半导体芯片中所发生的热迅速扩散到外部，可提高电路部件内装模块的可靠性。而且，通过变更该无机填料的种类及其在基板中的含有率来改变基板的线膨胀系数、热传导率、介电常数等，可以容易地制造具备多种特性的电路部件内装模块。例如，通过使基板的线膨胀系数与半导体芯片的线膨胀系数接近能够有效地防止温度变化所引起的裂缝的发生，此外，通过降低基板的介电常数能够制造介电损耗小的高频电路用模块。
再者，由于一般在把裸半导体芯片安装到基板上之前必须进行质量检验，故降低了操作性，因成本方面而受到限制，但是按照本制造方法，由于把半导体芯片内装于基板中的状态视为初期封装形态、能够检验半导体芯片的质量，故作为模块来说所谓KGD(已知可靠品模制)问题也可以解除了。在此，所谓KGD指的是，进行包含在加热状态下的导通检验等的检验(老化检验)，只把合格品作为封装品来处理。
(实施形态2)
图3A示出本实施形态的电路部件内装模块312的剖面图。电路部件内装模块312是这样的结构，把半导体芯片303以芯片厚度充分薄的晶片级的芯片比例封装(晶片级CSP)的形态内装于电绝缘性基板301中。另外，还一体化地装入了多层基板303a。302a是在电绝缘性基板301的主面上形成了的布线图形。302b是在电绝缘性基板301的另一主面上形成了的布线图形。通过贯穿电绝缘性基板301而形成了的内通路304，把布线图形302a与302b电连接起来。
图3B示出把晶片级CSP 303a安装到再布线用的多层基板306中的结构例。通过金属凸点305把电路部件内装模块312与多层基板306连接起来。
半导体芯片303的厚度为30～100μm是必要的，较为理想的是30～50μm。超过100μm时，不能使电路部件内装模块312薄型化，当实现高密度安装时有时会产生不方便。此外，电路部件内装模块312的厚度为300～600μm。
按照图3A所示的结构，在使用管脚个数少的晶片级CSP 303a的情况下，由于在对于晶片级CSP 303a进行倒装芯片安装的同时来形成包含再布线的布线图形，故不需要再布线用的多层基板，相应地使模块更加有效地薄型化。另一方面，如图3B所示，在需要再布线用的多层基板306的情况下，更加显著地发现使电路部件内装模块312薄型化了的效果，对于高密度安装贡献很大。
此外，按照该结构，由于把半导体芯片303在CSP状态、即在保证了质量的形态下内装于电路部件内装模块312中，故还从根本上清除了KGD问题。
图3C及图3D示出把另一半导体封装体307安装到多层基板306或电绝缘性基板301中并进行了层叠之例。这样，如果把在电绝缘性基板301的至少主面上形成了的布线图形做成与多层基板306的第1层上的布线图形一致的结构，则电路部件内装模块312的应用范围展宽了。例如，在把具有CPU功能的半导体芯片303加工成薄型的、并将其内装于电绝缘性基板中之后，如果在其上安装具有存储器功能的半导体封装体307(存储器封装体)、并进行层叠，就能够构成薄型且节省空间的功能快。
以下，一边参照图4A～图4C，一边说明本实施形态的电路部件内装模块312制造方法之一例。
首先，如图4A所示，利用回流处理在多层基板406上对于晶片级CSP 403a进行倒装芯片安装，利用砂轮等研磨半导体芯片403，一直研磨到图中的研磨线为止，将其加工成厚度为30～100μm，较为理想的是30～50μm。在此，利用了研磨法，但除此以外，还可以利用抛光等研磨法、放电加工法进行加工。但是，在以高速进行加工的情况下，把多层基板306固定在金属模卡具等上、利用研磨法来进行是较为理想的。按照该方法，能够不引起损伤、以高速、把厚度约为200～400μm的半导体芯片容易地加工成约为50～100μm
接着，如图4B所示，把安装了晶片级CSP 403a的多层基板406与合成片401重叠、并进行加压，把晶片级CSP 403a埋入合成片401中。其次，在合成片401的混合物硬化的温度以上的温度(例如150°～260℃)下进行加热。由此，合成片401成为电绝缘性基板401a(图4C)。412为电路部件内装模块。
其后，例如如图4C所示，也能够把存储器封装体407安装到多层基板406上、并进行层叠。按照该制造方法，即使层叠存储器封装体407，也能够稳定地制造总厚度T为1～2mm的薄型电路部件内装模块412。此外，由于使用利用回流处理安装了晶片级CSP的多层基板，故能够提高生产效率。
(实施形态3)
图5示出本实施形态的电路部件内装模块512的剖面图。与实施形态1的电路部件内装模块112对应的构件由进行了同样处理的同种材料构成。电路部件内装模块512是，在将其上表面互相对置起来的状态下、把半导体芯片503a及503b内装于电绝缘性基板501中的结构。502b及502c为在电绝缘性基板501的主面上形成了的布线图形，502a及502d为在电绝缘性基板501的另一主面上形成了的布线图形。通过贯穿电绝缘性基板501而形成了的内通路504，把布线图形502a与502b电连接起来。通过凸点505，把半导体芯片503a及503b分别与布线图形502d、布线图形502c电连接起来。在半导体芯片503a与503b之间形成了由无机填料及热硬化树脂构成的、厚度为50～100μm的缓冲层507。506是电绝缘性片的层。
按照该结构，能够把半导体芯片更加高密度地安装到电路部件内装模块中。当把电路部件内装模块层叠起来作成多级层叠模块时，该效果变得更加显著。
以下，一边参照图6A～E，一边说明本实施形态的电路部件内装模块512制造方法之一例。
首先，如图6A所示，预先使用通过电镀在布线图形602b、602c上形成了Ni和Cu层的脱模载体607a，通过凸点605b在布线图形602c上对于厚度为200～400μm的半导体芯片603a进行倒装芯片安装。其次，利用砂轮等研磨半导体芯片603a，一直研磨到图中的研磨线为止，将其加工成厚度为30～100μm，较为理想的是30～50μm。
其次，如图6B所示，把0603尺寸的片状电容器603c安装到脱模载体607a上的布线图形602b上。在利用底填材料等密封树脂来增强半导体芯片603a与布线图形602c的连接部的情况下，如果假定与片状电容器603c的隔开距离为0.5mm以内对半导体芯片603a进行倒装芯片安装，则由于密封树脂溢出约0.5mm而成为妨碍，故使用其面积大致与半导体芯片603a的占有面积相同的电绝缘性膜(NCF)来代替密封树脂，是较为理想的。
其次，如图6c所示，一边加以注意以使贯穿孔604的位置及形状不失真，一边对于具有贯穿孔604的合成片601、安装了半导体芯片603a及片状电容器603c的脱模载体607a、及安装了半导体芯片603b的脱模载体607b进行位置重合，这样来进行重叠。605a为脱模载体上的凸点。
其次，进行加压，如图6D所示，在把半导体芯片603a、603b埋入合成片601中之后，在合成片601的混合物及贯穿孔604中的导电性树脂硬化的温度以上的温度(例如150°～260℃)下进行加热。由此，合成片601成为电绝缘性基板601a，贯穿孔604中填充了导电性树脂而成为内通路604a。
其后，如图6E所示，把脱模载体607a、607b分别从电绝缘性基板601a机械地剥离，把布线图形602a、602b转移到电绝缘性基板601a上而得到电路部件内装模块612。在此，在电绝缘性基板601a的厚度方向上内装了2个半导体芯片，单体模块相对地变厚，与此相应，脱模载体的剥离变得容易。
按照该制造方法，由于第二板状体(电绝缘性基板601a)包含无机填料及热硬化树脂成分，故能够不使半导体芯片及无源元件受到损伤来制造内装了半导体芯片及无源元件的模块。因而，也能够把例如0603尺寸的电容器片等体积大的无源元件及薄膜状的无源元件内装于模块中了。而且，利用该制造方法能够使半导体芯片与无源元件靠近配置，消除了包含电路部件最佳配置的电路基板结构设计上的限制。
(实施形态4)
图7B示出本实施形态的多级层叠模块712的剖面图。多级层叠模块712是多级层叠实施形态1的电路部件内装模块112的结构。
以下，一边参照图7A～B，一边说明本实施形态的多级层叠模块712的制造方法之一例。
首先，除了假定加热温度为100°～130℃的范围、以使合成片701的混合物及贯穿孔704中的导电性树脂组成物保持半硬化或部分硬化的状态(B级状态)的原样以外，与实施形态1同样来制造电路部件内装模块701a～701d(图7A)。
其次，一边控制压力一边进行层叠，把各电路部件内装模块作成4级结构的多级层叠模块712(图7B)。在图7A～B中，702a～702b为在内通路704的两表面上形成了的布线，703a～703d为半导体芯片，705为在半导体芯片的表面上形成了的凸点，707a、707b为脱模载体。
再有，多级层叠模块712可以是依次进行层叠的模块，或者是汇总进行层叠的模块。在汇总进行层叠的情况下，不需要转移布线图形的工序等，能够简化制造工序。
按照本实施形态，例如在作成4级结构的情况下，可得到厚度为400～600μm的薄型多级层叠模块。
(实施形态5)
图9B示出本实施形态的多级层叠模块813的剖面图。
多级层叠模块813是在相邻的电路部件内装模块间配设了树脂片811的状态下、多级层叠实施形态2的电路部件内装模块512的结构。
按照该结构，能够在厚度方向上把内装于电路部件内装模块中的半导体芯片的端子再布线部2层化，能够使布线图形立体交叉，提高了电路基板在结构设计上的自由度。例如，当作成8级结构的多级层叠模块时，厚度约为1mm且是薄型的，应用范围展宽了。例如，可得到在安装于母板中的状态下、总厚度为1.5mm以下的多级层叠模块。
以下，一边参照图8A～D及图9A～B，一边说明本实施形态的多级层叠模块813的制造方法之一例。
首先，除了假定加热温度为100°～130℃的范围、以使合成片801的混合物及贯穿孔804中的导电性树脂组成物保持半硬化或部分硬化的状态(B级状态)的原样以外，与实施形态2同样来制造电路部件内装模块810。
其次，如图8A所示，机械地剥离电路部件内装模块810的单面脱模载体807a。803a、803b为半导体芯片，807b为背面的脱模载体。
其次，如图8B所示，把具有内通路804b的树脂片811(B级状态)配置到相邻的电路部件内装模块810a、810b间，从电路部件内装模块的剥离了脱模载体的粘贴面一侧一边加以注意，一边对于811、810a、810b进行位置重合，这样来进行重叠。
其次，进行加压，在作成图8c所示那样的层叠状态之后，在合成片801、树脂片811、及贯穿孔804中的热硬化树脂硬化的温度以上的温度(例如150°～260℃)下加热层叠物。在此，也可以把加热温度抑制在约130℃来维持B级状态。作为树脂片811的材料只要是B级状态的材料就不作特别限定，但可使用与合成片801中使用了的混合物相同组成的混合物，较为理想的是使用其无机填料的含量与合成片801中使用了的混合物相等的混合物。
然后，如图8D所示，机械地剥离多级层叠模块812的上、下表面的脱模载体807a、807b。
其后，如图9A所示，把树脂片811b(B级状态)配置到相邻的多级层叠模块812a与812b间，进而，把树脂片811a及811c(B级状态)分别配置到层叠物的上、下，一边加以注意，一边进行位置重合，这样来重叠并进行加压、在层叠起来以后，在合成片801、树脂片811、及贯穿孔804中的未硬化的热硬化树脂硬化的温度以上的温度(例如150°～260℃)下进行加热，得到图9B所示那样的、8级结构的多级层叠模块813。
按照该制造方法，通过只从电路部件内装模块的单面剥离脱模载体来进行层叠，在加压时由脱模载体保护布线图形、可防止布线图形的空气氧化。此外，树脂片811作为避免单体模块的接触的缓冲层而起作用，可有效地防止在层叠加压时半导体芯片的损伤。
此外，通过剥离多级层叠模块的上、下主面的脱模载体而使端子电极露出来，能够在层叠成多级之前更加完全地进行导通检验等质量检验。
(实施形态6)
图10D示出本实施形态的多级层叠模块912的剖面图。多级层叠模块912是在实施形态5的多级层叠模块813中，使用配置了薄膜状电容器914及薄膜状电阻913的连接用片915、来代替树脂片811的结构。
按照该结构，能够把薄膜状电容器配置成为比模块厚度所相应的隔开距离更靠近于半导体芯片，能够使电容器作为旁路电容器而有效地起作用。此外，还能够使电容器大容量化。
以下，一边参照图10A～D及图11A～C，一边说明本实施形态的电路部件内装模块的制造方法之一例。
首先，与实施形态5同样来制造电路部件内装模块910。然后，如图10A所示，机械地剥离电路部件内装模块910的单面脱模载体907a。901为合成片，903a、903b为半导体芯片，904为内通路，905为凸点，907b为背面的脱模载体。
另外，如图11A～C所示，预先制作连接用片915。首先，如图11A所示，对于在表面上印刷了薄膜状电容器914的脱模载体907a、印刷了薄膜状电阻913的脱模载体907b、及具有贯穿孔904的树脂片911进行位置重合、这样来进行重叠，作成图11B所示那样的层叠状态。在此，在脱模载体907a、907b上形成了规定的布线图形。此外，电容器914及电阻913是利用蒸镀、溅射、MOCVD(金属有机化学气相淀积)等薄膜形成法、或丝网印刷等在脱模载体907a、907b上形成的。此外，作为树脂片911的材料只要是B级状态的材料就不作特别限定，但可使用与合成片901中使用了的混合物相同组成的混合物，较为理想的是使用其无机填料的含量与合成片901中使用了的混合物相等的混合物。其次，如图11C所示，从树脂片911的上、下表面机械地剥离脱模载体907a、907b，在把电阻913及电容914转移到树脂片911上之后将其埋入到911中，制作连接用片915。
以下，与实施例5同样，如图10B所示，把连接用片915配置到相邻的电路部件内装模块910、910间，对于910、915、910进行位置重合，这样来重叠并进行加压，作成图10C所示那样的层叠状态，如图10D所示，从多级层叠模块912的上、下表面机械地剥离脱模载体907a、907b。
由此，得到4级层叠了半导体芯片的多级层叠模块912。
按照本实施形态，由于能够把旁路电容器配置在极靠近裸半导体端子电极处，故能够发挥噪声特性良好的特性。

Claims (27)

1.一种电路部件内装模块，它包含：由包含无机填料及热硬化树脂的混合物构成的电绝缘性基板、及在上述电绝缘性基板的至少主面上形成了的多个布线图形；
内装于上述电绝缘性基板中、与上述布线图形电连接起来的半导体芯片；以及
以把上述多个布线图形电连接的方式贯穿上述电绝缘性基板而形成了的内通路，该模块的特征在于，
上述半导体芯片的厚度为30μm以上、100μm以下，且非布线面为研磨面，
上述电路部件内装模块的厚度在80μm以上、200μm以下的范围内。
2.根据权利要求1中所述的电路部件内装模块，其特征在于，上述半导体芯片为晶片级的芯片比例封装(CSP)半导体。
3.根据权利要求1中所述的电路部件内装模块，其特征在于，在使其上表面互相对置的状态下、在厚度方向上埋入了2个上述半导体芯片。
4.根据权利要求1中所述的电路部件内装模块，其特征在于，进而，在上述电绝缘性基板的另一主面上也形成了上述布线图形，在上述电绝缘性基板中，在将其上表面互相对置起来的状态下、在上述电绝缘性基板的厚度方向上内装了2个上述半导体芯片，
上述2个半导体芯片中的一个与在上述电绝缘性基板的主面上形成了的布线图形电连接起来，另一个与在上述电绝缘性基板的另一主面上形成了的布线图形电连接起来。
5.根据权利要求1中所述的电路部件内装模块，其特征在于，在上述电绝缘性基板的至少主面上形成了的布线图形是在上述电绝缘性基板上层叠了的多层布线基板的表层上的布线图形的一部分。
6.根据权利要求1中所述的电路部件内装模块，其特征在于，进而把无源部件内装于上述电绝缘性基板中，把上述无源部件与上述多个布线图形的某一个电连接起来。
7.根据权利要求6中所述的电路部件内装模块，其特征在于，上述无源元件是从电感、电容器及电阻中选择的至少一种。
8.根据权利要求1中所述的电路部件内装模块，其特征在于，利用底填树脂、电绝缘性膜(NCF)、或包含导电粒子的各向异性导电膜(ACF)增强了上述半导体芯片与上述布线图形的连接部。
9.根据权利要求1中所述的电路部件内装模块，其特征在于，层叠4～8层上述电路部件内装模块来形成多级层叠模块，由上述内通路把相邻的电路部件内装模块电连接起来。
10.根据权利要求1中所述的电路部件内装模块，其特征在于，把具备内通路的电绝缘性基板，配置在上述相邻的电路部件内装模块间，把上述电绝缘性基板作成与构成上述电路部件内装模块的电绝缘性基板为同一组成物。
11.根据权利要求9中所述的电路部件内装模块，其特征在于，层叠4～8层上述电路部件内装模块来形成多级层叠模块，把具备内通路的电绝缘性基板配置在相邻的电路部件内装模块间，把薄膜状的无源元件配置在上述电绝缘性基板上。
12.根据权利要求1中所述的电路部件内装模块，其特征在于，上述电路部件内装模块的厚度为100～150μm。
13.一种电路部件内装模块的制造方法，该模块包含：由包含无机填料及热硬化树脂的混合物构成的第1电绝缘性基板、及在上述电绝缘性基板的至少主面上形成了的多个布线图形；
内装于上述电绝缘性基板中、与上述布线图形电连接起来的半导体芯片；以及
以把上述多个布线图形电连接的方式贯穿上述电绝缘性基板而形成了的内通路，该制造方法的特征在于包含：
准备在上述电绝缘性基板上开设贯穿孔、在该孔中填充了热硬化导电性物质的板状体的工序；
把半导体芯片安装到在脱模载体上形成了的布线图形上的工序；
研磨上述半导体芯片的非布线面，将其作成厚度为30μm以上、100μm以下的工序；
在上述脱模载体的形成了布线图形的面上以使在上述贯穿孔中填充了导电性物质的部分与上述布线图形一致的方式对上述板状体进行位置重合，通过这样来进行重叠及加压，把上述半导体芯片埋入上述板状体中的工序；
通过加热上述埋入体，使上述混合物与上述导电性物质同时硬化得到厚度在80μm以上、200μm以下的电路部件内装模块的工序；以及
剥离上述脱模载体的工序。
14.根据权利要求13中所述的电路部件内装模块的制造方法，其特征在于，把上述半导体芯片埋入上述板状体中的工序是，使用2个形成了上述布线图形的脱模载体夹住上述板状体进行位置重合，通过这样来进行重叠及加压，把2个半导体芯片在使其上表面互相对置的状态下、在厚度方向上埋入上述板状体中的工序。
15.根据权利要求13中所述的电路部件内装模块的制造方法，其特征在于，
进而，在上述电绝缘性基板的另一主面上也形成了上述布线图形，
在上述电绝缘性基板中，在将其上表面互相对置起来的状态下、在上述电绝缘性基板的厚度方向上内装了2个上述半导体芯片，
上述2个半导体芯片中的一个与在上述电绝缘性基板的主面上形成了的布线图形电连接起来，另一个与在上述电绝缘性基板的另一主面上形成了的布线图形电连接起来。
16.根据权利要求13中所述的电路部件内装模块的制造方法，其特征在于，在上述电绝缘性基板的至少主面上形成了的布线图形是在上述电绝缘性基板上层叠了的多层布线基板的表层上的布线图形的一部分。
17.根据权利要求13中所述的电路部件内装模块的制造方法，其特征在于，进而把无源部件内装于上述电绝缘性基板中，把上述无源部件与上述多个布线图形的某一个电连接起来。
18.根据权利要求17中所述的电路部件内装模块的制造方法，其特征在于，上述无源元件是从电感、电容器及电阻中选择的至少一种。
19.根据权利要求13中所述的电路部件内装模块的制造方法，其特征在于，利用底填树脂、电绝缘性膜(NCF)、或包含导电粒子的各向异性导电膜(ACF)增强了上述半导体芯片与上述布线图形的连接部。
20.根据权利要求13中所述的电路部件内装模块的制造方法，其特征在于，在层叠4～8层上述电路部件内装模块来形成多级层叠模块时，由上述内通路把相邻的电路部件内装模块电连接起来。
21.根据权利要求20中所述的电路部件内装模块的制造方法，其特征在于，把具备内通路的第2电绝缘性基板配置在上述相邻的电路部件内装模块间，把上述第2电绝缘性基板作成与构成上述电路部件内装模块的第1电绝缘性基板为同一组成物。
22.根据权利要求13中所述的电路部件内装模块的制造方法，其特征在于，在层叠4～8层上述电路部件内装模块来形成多级层叠模块时，把具备内通路的电绝缘性基板配置在相邻的电路部件内装模块间，把薄膜状的无源元件配置在上述电绝缘性基板上。
23.根据权利要求13中所述的电路部件内装模块的制造方法，其特征在于，上述电路部件内装模块的厚度为100～150μm。
24.根据权利要求13中所述的电路部件内装模块的制造方法，其特征在于，上述脱模载体为金属片或树脂片。
25.根据权利要求24中所述的电路部件内装模块的制造方法，其特征在于，上述树脂片为从聚酰亚胺、聚对苯二甲酸乙二酯、聚乙烯萘、聚苯撑亚硫酸盐、聚乙烯、聚丙烯、及氟树脂中选择的至少一种树脂膜。
26.根据权利要求24中所述的电路部件内装模块的制造方法，其特征在于，上述金属片是铜箔。
27.根据权利要求13中所述的电路部件内装模块的制造方法，其特征在于，上述脱模载体是铜箔，上述布线图形是铜箔，上述脱模载体与上述布线图形间的剥离层由铬电镀层形成。
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