CN1439176A - 在GaN基板上的发光二极管芯片和用GaN基板上的发光二极管芯片制造发光二极管元件的方法 - Google Patents

在GaN基板上的发光二极管芯片和用GaN基板上的发光二极管芯片制造发光二极管元件的方法 Download PDF

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CN1439176A
CN1439176A CN01808734A CN01808734A CN1439176A CN 1439176 A CN1439176 A CN 1439176A CN 01808734 A CN01808734 A CN 01808734A CN 01808734 A CN01808734 A CN 01808734A CN 1439176 A CN1439176 A CN 1439176A
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CN1252837C (zh
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S·巴德·B·哈赫恩
V·赫尔勒
H·-J·卢高尔
M·芒德布罗德－范格罗
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Abstract

本发明涉及两种发光二极管芯片。一种芯片具有一个导电的和辐射能穿透的衬底，外延层序列(3)在其背离衬底(2)的p型区(9)上基本上整个面积设置了一层反射的、可压焊的p型接触层(6)，衬底(2)在其背离外延层序列(3)的主面(10)上设置了一层金属化接触(7)，该接触只覆盖该主面(10)的一部分；从芯片(1)的光输出是通过衬底(2)的主面(10)的自由区和通过芯片侧面(14)来实现的。另一种发光二极管芯片则只具有外延层，p型导电外延层(5)在其背离n型导电外延层(4)的主面(9)上基本上整个面积设置了一层反射的、可压焊的p型接触层(6)，而n型导电外延层(4)则在其背离p型导电外延层(5)的主面(8)上设置了一层n型接触层(7)，该接触层只覆盖该主面的一部分；从芯片(1)的光输出是通过n型导电外延层(4)的主面(8)的自由区和通过芯片侧面(14)来实现的。

Description

在GaN基板上的发光二极管芯片和用GaN基板上的 发光二极管芯片制造发光二极管元件的方法
本发明涉及权利要求1或4的前序部分所述的一种发光二极管芯片以及用GaN基板上的发光二极管芯片制造发光二极管元件的一种方法。
在GaN基板上制造发光二极管芯片时存在的基本问题是，p型掺杂的层尤其是p型掺杂的GaN层或AlGaN层可达到的电导率满足不了这样的要求，即：在用别的材料系统制成常规发光二极管芯片的情况下，为了达到尽可能高的辐射输出，一般用的端面接触只覆盖芯片正面的很小一部分，以至电流不能扩展到芯片的整个横断面。
在一个导电的衬底上生长p型导电层，从而可在p型导电层的整个横断面上注入电流，导致了不可接受的经济后果。其原因在于：制造导电的晶格匹配的衬底(例如GaN衬底)，在生长基于GaN的各层时需要付出高昂的技术费用；在对未掺杂的和n型掺杂的GaN连接不适合的晶格匹配的衬底上生长p型掺杂的基于GaN的各层时，导致对发光二极管不足的差的晶体质量。
在解决上述问题的一个已知的方案中，在背离衬底的p型导电层的一侧上设置了一层辐射能穿透的整个面积的接触层或附加的一层导电良好的电流扩展层，该层设置有压焊接触。
但上述第一方案的缺点是，辐射的相当大的一部分在接触层被吸收。而在上述第二方案时，则需要一道附加的工序，从而导致制造费用的增加。
日本专利摘要JP 10-150 220A公开了一种发光半导体器件，这种器件在一个n型GaN衬底上依次设置了一层n型GaN半导体层、一层发光层和一层p型GaN半导体层。在p型GaN半导体层的表面上布置了一个基本上完全覆盖了该层的p型电极。
本发明的目的是：首先开发一种具有改善电流扩展的上述发光二极管芯片，这种芯片的附加制造费用很少；其次，提出用这种芯片制造发光二极管元件的一种方法。
上述的第一目的是通过权利要求1或权利要求4的特征部分所述的一种发光二极管芯片来实现的，有利的各项改进可从各项从属权利要求中得知。本发明发光二极管芯片的优选制造方法是权利要求9至14的内容。权利要求15给出了一个优选的发光二极管元件。
根据本发明的一种发光二极管芯片，衬底是导电的。在该衬底上，首先设置一个外延层序列的n型导电层，在这个外延层序列上设置外延层序列的p型导电层，然后设置一层横向整个面积反射的、可压焊的p型接触层。该衬底在其背离外延层序列的主面上设置有金属化接触，该接触只覆盖该主面的一部分。从芯片的光输出是通过衬底主面的自由区和通过芯片侧面来实现的。
该衬底在这里优选起窗口层的作用，该层改进了芯片内产生的辐射的输出。为了衬底厚度的最佳化，该衬底最好在生长外延层序列后例如用磨削和/或腐蚀进行减薄。
根据本发明的另一种发光二极管芯片，该芯片只具有外延层。为此，在外延层序列的外延生长后要把生长衬底去掉。p型导电外延层在其背离n型导电外延层的主面上基本上整个面积都设置了一层反射的、可压焊的p型接触层，在离p型导电外延层的n型导电外延层的主面上设置一层只覆盖该主面一部分的n型接触层。从芯片的光输出是通过n型导电外延层的主面自由区和通过芯片侧面来实现的。
在这种情况中，该生长衬底既可以是电绝缘的又可以是辐射不能穿透的并因此而可按有利的方式单独地选择最佳的生长条件。
这种所谓的薄膜发光二极管芯片的独特优点是，特别是由于具有折射率跃变的界面的数目减少，在芯片中的辐射吸收减少到理想的程度并改善了芯片的辐射输出。
本发明两种发光二极管芯片的独特优点是：可把芯片产生损耗热的区域(特别是p型掺杂层和pn结)直接放在散热器附近；外延层序列实际上直接与一个散热器进行连接。这样，芯片可很有效地进行冷却，从而提高输出辐射的稳定性。同样也提高了芯片的效率。
由于整个面积的接通，本发明的两种发光二极管芯片以有利的方式降低了正向电压。
在用本发明发光二极管芯片时，p型接触层具有一层设置p型区上的透明第一层和一层设置在该透明层上的反射第二层。这样，接触层就可按简单的方式既可在其电性能又可在其反射性能方面达到最佳化。
上述第一层和第二层的优选材料为Pt和/或Pd或Ag、Au和/或Al。但反射层也可作为介质反射镜构成。
在另一种优选方案中，p型接触层具有一种PtAg合金和/或PdAg合金。
在又一种优选的结构型式中，由层序列形成的半导体的整个外露表面或其中的一部分区域进行了打毛。通过这种打毛使输出面的总反射受到干扰，从而有利于进一步提高光的输出率。
在用本发明发光二极管芯片制造发光二极管元件的本发明方法中，具有p型区的芯片安装在电连接部分尤其是芯片引线架的一个芯片装配面上。
在本发明的一个特别优选的方案中，通过对层序列形成的半导体本体的打毛继续进行制造处理，其中，半导体本体的整个外露表面或其部分区域被打毛。对发光效率的提高特别有效的打毛是通过对半导体本体进行腐蚀或用喷砂方法来实现的。
本发明的其他有利结构可从下面结合附图1a至5所述的实施例中得知。附图表示：
图1a        第一实施例的一个示意断面图；
图1b        优选的p型接触层的示意图；
图2         第二实施例的一个示意断面图；
图3a至3c    图1a实施例的制造工艺过程的示意图；
图4a至4e    图2实施例的制造工艺过程的示意图；
图5         本发明发光二极管芯片的另一个实施例的示意断面图。
在不同实施例的附图中，相同或作用相同的部分分别用相同或相似的附图标记表示。
在图1a的发光二极管芯片1中，在一个SiC衬底2上设置了一个发光的外延层序列3。该外延层序列例如具有一层n型导电掺杂的GaN或AlGaN外延层4和一层p型导电掺杂的GaN或AlGaN外延层5。同样，例如一个基于GaN的外延层序列3可具有一个双异质结构、一个单量子井(SQW)结构(Einfach-Quantenwell-Struktur)或一个带一层或多层未掺杂层19的多量子井(MQW)结构，例如用InGaN或InGaAlN制成。
SiC衬底2是导电的并对外延层序列3发出的辐射是可穿透的。
在其背离SiC衬底2的p型区9上，在外延层序列3上基本上整个面积设置了一层反射的、可压焊的p型接触层6，该接触层例如主要用Ag、用一种PtAg合金和/或用一种PdAg合金制成。
但如图1b示意图所示，p型接触层6也可用辐射能穿透的第一层15和反射的第二层16组成。第一层15例如主要用Pt和/或Pd制成，而第二层16则例如主要用Ag、Au和/或Al或一层介电的反射层制成。
在其背离外延层序列3的主面10上，SiC衬底2设置了金属化接触7，该接触只覆盖该主面10的一部分并作为丝焊法键合用的焊盘构成。金属化接触7例如由一层设置在SiC衬底2上的Ni层和紧接着的一层Au层组成。
芯片1用模片结合法用其p型区即用p型接触层6装配到芯片面性引线架11的芯片装配面12上。n型金属化接触7通过一根压焊丝17与芯片引线架11的连接部分18连接。
芯片1的光输出是通过SiC衬底2的主面10的自由区域和通过芯片侧面14来实现的。
芯片1在外延层序列3生长后可选择地具有一个减薄的SiC衬底2(在图1a中用虚线表示)。
图2所示实施例与图1a的区别在于，芯片1只具有外延序列3的外延层而没有衬底层。在外延层生长后，衬底层例如用腐蚀和/或磨削去掉。关于这种所谓薄膜发光二极管芯片的优点可参看本说明书的综述部分。另一方面，外延层序列3具有一个双异质结构、一个单量子井结构或一个带一或多层未掺杂层19的多量子井结构，例如用InGaN或InGaAlN制成。这里还举例示意示出了一个发光二极管封装21。
图3a至3c表示用图1a的发光二极管芯片1制造发光二极管元件的示意工艺过程：首先在SiC衬底2上生长发射光的外延层序列3(图3a)，然后在外延层序列3的p型区9上整个面积设置可压焊的p型接触层6和在衬底2离外延层序列3的主面10的部分区域设置n型接触层7(图3b)。这些工艺过程全在所谓的复合晶片内进行，从而可同时制作许多芯片。
在上述工艺过程结束后，将复合晶片分割成单个芯片1。然后将这些单个芯片借助于焊接分别用可压焊的p型接触层6安装在一个芯片引线架11的芯片装配面12上(图3c)。
图4a至4e所示的用图2发光二极管芯片1制造发光二极管元件的方法与图3a至3c所示方法的主要区别在于，在外延层序列3生长后和p型接触层6设置之前或之后去掉了衬底2(图4c)。在这种情况中，衬底2既可以是电绝缘的又可以是辐射穿不透的，因而可按有利方式单独地选择最佳的生长条件。
在去掉衬底2后，在进行类似于上面结合图3c所述的装配步骤之前(图4e)，在外延层序列3的n型区13上设置n型金属化接触7(图4d)。
图5所示的实施例具有许多叠层式布置的不同的半导体层101，这些半导体层用GaN或其三元或四元化合物制成。在运行过程中，在这些层的里面构成一个产生辐射105的活性区102。
层叠被第一个主面103和第二个主面104限定。产生的辐射105主要通过第一主面103输出到邻域中。
如上所述，在第二主面104上设置了一层反射的可压焊的p型接触层106。在发射侧上的半导体通过接触面112接通，而反射器侧的半导体则通过p型接触层106接通。反射器侧的接通例如可这样来实现，半导体本体在反射器侧放置在一个金属体上，该金属体既作为载体又作为电流引线使用。
反射器106使在第一主面103上输出时反射到半导体本体的辐射105的一部分重新在第一主面103的方向内反射，所以总的来说，增加了由第一主面103输出的辐射量。这种辐射量的增加是这样实现的，该元件作为薄膜元件构成而没有吸收辐射的衬底，且反射器106直接设置在GaN半导体本体上。
在这种情况下，半导体本体的表面具有打毛层107，打毛层107引起辐射105在第一主面103上散射，从而使第一主面103上的总反射受到干扰。这种散射在很大程度上阻止了产生的辐射通过连续的相同的反射象光导体那样在两个主面103和104或反射器106之间通导，而不离开该半导体本体。所以通过打毛层107进一步增加了发光效率。
当然，本发明不受上述实施例的限制。确切地说，本发明特别适用于所有这类位于离一个生长衬底较远的外延层导电率不够的发光二极管芯片。

Claims (15)

1.发光二极管芯片(1)，具有一个发光的外延层序列(3)，该外延层序列具有带n型导电区(8)的GaN基体上的一层n型导电外延层(4)和一层p型导电外延层(5)并设置在一个导电的衬底(2)上，该衬底(2)对该外延层序列(3)发出的辐射是可穿透的，外延层序列(3)在其背离衬底(2)的p型区(9)上基本上整个面积设置了一层反射的、可压焊的p型接触层(6)，衬底(2)在其背离外延层序列(3)的主面(10)上设置了金属化接触(7)，该接触只覆盖该主面(10)的一部分，从芯片(1)的光输出是通过衬底(2)的主面(10)的自由区和通过芯片侧面(14)来实现的，
其特征为，
p型接触层(6)具有一层设置在P型区(9)上的透光的第一层(15)和一层设置在该第一层上的反射的第二层(16)。
2.按权利要求1的发光二极管芯片(1)，
其特征为，
在设置外延层序列(3)后，设置一层减薄的衬底(2)。
3.按权利要求1或2的发光二极管芯片(1)，
其特征为，
作为导电衬底(2)采用一个碳化硅衬底。
4.在GaN基体上具有一个发光外延层序列(3)的发光二极管芯片(1)，该外延层序列具有一层n型导电外延层(4)和一层p型导电外延层(5)，其特征为：
在外延层序列(3)的外延生长后，芯片(1)借助于一个生长衬底的去掉而只具有外延层，p型导电外延层(5)在其背离n型导电外延层(4)的主面(9)上基本上整个面积设置了一层反射的、可压焊的p型接触层(6)，而n型导电外延层(4)则在其背离p型导电外延层(5)的主面(8)上设置了一层n型接触层(7)，该接触层只覆盖该主面的一部分；从芯片(1)的光输出是通过n型导电外延层(4)的主面(8)的自由区和通过芯片侧面(14)来实现的。
5.按权利要求4的发光二极管芯片，
其特征为，
p型接触层(6)具有一层设置在p型区(9)上的透光的第一层(15)和一层设置在该第一层上的反射的第二层(16)。
6.按权利要求1、2、4或5任一项的发光二极管芯片，
其特征为，
第一层(15)主要具有Pt和/或Pd，而第二层(16)则主要具有Ag、Au和/或Al或作为介质反射镜构成。
7.按权利要求4的发光二极管芯片，
其特征为，
p型接触层(6)具有一种PtAg合金和/或PdAg合金。
8.按前述权利要求任一项的发光二极管芯片，
其特征为，
层序列(3、101)的整个外露表面或其一部分被打毛。
9.用GaN基板上的发光二极管芯片(1)制造发光二极管元件的方法，其工艺步骤是：
a)在一个衬底(2)上外延生长一个发光的外延层序列(3)，该衬底对从外延层序列(3)发出的辐射是可以穿透的，外延层序列(3)的一个n型区(8)面向该衬底(2)，而外延层序列(3)的一个p型区(9)则背离衬底(2)；
b)通过在p型区(9)上设置透光的第一层(15)和在第一层(15)上设置反射的第二层(16)而在外延层序列(3)的p型区(9)上整个面积设置一层可压焊的p型接触层(6)；
c)在背离外延层序列(3)的衬底(2)的一个主面(10)的一部分区域上设置n型接触层(7)；
d)用朝芯片装配面的可压焊的p型接触层(6)把芯片(1)安装到一个发光二极管封装的或一个发光二极管封装内的一根印制导线的或一个电引线架(11)的芯片装配面(12)上。
10.按权利要求9的方法，
其特征为，
在设置n型接触层(7)之前，衬底(2)被减薄。
11.用GaN底板上的发光二极管芯片(1)制造发光二极管元件的方法，其工艺步骤是：
a)在一个衬底(2)上这样外延生长一个发光的外延层序列(3)，使外延层序列(3)的一个n型区(8)面向衬底(2)，而该外延层序列的一个p型区(9)则背离衬底(3)；
b)通过在p型区(9)上设置透光的第一层(15)和在第一层(15)上设置反射的第二层(16)而在外延层序列(3)的p型区(9)上整个面积设置一层可压焊的p型接触层(6)；
c)去掉外延层序列(3)的衬底(2)；
d)把一层n型接触层(7)设置到外延层序列(3)的在步骤c)露出的主面(13)的一部分区域上；
e)用朝芯片装配面的可压焊的p型接触层(6)把芯片(1)安装到一个发光二极管封装的或一个发光二极管封装内的一根印制导线的或一个电引线架(11)的芯片装配面(12)上。
12.按权利要求9至11任一项的方法，
其特征为，
层序列(3，101)整个或部分区域被打毛。
13.按权利要求12的方法，
其特征为，
层序列(3，101)通过腐蚀打毛。
14.按权利要求12的方法，
其特征为，
层序列(3，101)通过喷砂方法打毛。
15.具有权利要求1至8任一项发光二极管芯片的发光二极管元件，其芯片(1)被安装在一个发光二极管封装(21)的芯片装配面(12)上，特别是一个芯片引线架(11)上或发光二极管封装的印制导线的装配面上，
其特征为，
反射的金属化接触(6)放在芯片装配面(12)上。
CNB018087345A 2000-04-26 2001-03-16 在GaN基板上的发光二极管芯片和用GaN基板上的发光二极管芯片制造发光二极管元件的方法 Expired - Lifetime CN1252837C (zh)

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