CN1408125A - 双注模集成电路封装 - Google Patents

双注模集成电路封装 Download PDF

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CN1408125A
CN1408125A CN00816866A CN00816866A CN1408125A CN 1408125 A CN1408125 A CN 1408125A CN 00816866 A CN00816866 A CN 00816866A CN 00816866 A CN00816866 A CN 00816866A CN 1408125 A CN1408125 A CN 1408125A
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integrated circuit
chips
injection molding
circuit encapsulation
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J·A·科瓦特斯
K·M·拉姆
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Atmel Corp
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Abstract

双注模集成电路封装(10)可容纳两个集成电路芯片(14，16)，该两个集成电路芯片采用“倒装芯片”的方式相互组合成一体且将一个芯片(14)与另一个芯片(16)之间的角度调整到一个指定的角度，使得每个芯片表面的焊盘都能将引线连接置入芯片封装之中。在第一实施例中，两个芯片在形状上都是矩形的且将两者之间的角度调整到90°，使得下层芯片的两端部分能用于芯片封装的连接。另一个实施例中，芯片相互之间的角度小于90°，使得每个芯片的角部能用于芯片的连接。本发明允许两个相同结构的芯片能使功能成倍或多倍地提供IC封装或存储器，然而仅使用用于单个芯片的相同封装引脚。另外，从晶片制造的观点来看，能采用两个具有相同结构的芯片有利于只要求一个IC工艺来实现。

Description

双注模集成电路封装
技术领域
本发明涉及集成电路封装，特别涉及具有多个半导体芯片(注模(dies))的集成电路封装。
背景技术
芯片封装是用于保护集成电路免受污染和机械损伤，并用于提供适用于集成电路与外部印刷电路板相连接或直接与电子产品相连接的耐用和牢固的电连接系统(electrical lead system)。多片集成电路(IC)封装具有许多超越单片封装的优点。采用将多个芯片直接设置在基片上的方法，可提供芯片和信号/电源引线之间的低电感和低电容的连接，可提供非常密的互联网络，从而可以提高封装的密度和系统的。采用非常优异的注模(die)—焊点(bump)—互连—焊点—注模的路径来取代注模—丝焊(wirebond)—引脚—电路板—丝焊—注模的路径，使得多片封装能减小芯片与芯片之间的空间以及减少安装在基片上芯片之间的电感和电容的断路。此外，在陶瓷基片上更细和更短的引线可具有比印刷电路板的互连方式要低得多得电容和电感。将多个相同的IC芯片集成在同一个封装中常常有利于提高存储器而不需要利用印刷电路板的有效空间。
参照图6，在已有技术中，将多个IC芯片组合在一个单一封装中的常用的方法是使用层叠的注模(die)IC封装50，在这种封装中，上层的IC芯片16小于下层的IC芯片14，以便集成电路引线26能与下层IC芯片14相连接。如图7的层叠IC多层封装60所示，如果两个IC芯片是同样尺寸的，则必须将上层IC芯片16与下层IC芯片14错开，以便集成电路的引线能与下层IC芯片14相连接。这就将集成电路的引线限制在封装的一侧或两侧，对装配来说，这种限制往往是不实际的。在已有技术中，组合相同尺寸的IC芯片的另一种方法也是众所周知的，如图8所示，就是将一个芯片放置于封装中下面的引线框18中。在图8的IC封装70中，上层IC芯片16是叠放在芯片引线框18的上面，而下层IC芯片14是置于引线框18的下面。图8注模置于下面的方法的缺点是芯片必须相互成镜像图像，从而要求两个完全匹配的IC制造步骤。
美国专利No.5,399,899中，Rostoker公开了一种多芯片多层半导体封装的排列，它基于单面和双面倒装芯片(flip chips)，。这种排列是基于类似于以上所讨论的图6和图7层叠的结构。在美国专利No.5,655,553中，Leas等公开了包括多个集成电路芯片的层叠平面延伸矩阵的制作方法和生产出的单一模块。在该专利中显示的层叠注模排列是采用边缘连接方法将上层注模于下层注模相连接。而在该层叠多片注模的方法用于层叠两个相同的注模的情况下，该方法就不具有路径设计上的灵活性，如电路的路径是垂直从上往下，如果存在着任意交叉时，芯片封装就不能很好地工作。
本发明的一个目的是提供具有两个或多个半导体IC芯片的多芯片IC封装。
本发明的另一个目的是提供具有两个或多个半导体IC芯片且不限制引线在芯片的一侧以及不要求两个完全匹配IC制作步骤的多芯片封装。
本发明的还有一个目的是提供在电路路径上具有灵活性的多芯片IC封装。
发明内容
为达到上述目的，能采用具有两个芯片(注模)的双注模集成电路封装，从晶片制作工艺的观点上看，这两个注模可以是同样构成的，并采用标准的焊料焊点和焊料回流工艺将两者相互结合在一起的“倒装芯片”。第一个芯片要调整到与第二个芯片有关的指定角度，以便至少各个芯片表面上的各个焊接引脚能露出来用于与标准芯片封装相连接。在本发明的实施例中，将两个矩形芯片调整到一个芯片与另一个芯片成90°的角度，使得不重叠的表面能暴露，以保证芯片封装的装配。在本发明的另一个实施例中，将芯片调整到小于90°的角度，使得至少各个芯片的小部分，例如角能暴露，以便芯片的装配。该实施例最适用于两个芯片是正方形的情况。在本发明的另一个实施例中，两个芯片是不同形状的，且大的芯片设置在小的芯片的上面以及旋转一个角度以便下面的芯片至少有一些小的面积可用于装配的。这种将大的IC芯片安装于小的IC芯片的能力更适用于那些可以控制小的注模的设计但可从其它货源购买到大的注模的IC制造商。
本发明在使用相同封装引脚作为一个芯片和仅仅使用一个IC设计时允许芯片封装的功能或容量加倍。本发明的集成电路封装在引线连接和路径方面允许具有灵活性，并可以在一个IC制作步骤中完成。本发明允许IC制造商能在非常短的时间周期内开发出容量或功能加倍的产品，仅仅采用所提供的将多个相同的芯片设置于相同的封装中的能力而不需要对芯片作明显的设计变化。
附图说明
图1是本发明的双注模集成电路封装的第一实施例的去除密封材料的俯视图。
图2是显示两个芯片之间连接的两个芯片的透视图。
图3是显示两个芯片置于引线框中的图1的双注模集成电路封装的俯视图。
图4是图1的双注模集成电路封装的侧视图。
图5是本发明的双注模集成电路封装的第二实施例的去除密封材料的俯视图。
图6是已有技术中的第一个层叠注模IC封装的侧视图。
图7是已有技术中的第二个层叠注模IC封装的侧视图。
图8是已有技术中的注模在下面的IC封装的侧视图。
具体实施方式
实施例1
参照图1，图1显示了本发明的集成电路(IC)封装10的第一实施例，它包括了上层IC芯片16和下层IC芯片14且将两者调整到相互间成90°的角度。芯片14，16设置在引线框18的平面注模附件的表面12。引线框18是由一片金属片组成并且从注模附件表面12延伸至多个输出引线20，输出引线排列在IC封装10的四周以及为了将IC封装安装在外部的印刷电路板上而向下延伸。
参照图2，采用标准焊料焊点和焊料回流工艺的“倒装芯片”方法将上层IC芯片16与下层IC芯片14机械连接和电连接。芯片16和芯片14之间的连接是采用各个芯片上的焊料焊点22来实现的，这些焊点以对角线或以“×”交叉的图形来排列。焊料焊点22可以作为部分常规制造工艺来制成，也可以增加电路径再区分工艺来制造。图2说明了采用再区分工艺的情况。在各个芯片14和16的常规制造芯片层23上，有许多以虚线来表示的焊盘49，排列在芯片的四周。在图2中，焊盘49分布在上层芯片16的下面17和下层芯片14的上面15。焊盘49是用于将芯片14，16与芯片封装与电端点相连接的。各个焊盘49都对应于芯片中的特定电路，例如，电源输入，接地，存储器地址，等等。为了能实现再区分工艺，首先，将一系列焊盘以对角线图形排列在芯片层23的表面。如果仅仅只需要少量的连接，最好是将焊盘制作在芯片的角上，以减少在芯片中间部分焊盘的数目，因为芯片的中间部分是存储器矩阵和其它敏感电路设置的地方。
接着，在各个芯片14，16的表面提供路径的线条24，将焊盘49与焊料焊点22电连接。两个芯片的公共电路部分，例如，接地，电源输入和时钟信号等等，都在芯片上从对应于电路的指定焊盘连接到各个芯片的指定焊料焊点上，各个芯片的焊料焊点都调整到一起便于互连。各个芯片的非公共电路部分，例如，芯片的使能端，就不与焊料焊点相连接。焊料焊点22也起着跳线器的作用，以便在两个芯片组合在一起时能将下层芯片14的电路与上层芯片16的电路相连接。在芯片的表面可以增加另一种路径的线条，便于将焊料焊点与一些指定的焊盘连接起来，而这些焊盘将用于芯片和芯片封装的连接。随后，在芯片14，16的表面15，17上提供一层钝化层21，并且通过钝化层21使得焊料焊点22能暴露，用于互连。一些引线的焊盘49也可以通过钝化层21来实现，并且构成暴露的焊盘29用于芯片与芯片封装之间的连接。
随后将两个芯片14，16调整到相互间成90°的角度，以便如箭头11所示，在上层芯片16倒装在下层芯片14的上面时，焊料焊点22能来接上用于互连。一般来说，往往最好是在将芯片放置于芯片封装的注模附件表面之前，将芯片14和16互连好。这是因为芯片之间回流焊料焊点所需的金属温度通常高于将芯片置于注模附件表面所需的温度。因此，如果先将下层芯片放置于注模附件的表面，那么当上层芯片放置在已经置于芯片封装的下层芯片上需更高温度时，附件就可能损坏。将两个芯片相连接的其它方法包括各向异性(“Z轴”)环氧树脂或其它导电焊料金属化的使用方法。
参照图3，置入芯片的下层芯片14被环氧树脂制成的引线框的注模附件表面保护着。因为两个矩形芯片调整到相互间成90°的角度，所以在下层芯片14上所暴露的焊盘29可以将引线连接附件连接到芯片封装10上。引线连接引线26用于将暴露的焊盘29与引线框的内部引线19相连接。内部引线19向外延伸形成外部引线20，用于和外部电路相连接，外部电路向芯片封装10提供电源与其它输入和输出信号。
参照图4，引线框18的注模附件表面12支撑着下层芯片14，它通过引线连接器26与引线框18和引线20相连接。上层IC芯片16通过焊料焊点22与下层芯片14相连接。由于芯片是旋转成相互间为90°的角度，所以下层芯片的两端部分是暴露用于引线连接26连接的。随后采用各向异性的环氧树脂材料28来覆盖，包括两个芯片14，16和注模附件表面12的上面的，IC封装10的上面，使得引线框18的引线20仍保持至少部分暴露。在图4中，密封材料28被切开了，所以能够看到IC封装的内部，但是在芯片的封装生产中，密封材料28是完全覆盖着芯片14，16。密封材料28最好是环氧树脂的外层或塑料成型的外层。
实施例2
图5示出了本发明的另一个实施例。第二实施例的IC芯片封装30显示了上层芯片36与下层芯片34的角度调整到小于90°的角度。这种结构对正方形的IC芯片非常有用，但也可用于矩形的芯片。通过将上层芯片36调整到与下层芯片34偏离一个角度，使得下层芯片34的区域38能暴露，以便将芯片34和引线40相连接。
本发明也能够采用两个不同尺寸的芯片来实现。在类似于图5所示的另一个实施例中，上层芯片36大于下层芯片。因为上层IC芯片36相对于下层芯片34旋转了一个角度，所以即使上层是较大的IC芯片36，下层芯片34仍有暴露的区域38以允许连接引线的连接。这对能控制较小IC芯片的设计但需要从其它途径购买较大IC芯片的制造商是十分有益的。
虽然上述已经讨论了本发明双注模IC封装，它是基于PLCC(可塑性无引线的芯片载体)型的封装，但是，本发明的双注模IC芯片封装也能够采用在本技术领域中已有的其它类型封装设计，例如，采用封装底部的焊料焊点而不是引线的来实现芯片封装和印刷电路板连接的球状栅极矩阵。在采用球状栅极矩阵的封装和其它类型的封装设计的情况下，芯片封装的结构设计方法可与上述所讨论的方法相同，除非芯片封装和外部电路之间的电连接采用特殊的方法。本发明的双注模IC封装也可以是采用上述相同结构技术的薄型封装型，例如，平面型封装或小外形IC(SOIC)。

Claims (15)

1.一种双注模集成电路封装，其特征在于，包括
具有多个用于连接封装和外部电路的外部电接触点的平面注模附件表面，
具有第一表面和第二表面的第一IC芯片，在第一表面上具有多个焊盘，第二表面安装在注模附件表面上，
具有第一表面和第二表面的第二IC芯片，通过第二表面与所述第一芯片的第一表面进行机械和电的连接，其中第二IC芯片以一个指定的角度与第一IC芯片覆盖部分相倾斜，使得第一IC芯片的第一表面的焊盘保持不被覆盖，并电连接到注模附件表面的外部电接触点，和
密封所述第一和第二IC芯片以及覆盖所述注模附件表面部分的密封材料，使得多个电接触点保持至少部分不被覆盖。
2.如权利要求1所述的集成电路封装，其特征在于，
所述第一和第二IC芯片具有相同的晶片制造结构。
3.如权利要求1所述的集成电路封装，其特征在于，
所述第一和第二IC芯片具有矩形形状。
4.如权利要求3所述的集成电路封装，其特征在于，
所述调整的指定角度为90°。
5.如权利要求1所述的集成电路封装，其特征在于，
所述调整的指定角度小于90°。
6.如权利要求1所述的集成电路封装，其特征在于，
所述第二IC芯片的第二表面和所述第一IC芯片的第一表面包括一系列焊料焊点，以便能进行所述第二IC芯片和所述第一IC芯片之间的电和机械的连接。
7.如权利要求1所述的集成电路封装，其特征在于，
所述注模附件表面是引线框的一部分，它具有多个分布在注模附件表面四周的引线。
8.如权利要求7所述的集成电路封装，其特征在于，
利用所述引线与所述多个在第一IC芯片第一表面上的焊盘之间的丝焊连接，将多根引线电连接到所述第一和第二IC芯片。
9.如权利要求1所述的集成电路封装，其特征在于，
利用环氧树脂将所述第一IC芯片安装在所述注模附件的表面上。
10.如权利要求1所述的集成电路封装，其特征在于，
所述第二IC芯片大于所述第一IC芯片，并安装在所述第一IC芯片的上面。
11.如权利要求1所述的集成电路封装，其特征在于，
所述注模附件表面是球状栅极矩阵型结构的一部分，并包括一系列在芯片封装底部的焊料焊点。
12.如权利要求6所述的集成电路封装，其特征在于，
所述一系列焊料焊点设置成对角线图形。
13.如权利要求6所述的集成电路封装，其特征在于，
所述一系列焊料焊点设置成“×形状”图形。
14.一种形成双注模集成电路封装的方法，其特征在于，包括
在第一IC芯片的第一表面和第二IC芯片的第一表面上排列多个焊料焊点，所述第一和第二IC芯片具有在其表面上排列着的多个连接细条，
在第一和第二IC芯片的第一表面上排列一系列连接细条，所述连接细条用于焊料焊点与焊盘的互连，
在第一和第二的各个芯片的第一表面上加上钝化层，焊料焊点和焊盘通过钝化层保持暴露，
将所述第二芯片调整到与所述第一芯片相倾斜的指定角度上，
通过各个芯片的焊料焊点的焊料回流结合，将所述第二芯片连接到所述第一芯片，
第一芯片置于平面注模附件表面上，并采用多个电接触点进行机械和电连接，
用密封材料覆盖所述第一和第二芯片以及注模附件表面的内部。
15.如权利要求14所述的形成双注模集成电路封装的方法，其特征在于，包括
利用各向异性的环氧树脂，进行所述第二芯片与所述第一芯片连接的步骤。
CN00816866A 1999-12-09 2000-10-23 双注模集成电路封装 Pending CN1408125A (zh)

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CN104779215B (zh) * 2014-01-14 2019-07-05 三星电子株式会社 堆叠式半导体封装件

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US6376914B2 (en) 2002-04-23
WO2001043193A3 (en) 2002-03-28
TW472327B (en) 2002-01-11
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NO20022736D0 (no) 2002-06-07
WO2001043193B1 (en) 2002-05-30
NO20022736L (no) 2002-06-07
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US20010003375A1 (en) 2001-06-14
JP2003516637A (ja) 2003-05-13

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