CN1406000A - Channel speed regulator light-burst-bag exchange network core node - Google Patents
Channel speed regulator light-burst-bag exchange network core node Download PDFInfo
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Abstract
The despartcher comprises hte modules of the input control, the packet storage, the channel manage, the swapping control and the output control. The swrapping control module comprises the sub functional modules of the processor, the buffer, the decoder, the queue, the registers, the comparator and the gate, The input control module sends the control packet to the packet storage module, meanwhile the control information picked as well as the position pointer of packet are submitted to the channel manage module. The packet storage module stores the packet and returns the position pointer pointed to the packet. The channels are despatched by the channel manage module. The swrapping control generates the control signal in order to control the operation of the optical switch matrix. The output control module updates the control packets.
Description
Technical field:
The present invention relates to the channel scheduler of core node in a kind of smooth burst packets switching network, can utilize simple horizontal dispatching algorithm that optical switching matrix is configured operation,, belong to fiber optic communication field to carry out the interconnection of burst packets.
Background technology:
Light burst packets exchange (Optical Burst Switching--OBS) is a kind of new light switching technology that occurs in recent years.It fully combines ripe already electronic technology and advanced optical tech.By sending control information in advance, and at each intermediate node place, after control information carried out light/electric conversion, processing, reserved bandwidth resource, network edge node transmits data again, data can remain in the light territory, and remove the trouble of handling packets headers in the packet switching one by one from, also avoid simultaneously or reduced the demand to the light buffer memory at network core node place.
At present, the exchange of light burst packets still is in the laboratory research stage, also has certain distance from real practicability and then formation OBS optical-fiber network.In order to promote the practicability of OBS, how to realize on hardware that the exchange of light burst packets is a problem that urgency is to be solved.In the OBS core node, control unit is the parts of a key, and the dateout channel scheduler is the core component of control unit.Washington, DC university is in the work of doing initial property aspect the realization of channel scheduler, and they have proposed a kind of implementation that is used for the channel scheduler of its research project " too bit burst packet technology ".This project alternative is based on the atm switching matrix of electricity, scheduler safeguards that by an input control module, two master controllers, two register, a channel manager, an exchange control unit, a cell memory and an o controller form the general structure more complicated.In addition, exchange control unit module in this scheduler schemes adopts a plurality of random access memory storage control signals, and the mode that adopts two a plurality of registers of pointer poll, structure is more complicated also, and do not consider the corresponding time of each optical device in the optical switching matrix, so can not be applicable to light burst packets switching network fully.
Summary of the invention:
The objective of the invention is to deficiency, a kind of channel scheduler of new light burst packets switching network core node is provided, make it to be applicable to OBS server node, thereby promote the practicability of OBS at the previous designs scheme.
For realizing such purpose, channel scheduler structure of the present invention comprises input control, packet memory, channel management, exchange control and output control module.The function and the annexation of each module are as follows:
The output of input control module links to each other with the packet memory module with the channel management module respectively.Be used for receiving control grouping, the control grouping is sent to the packet memory module, from the control grouping, extract control information and submit the channel management module to simultaneously together with pointer and request signal that the packet memory module is returned from ip router.The control information here comprises: input connection identifier, input wavelength channel logo, burst packets length and offset time.
The input of packet memory module links to each other with input control module, and output links to each other with output control module with input control module.In the process that control information is handled in scheduler, the grouping of packet memory module stores control corresponding, control information are then taken with pointing to control and are grouped in the pointer of memory location in the packet memory module by other parts in the scheduler.The packet memory resume module comes from the request signal storage of input control module and comes from the request signal that reads of output control module, and returns the pointer that points to the grouping position.
The input of channel management module links to each other with input control module, exports to switching control module.It is responsible for receiving the control information that comes from input control module, and calculates the burst packets due in and fully by constantly, and coming according to the state of this due in and channel management module institute management channel then is this burst packets distribution delivery channel.In order to finish above-mentioned task, the channel management module need be followed the tracks of the state of each channel, and adopts certain dispatching algorithm such as horizontal dispatching algorithm with allocated channel.
The input of switching control module links to each other with the channel management module, and output links to each other with the optical switching matrix control circuit with output control module.Switching control module is the foundation of path in the switching matrix and discharges the preservation associative operation, and generates control signal in time slot scheduling.Its major function is to receive swap operation and in the correct time they are sent to switching matrix from the channel management module.Switching control module among the present invention generates control signal by processor and decoder, keep in control signal by formation, by comparator the operation moment and current time is compared to determine when to switching matrix and send control signal again.
The input of output control module links to each other with switching control module and packet memory module, and output links to each other with packet memory module and output packet handler.After receiving the switching control module signal, output control module generates the request of reading to read the control grouping according to the storage pointer of control grouping.Subsequently, the control grouping of reading is sent to the output PHM packet handling module.Output control module also receives the delivery channel sign of switching control module and abandons bit, is set up if abandon bit, and then output control module notice packet memory module abandons this control grouping.Otherwise output control module replaces the former data channel in the control grouping to identify with the dateout channel logo.If switching control module is request not, output control module generates an idle packet.
The present invention compares following characteristics with scheme described in the background technology: simplified the structure of scheduler, removed two registers and two master controllers, with their function and channel scheduler merging; Packeting memory return pointer in the scheduler is to the input control interface, and this pointer passes through other parts of scheduler in company with the routing iinformation of control grouping then; Switching control module in the scheduler is proposed a kind of brand-new implementation.Like this, it is simply clear that scheduler architecture becomes, and is easy to realize, but also considered the response time of optical device in the optical switching matrix, is applicable to the exchange of light burst packets.
Description of drawings:
Figure 1 shows that the structured flowchart of this channel scheduler.
Figure 2 shows that the structural representation of the switching control module in this scheduler.
Embodiment:
In the control unit of OBS network core node, optical-electrical converter is converted into the signal of telecommunication with input optical signal, output to the output packet handler, the control grouping is handled, and then exchange to buffer through electric switching matrix, channel scheduler is received in the output of buffer, after after the output control packet transaction, be converted into light signal and send.
As shown in Figure 1, this channel scheduler is made of input control module, channel manager module, switching control module, packet memory module and output control module.The channel management module is given in the output control information of input control module, and this control is divided into groups to deliver in the packet memory module to store.The return pointer of packet memory module is given input control module, sends the control grouping when needed to output control module.The information processing that the channel management module is come input control module, the result exports to switching control module with channel dispatch.Switching control module then generates control signal and gives optical switching matrix control circuit and output control module.Output control module reads the control grouping to the packet memory module, and upgrades it, outputs to the output packet handler then.
As shown in Figure 2, switching control module is made up of the several sub-function module of processor, buffer, decoder, formation, register, comparator and gate.Its workflow is as follows: the operation information that processor receive channel administration module comes, these information comprise input connection identifier, input channel sign, delivery channel sign, burst packets due in and pass through constantly fully.Processor calculates the time of each operation in view of the above, then all information is stored up in buffer temporarily.In each grouping time slot,, from buffer, take out an operation information and deposit corresponding formation in according to the delivery channel numbering by decoder control.In each clock cycle, " pass " in each register be t constantly
CloseWith " opening " moment t
OpenSimultaneously with current time t
NowIn comparator, compare.Under the situation of having considered time loopback indication, work as t
Close-t
NowOr t
Open-t
NowDuring less than a particular value (this particular value depends on the response time of optical device), input connection identifier, input channel sign, delivery channel sign and expression are exchanged the control circuit that the control useful signal is delivered to switching matrix, to carry out this operation.From corresponding queues, read clauses and subclauses then again in register.In this process, relatively the walking abreast of operating time in current time and each register promptly can be set up a plurality of interconnections path simultaneously.In addition, device receives but does not have idle channel if control grouping is scheduled, then the channel management module generates one and abandons bit and send to switching control module, and switching control module must and point to the pointer that this control divides into groups with it and pass to output control module.
Claims (2)
1, a kind of channel scheduler of smooth burst packets switching network core node, it is characterized in that comprising input control, packet memory, channel management, exchange control and output control module, the output of input control module links to each other with the packet memory module with the channel management module respectively, the input of packet memory module links to each other with input control module, output links to each other with output control module with input control module, the input of channel management module links to each other with input control module, export to switching control module, the input of switching control module links to each other with the channel management module, output links to each other with the optical switching matrix control circuit with output control module, the input of output control module links to each other with switching control module and packet memory module, and output links to each other with packet memory module and output packet handler.
2,, it is characterized in that switching control module is made up of processor, buffer, decoder, formation, register, comparator and gate sub-function module as the channel scheduler of the said smooth burst packets switching network core node of claim 1.
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1316799C (en) * | 2003-12-03 | 2007-05-16 | 电子科技大学 | Method for supporting real-time service in optical burst exchange |
| US7266295B2 (en) | 2003-04-17 | 2007-09-04 | Intel Corporation | Modular reconfigurable multi-server system and method for high-speed networking within photonic burst-switched network |
| US7272310B2 (en) | 2003-06-24 | 2007-09-18 | Intel Corporation | Generic multi-protocol label switching (GMPLS)-based label space architecture for optical switched networks |
| US7310480B2 (en) | 2003-06-18 | 2007-12-18 | Intel Corporation | Adaptive framework for closed-loop protocols over photonic burst switched networks |
| US7526202B2 (en) | 2003-05-19 | 2009-04-28 | Intel Corporation | Architecture and method for framing optical control and data bursts within optical transport unit structures in photonic burst-switched networks |
| CN101001113B (en) * | 2006-12-29 | 2010-04-14 | 华为技术有限公司 | Burst packet channel reserving method and device |
| CN101035390B (en) * | 2007-02-13 | 2010-05-19 | 上海交通大学 | Parallel channel scheduler in the optical burst switching |
| US7734176B2 (en) | 2003-12-22 | 2010-06-08 | Intel Corporation | Hybrid optical burst switching with fixed time slot architecture |
| US7848649B2 (en) | 2003-02-28 | 2010-12-07 | Intel Corporation | Method and system to frame and format optical control and data bursts in WDM-based photonic burst switched networks |
| CN102984597A (en) * | 2012-11-21 | 2013-03-20 | 北京邮电大学 | Storing and optical switching hybrid optical network data node device and control method |
| US8660427B2 (en) | 2002-09-13 | 2014-02-25 | Intel Corporation | Method and apparatus of the architecture and operation of control processing unit in wavelenght-division-multiplexed photonic burst-switched networks |
-
2002
- 2002-11-07 CN CN02145104A patent/CN1406000A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8660427B2 (en) | 2002-09-13 | 2014-02-25 | Intel Corporation | Method and apparatus of the architecture and operation of control processing unit in wavelenght-division-multiplexed photonic burst-switched networks |
| US7848649B2 (en) | 2003-02-28 | 2010-12-07 | Intel Corporation | Method and system to frame and format optical control and data bursts in WDM-based photonic burst switched networks |
| US7266295B2 (en) | 2003-04-17 | 2007-09-04 | Intel Corporation | Modular reconfigurable multi-server system and method for high-speed networking within photonic burst-switched network |
| US7526202B2 (en) | 2003-05-19 | 2009-04-28 | Intel Corporation | Architecture and method for framing optical control and data bursts within optical transport unit structures in photonic burst-switched networks |
| US7310480B2 (en) | 2003-06-18 | 2007-12-18 | Intel Corporation | Adaptive framework for closed-loop protocols over photonic burst switched networks |
| US7272310B2 (en) | 2003-06-24 | 2007-09-18 | Intel Corporation | Generic multi-protocol label switching (GMPLS)-based label space architecture for optical switched networks |
| CN1574717B (en) * | 2003-06-24 | 2011-01-12 | 英特尔公司 | Gmpls based label space architecture |
| CN1316799C (en) * | 2003-12-03 | 2007-05-16 | 电子科技大学 | Method for supporting real-time service in optical burst exchange |
| US7734176B2 (en) | 2003-12-22 | 2010-06-08 | Intel Corporation | Hybrid optical burst switching with fixed time slot architecture |
| CN101001113B (en) * | 2006-12-29 | 2010-04-14 | 华为技术有限公司 | Burst packet channel reserving method and device |
| CN101035390B (en) * | 2007-02-13 | 2010-05-19 | 上海交通大学 | Parallel channel scheduler in the optical burst switching |
| CN102984597A (en) * | 2012-11-21 | 2013-03-20 | 北京邮电大学 | Storing and optical switching hybrid optical network data node device and control method |
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