CN1400648A - Method for forming shalow ridge isolation structure - Google Patents
Method for forming shalow ridge isolation structure Download PDFInfo
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- CN1400648A CN1400648A CN 01123812 CN01123812A CN1400648A CN 1400648 A CN1400648 A CN 1400648A CN 01123812 CN01123812 CN 01123812 CN 01123812 A CN01123812 A CN 01123812A CN 1400648 A CN1400648 A CN 1400648A
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- silicon nitride
- nitride layer
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Abstract
Method of forming shallow trench isolation (STI) structure contains utilizing wet etch to substitute present chemical mechanical polishing (CMP) and utilizing good option of wet etch to reduce or control thickness of oxidation layer of silicon nitride (Si3 N4) and shallow trench isolation and avoid micro-scratch resulted in CMP.
Description
Technical field
The present invention relates to a kind of shallow-trench isolation (Shallow Trench Isolation; STI) the formation method of structure particularly relates to a kind of method of utilizing Wet-type etching (Wet Etch) to form shallow groove isolation structure.
Background technology
At very lagre scale integrated circuit (VLSIC) (Very Large Scale Integration; VLSI) in the manufacture process, an integrated circuit is normally by numerous metal-oxide semiconductor (Metal-OxideSemiconductor; MOS) transistor is formed.MOS transistor has N channel MOS (N-channel MOS; NMOS) transistor, P channel MOS (P-channel MOS; PMOS) transistor and complementary MOS (Complementary MOS; CMOS) transistor is three types, and wherein the CMOS transistor is made up of a nmos pass transistor and a PMOS transistor.Along with the increase day by day of semiconductor subassembly integrated level (Integration), the less CMOS transistor of energy consumption replaces nmos pass transistor and PMOS transistor gradually, becomes the MOS transistor assembly of normal use.
In the transistorized use of CMOS, temporary transient or permanent disappearance for the function that prevents the CMOS transistor circuit, promptly produce so-called breech lock (Latch Up) phenomenon, nmos pass transistor in the CMOS transistor component and PMOS transistor must be isolated (Isolation).In present semiconductor fabrication process, trench isolations is the transistorized isolation technology of a kind of CMOS of extensive use.
Please refer to Fig. 1 to Fig. 5, it is to have the generalized section that forms shallow groove isolation structure on base material now.At first, on base material 100, form a bed thickness approximate number hundred by silicon dioxide (Silicon Dioxide with boiler tube technology; SiO
2) thermal oxide layer (Thermal Oxide) formed 102 is the assembly oxide layer.Wherein, this thermal oxide layer 102 is called pad oxide (Pad Oxide) again, because silicon nitride (Silicon Nitride; Si
3N
4) not strong to the adhesive force of silicon, therefore before deposited silicon nitride, can on silicon substrate, form layer of silicon dioxide earlier and help the silicon nitride deposition.On thermal oxide layer 102, deposit subsequently, for example with low-pressure chemical vapor deposition (Low Pressure Chemical VaporDeposition; LPCVD) method forms silicon nitride layer 104, as shown in Figure 1.
Then, for example on base material 100, define active area and shallow trench 106, form structure as shown in Figure 2 with photoetching (Photolithography) and dry-etching (Dry Etch) mode.Please refer to Fig. 3, finish the definition of shallow trench 106 after, deposit layer of oxide layer 108 in the chemical vapour deposition (CVD) mode again and cover shallow trenchs 106 and silicon nitride layers 104.
Please refer to Fig. 4, subsequently with chemical mechanical milling method (Chemical MechanicalPolishing; CMP) grind oxide layer 108 after exposing beneath silicon nitride layer 104 approximately, promptly stop grinding steps.In the mode of wet-clean platform (Clean Bench), utilize hot phosphoric acid (Phosphoric Acid at last; H
3PO
4) high selectivity (Selectivity), silicon nitride layer 104 is divested, again with hydrofluoric acid (Hydrofluoric Acid; HF) remove thermal oxide layer 102 when etching solution carries out Wet-type etching, and form complete shallow groove isolation structure 110, structure as shown in Figure 5.
In the manufacture process of above-mentioned shallow groove isolation structure, the CMP technology of being used is the expense cost height not only, and must utilize chemical solution (Chemical Solution) slurry (Slurry) and the layer the surface between reactant (Reaction), and the particle of slurry can make the surface of shallow groove isolation structure form many microscratch (Micro-scratch), causes the injury of active area.In addition, the thicker stress that silicon nitride layer produced (Stress) of thickness has great injury for thin thermal oxide layer and the oxide layer of erasable (Flash) internal memory soon, yet existing CMP technology but can't reduce or control thickness of oxide layer in silicon nitride layer and the shallow groove isolation structure effectively.
Therefore, in the formation method of above-mentioned existing shallow groove isolation structure, the CMP technology of being used is the expense cost height not only, and employed slurry can form many microscratch and causes the injury of active area on the surface of shallow groove isolation structure.On the other hand, CMP technology also can't reduce or control silicon nitride layer and thickness of oxide layer effectively, and then suppresses the stress problem by silicon nitride layer caused.
Summary of the invention
In order to overcome the deficiencies in the prior art, the purpose of this invention is to provide a kind of formation method of shallow ditch groove structure, utilization the present invention can reduce manufacturing cost, avoids grinding the microscratch that is produced, and then can improve product percent of pass.
Another object of the present invention provides a kind of formation method of shallow ditch groove structure, it can reduce or control the thickness of oxide layer in silicon nitride layer and the shallow groove isolation structure, avoids the stress problem that silicon nitride layer causes and causes the injury of the oxide layer of thermal oxide layer and flash memory.
To achieve the above object, the invention provides a kind of formation method of shallow ditch groove structure, at least comprise: form an oxide layer and cover a base material, wherein have one first silicon nitride layer on this base material, and a shallow trench is arranged in this base material and this first silicon nitride layer; Carry out this oxide layer of wet etch step etching until exposing this first silicon nitride layer approximately; Form one second silicon nitride layer and cover this oxide layer and this first silicon nitride layer; Form a photoresistance and cover this second silicon nitride layer; Define this photoresistance, and etching partly this second silicon nitride layer and this oxide layer until exposing this first silicon nitride layer approximately; And remove this photoresistance, this second silicon nitride layer and this first silicon nitride layer.
The present invention also provides a kind of formation method of shallow groove isolation structure, comprises at least: a base material is provided, and has one first silicon nitride layer on this base material; In this base material, define a shallow trench in a dry-etching mode; Form an oxide layer with a chemical vapour deposition technique and cover this first silicon nitride layer and this shallow trench; Carry out this oxide layer of wet etch step etching until exposing this first silicon nitride layer approximately; Form one second silicon nitride layer and cover this oxide layer and this first silicon nitride layer; On this second silicon nitride layer, form a defined photoresistance; This second silicon nitride layer of etching and this oxide layer are until exposing this first silicon nitride layer approximately; And remove this second silicon nitride layer, this oxide layer and this first silicon nitride layer in a wet-clean platform mode.
The present invention also provides a kind of formation method of shallow groove isolation structure, comprises at least: a base material is provided, and has one first silicon nitride layer on this base material; In this base material, define a shallow trench in a dry-etching mode; Form an oxide layer with a chemical vapour deposition technique and cover this first silicon nitride layer and this shallow trench; Carry out this oxide layer of wet etch step etching until exposing this first silicon nitride layer approximately; Form one second silicon nitride layer and cover this oxide layer and this first silicon nitride layer; On this second silicon nitride layer, form a defined photoresistance; This second silicon nitride layer of etching and this oxide layer are until exposing this first silicon nitride layer approximately; And remove this second silicon nitride layer, this oxide layer and this first silicon nitride layer in a wet-clean platform mode.
In other words, method of the present invention is when forming shallow groove isolation structure in ic manufacturing process, utilizes oxide layer on first silicon nitride layer of Wet-type etching mode etching active area until exposing first silicon nitride layer approximately.Then, deposit one deck second silicon nitride layer again, on this second silicon nitride layer, form a photoresistance subsequently, cover whole shallow trench zone, with photolithographicallpatterned and carry out dry-etching and remove second silicon nitride layer partly and oxide layer, utilize wet type to peel off method (Wet Strip) or dry type again and peel off method (Dry Strip) and divest photoresistance until exposing the first beneath silicon nitride layer approximately.Utilize hot phosphoric acid to divest all silicon nitride layers in the mode of wet-cleaned subsequently, work as etching solution with hydrofluoric acid again and carry out Wet-type etching, and form complete shallow groove isolation structure with the removal thermal oxide layer.Therefore, utilization the present invention need can not obtain shallow groove isolation structure through CMP technology, not only reduces manufacturing cost and product percent of pass and also obtains to improve.Moreover the present invention is may command silicon nitride layer and thickness of oxide layer and avoid the stress problem of thick silicon nitride layer also.
Advantage of the present invention is: method of the present invention is not owing to need use CMP technology, therefore use the present invention can reduce manufacturing cost, and can avoid the microscratch that forms on the shallow groove isolation structure surface, particle place of slurry of CMP technology, and cause product percent of pass to reduce.On the other hand, the employed wet etching of method of the present invention has high selectivity to silicon nitride and oxide layer, can reduce or control the thickness of oxide layer in silicon nitride layer and the shallow groove isolation structure, and then the inhibition stress that silicon nitride layer caused is to the injury that oxide layer caused of thermal oxide layer and flash memory.
Description of drawings
The present invention is described in detail below in conjunction with drawings and Examples:
Fig. 1 is existing base material profile with thermal oxide layer and silicon nitride layer;
Fig. 2 is the existing section of structure that defines behind the shallow trench;
Fig. 3 is for having now with the section of structure after the chemical vapour deposition (CVD) mode deposited oxide layer;
Fig. 4 is existing section of structure behind cmp;
Fig. 5 is the existing section of structure that forms shallow groove isolation structure;
Fig. 6 has the base material profile of thermal oxide layer and silicon nitride layer for a preferred embodiment of the present invention;
Fig. 7 defines section of structure behind the shallow trench for a preferred embodiment of the present invention;
Fig. 8 is the section of structure of a preferred embodiment of the present invention after with chemical vapour deposition (CVD) mode deposited oxide layer;
Fig. 9 is the section of structure of a preferred embodiment of the present invention behind Wet-type etching;
Figure 10 is a preferred embodiment of the present invention section of structure after the deposited silicon nitride layer once more;
Figure 11 covers section of structure behind the shallow trench isolation region for a preferred embodiment of the present invention with photoresistance;
Figure 12 be a preferred embodiment of the present invention behind dry-etching section of structure;
Figure 13 is the section of structure of a preferred embodiment of the present invention photoresistance after divesting;
Figure 14 forms the section of structure of shallow groove isolation structure for a preferred embodiment of the present invention.
Symbol description among the figure:
100 base materials, 102 thermal oxide layers
104 silicon nitride layers, 106 shallow trenchs
108 oxide layers, 110 shallow groove isolation structures
200 base materials, 202 thermal oxide layers
204 silicon nitride layers, 206 shallow trenchs
208 oxide layers, 210 silicon nitride layers
212 photoresistances, 214 shallow groove isolation structures
Embodiment
Past all must be used the silicon nitride layer (Si of CMP technology with active area when forming shallow groove isolation structure in ic manufacturing process
3N
4) on oxide layer worn.Because the cost height of CMP technology, and its employed slurry instability make technology be difficult for reaching an agreement property, therefore,, the invention provides a kind of method of using Wet-type etching to form shallow groove isolation structure for fear of using CMP technology, as described below.
Please refer to Fig. 6 to Figure 14, it is a preferred embodiment of the present invention forms shallow groove isolation structure on base material a generalized section.At first, utilize boiler tube technology on base material 200, to form a bed thickness approximate number hundred by silicon dioxide (SiO
2) thermal oxide layer formed 202 is the assembly oxide layer.Wherein, thermal oxide layer 202 is called pad oxide again, because silicon nitride is not strong to the adhesive force of silicon, helps the silicon nitride deposition so can form layer of silicon dioxide earlier on silicon substrate before deposited silicon nitride.Then, for example with low-pressure chemical vapor deposition (LPCVD) deposited silicon nitride layer 204 on thermal oxide layer 202, form structure as shown in Figure 6.
Then, on base material 200, define active area and shallow trench 206 by photoetching process and dry-etching mode, as shown in Figure 7.Please refer to Fig. 8, finish the definition of shallow trench 206 after, deposit layer of oxide layer 208 in the chemical vapour deposition (CVD) mode again and cover shallow trenchs 206 and silicon nitride layers 204.
Please refer to Fig. 9, utilize the Wet-type etching mode with oxide layer 208 etchings until the silicon nitride layer 204 that exposes approximately on shallow trench 206 edges, because Wet-type etching has high selectivity to silicon nitride and oxide layer, so its etching end point of may command.The embodiment of the invention promptly is after finishing wet etch step, for example use chemical vapour deposition technique deposition one deck silicon nitride layer 210 to cover the silicon nitride layer 204 that is exposed on whole oxide layer 208, shallow trench 206 and shallow trench 206 edges again, form structure as shown in figure 10.Yet more noticeable is that the present invention also can not form silicon nitride layer 210 when Wet-type etching.The purpose that forms silicon nitride layer 210 only is in order more preferably to control the thickness of shallow groove isolation structure 214.
Of the present invention one is characterised in that the use wet etch process mode thickness of controlled oxidation layer 208 effectively, nor needs to form the thicker silicon nitride layer of thickness as existing CMP technology.
Please refer to Figure 11, on silicon nitride layer 210, form the zone that photoresistance 212 covers whole shallow trench 206, then utilize mask on photoresistance 212, to carry out lithography step.And then for example carry out etching and remove silicon nitride layer partly 210 and oxide layer 208, until till the silicon nitride layer 204 under exposing approximately, as shown in figure 12 in the dry-etching mode.
Please refer to Figure 13, finish dry etch process after, utilize wet type to peel off method or dry type again and peel off method photoresistance 212 is removed, and expose silicon nitride layer 210.Subsequently, with the hot phosphoric acid in the wet-cleaned, silicon nitride layer 204 and silicon nitride layer 210 are divested.In addition, the oxide layer 208 between silicon nitride layer 204 and the silicon nitride layer 210 is also peeled off thereupon.Remove thermal oxide layer 202 with hydrofluoric acid when etching solution carries out Wet-type etching again, and form complete shallow groove isolation structure 214, structure as shown in figure 14.
As understood by those skilled in the art, the above is preferred embodiment of the present invention only, is not in order to limit claim of the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, all should be included in protection scope of the present invention.
Claims (18)
1. the formation method of a shallow groove isolation structure comprises at least:
Form an oxide layer and cover a base material, wherein have one first silicon nitride layer on this base material, and a shallow trench is arranged in this base material and this first silicon nitride layer;
Carry out this oxide layer of wet etch step etching until exposing this first silicon nitride layer approximately;
Form one second silicon nitride layer and cover this oxide layer and this first silicon nitride layer;
Form a photoresistance and cover this second silicon nitride layer;
Define this photoresistance, and etching partly this second silicon nitride layer and this oxide layer until exposing this first silicon nitride layer approximately; And
Remove this photoresistance, this second silicon nitride layer and this first silicon nitride layer.
2. method according to claim 1 is characterized in that: in the formation step of this oxide layer, this oxide layer covers this first silicon nitride layer and this shallow trench, and fills up this shallow trench.
3. method according to claim 1 is characterized in that: the step that forms this oxide layer is to utilize chemical vapour deposition technique.
4. method according to claim 1 is characterized in that: the step that defines this shallow trench is to adopt the dry-etching method.
5. method according to claim 1 is characterized in that: the step of removing this second silicon nitride layer and this oxide layer is to adopt the dry-etching method.
6. method according to claim 1 is characterized in that: the step that removes this second silicon nitride layer and this first silicon nitride layer is to adopt a wet-clean platform mode.
7. method according to claim 6 is characterized in that: this wet-clean platform is to use hot phosphoric acid to be used as a cleaning fluid.
8. method according to claim 1 is characterized in that: when removing this second silicon nitride layer and this first silicon nitride layer, also remove this oxide layer between this second silicon nitride layer and this first silicon nitride layer simultaneously.
9. the formation method of a shallow groove isolation structure comprises at least:
Form an oxide layer and cover a base material, wherein have a silicon nitride layer on this base material, and a shallow trench is arranged in this base material and this silicon nitride layer;
Carry out this oxide layer of wet etch step etching until exposing this silicon nitride layer approximately;
Form a photoresistance and cover this oxide layer;
Define this photoresistance, and etching this oxide layer partly is until exposing this silicon nitride layer approximately; And
Remove this photoresistance and this silicon nitride layer.
10. method according to claim 9 is characterized in that: in the formation step of this oxide layer, this oxide layer is to cover this silicon nitride layer and this shallow trench, and fills up this shallow trench.
11. method according to claim 9 is characterized in that: the step that forms this oxide layer is to utilize chemical vapour deposition technique.
12. method according to claim 9 is characterized in that: the step that defines this shallow trench is to adopt the dry-etching method.
13. method according to claim 9 is characterized in that: the step of removing this oxide layer is to adopt the dry-etching method.
14. method according to claim 9 is characterized in that: removing this silicon nitride layer is to adopt a wet-clean platform mode.
15. method according to claim 14 is characterized in that: this wet-clean platform is to use hot phosphoric acid to be used as a cleaning fluid.
16. method according to claim 9 is characterized in that: when removing this silicon nitride layer, also remove this oxide layer on this silicon nitride layer simultaneously.
17. the formation method of a shallow groove isolation structure comprises at least:
One base material is provided, and has one first silicon nitride layer on this base material;
In this base material, define a shallow trench in a dry-etching mode;
Form an oxide layer with a chemical vapour deposition technique and cover this first silicon nitride layer and this shallow trench;
Carry out this oxide layer of wet etch step etching until exposing this first silicon nitride layer approximately;
Form one second silicon nitride layer and cover this oxide layer and this first silicon nitride layer;
On this second silicon nitride layer, form a defined photoresistance;
This second silicon nitride layer of etching and this oxide layer are until exposing this first silicon nitride layer approximately; And
Remove this second silicon nitride layer, this oxide layer and this first silicon nitride layer in a wet-clean platform mode.
18. method according to claim 17 is characterized in that: this wet-clean platform is to use hot phosphoric acid to be used as a cleaning fluid.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011238127A CN1178290C (en) | 2001-07-30 | 2001-07-30 | Method for forming shalow ridge isolation structure |
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| CNB011238127A CN1178290C (en) | 2001-07-30 | 2001-07-30 | Method for forming shalow ridge isolation structure |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1323433C (en) * | 2003-11-28 | 2007-06-27 | 海力士半导体有限公司 | Semiconductor device with trench isolation structure and method for fabricating the same |
| US7259078B2 (en) | 2004-09-03 | 2007-08-21 | Hynix Semiconductor Inc. | Method for forming isolation layer in semiconductor memory device |
| CN105448923A (en) * | 2014-08-07 | 2016-03-30 | 旺宏电子股份有限公司 | Semiconductor element and manufacturing method thereof |
-
2001
- 2001-07-30 CN CNB011238127A patent/CN1178290C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1323433C (en) * | 2003-11-28 | 2007-06-27 | 海力士半导体有限公司 | Semiconductor device with trench isolation structure and method for fabricating the same |
| US7528052B2 (en) | 2003-11-28 | 2009-05-05 | Hynix Semiconductor Inc. | Method for fabricating semiconductor device with trench isolation structure |
| US7902628B2 (en) | 2003-11-28 | 2011-03-08 | Hynix Semiconductor Inc. | Semiconductor device with trench isolation structure |
| US7259078B2 (en) | 2004-09-03 | 2007-08-21 | Hynix Semiconductor Inc. | Method for forming isolation layer in semiconductor memory device |
| CN1744296B (en) * | 2004-09-03 | 2012-03-28 | 海力士半导体有限公司 | Method for forming isolation layer in semiconductor memory device |
| CN105448923A (en) * | 2014-08-07 | 2016-03-30 | 旺宏电子股份有限公司 | Semiconductor element and manufacturing method thereof |
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| Publication number | Publication date |
|---|---|
| CN1178290C (en) | 2004-12-01 |
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Granted publication date: 20041201 Termination date: 20190730 |