CN1364311A - 用表面涂敷方法降低铜布线的电迁移和应力引起的迁移 - Google Patents

用表面涂敷方法降低铜布线的电迁移和应力引起的迁移 Download PDF

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CN1364311A
CN1364311A CN00810831A CN00810831A CN1364311A CN 1364311 A CN1364311 A CN 1364311A CN 00810831 A CN00810831 A CN 00810831A CN 00810831 A CN00810831 A CN 00810831A CN 1364311 A CN1364311 A CN 1364311A
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conductive film
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胡朝坤
罗伯特·罗森博格
朱迪思·M·鲁宾诺
卡洛斯·J·撒姆布赛蒂
安舍尼·K·斯坦伯尔
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Abstract

本发明的想法是在淀积层间介质之前,用1－20nm厚的金属层(63,74)涂敷芯片上互连(BEOL)布线中的被图形化的铜导线(60,70)的自由表面。这一涂层要足够薄,以便免除对抛光额外整平的需要,同时提供抗氧化、抗铜的表面或界面扩散的保护,本发明人已经证实铜的表面和界面扩散是电迁移和热应力空洞造成金属线条失效的首要原因。金属层(63,74)还提高了铜(60,70)与介质(66)之间的粘附强度,从而进一步提高了寿命和工艺成品率。自由表面是镶嵌工艺或干法腐蚀工艺中用以对铜布线进行图形化的CMP(化学机械抛光)的直接结果。提出了用选择性工艺将金属覆盖层(63,74)淀积到铜上以便尽量减少进一步处理。虽然能够使用金属或金属形成的化合物来进行化学汽相淀积(CVD),但我们已经使用诸如CoWP、CoSnP和Pd之类的无电金属涂敷方法来演示明显的可靠性好处。

Description

用表面涂敷方法降低铜布线的电迁移和应力引起的迁移
技术领域
本发明涉及到半导体芯片上的金属互连，更确切地说是涉及到一种表面涂敷或处理，用来防止电子流使导体表面原子向下运动即所谓电迁移现象和/或防止倾向于释放应力的应力梯度使导体表面原子移动即所谓应力引起的迁移。
背景技术
微电子电路越来越高的密度和速度，已经使金属化系统从Al(Cu)转向到了Cu，以便降低导体的电阻。同时，对更高的电流密度的要求已经暴露出Al(Cu)线由于电迁移而失效，限制了电路设计者能够提高性能的范围。铜的更高的熔点被期望能够改进导体的电流承载能力，延长电迁移寿命。但我们从所得到的测试结果已经发现，电迁移寿命主要依赖于诸如铜/介质界面处的原子输运之类的原子行为，而不依赖于铜晶格、晶粒边界或铜/衬里界面原子输运的本征特性。于是证明铜导体承受电流的特性并不明显地优越于Al(Cu)。
制造铜导体图形的基本工艺是采用镶嵌方法，其中，在介质层中制作沟槽，在沟槽中形成衬里，然后用铜填充沟槽，并对其进行化学机械抛光(CMP)，终止于与介质层共平面的洁净铜顶面。铜/金属衬里界面被形成在铜导体的其他3个表面上。电迁移寿命是线条厚度、宽度和截面积的函数。测得的数据表明，仅仅顶部表面对具有竹状和接近竹状的晶粒结构的铜导体的质量输运有贡献，而边界与表面的组合对更宽的线条的质量输运有贡献。同一个关系被发现而与铜的淀积方法无关，亦即，不管是用物理汽相淀积(PVD)、化学汽相淀积(CVD)、或电镀来进行淀积，都出现此问题。除了电迁移寿命失效之外，还发现铜导体图形对热循环应力下的原子空洞很敏感，发现空洞总是开始于原子迁移率最高的铜/介质界面处。由于铜迁移速率即漂移速度是迁移率(D/kT)与驱动力(F)的乘积，其中D是铜的扩散率，T是绝对温度，k是波耳兹曼常数。对于电迁移和应力引起的迁移力，驱动力F分别是Z*eE和(Ds/Dx)W，其中Z*是有效电荷数目，e是电子电荷，E是电场，(Ds/Dx)是应力梯度，而W是原子体积。目前不可避免的是，能够实现最高性能和可靠性的铜导体技术的成就要求改变或修正覆盖层的铜/介质界面以降低铜输运和原子空洞。
铜导体表面的修正可以在CMP之后进行。此工艺则应该对铜有选择性，并在铜导体表面上提供一个薄层，以便基本上保持与包含沟槽的介质或绝缘体共平面。此工艺必须导致铜导体与层上随后制作的介质之间更好的粘附性和铜导体中铜原子更好的抗氧化性以及降低了的铜导体原子输运，以便提供最高的可靠性。
发明内容
根据本发明，借助于在诸如CMP整平或干法腐蚀工艺之后在铜表面上提供一个1-20nm的金属薄层，改变了铜导体的暴露铜表面，以便在后续的芯片处理和/或芯片利用过程中降低对电迁移、氧化、腐蚀、应力空洞和剥层的敏感性，从而改善可靠性和成品率。本发明提出了无电金属淀积方法作为在铜导体上形成金属薄层的方法，用来提高电迁移寿命和抗应力引起的迁移。
此选择性淀积工艺包含下列步骤。
a.用Pd离子催化剂选择性地激活铜表面，如方程1所示。
                       (1)
这一步骤在铜线表面上留下多个Pd纳米粒子，用作下一步骤的催化剂。
b.用无电还原方法选择性地淀积金属或合金，如方程2所示。
    (2)
其中Men+是金属离子，例如Co2+。
例如，使用次磷酸盐作为还原剂，钴离子作为覆盖金属，则有方程3所示的化学反应。     (3)
在本发明中，我们使用了上述的次磷酸盐系统，并将金属钯、钴、钴钨、磷化钴钨、钴锡、磷化钴锡、磷化钴和钴的其它合金淀积到铜导体的表面上。还可以理解的是，能够使用其它的还原剂，例如能够淀积诸如Co-B或Ni-B之类的其它类型合金的二甲氨基硼烷。
上述步骤a和b的结果是，铜导体的暴露表面被由金属化合物或合金组成的厚度最好为1-10nm的薄膜涂敷，该薄膜通过化学键和/或金属键牢固地粘附于铜表面上或铜表面中的铜原子。
在用来制作集成电路芯片上的铜互连的镶嵌工艺中，下列重要发现对于本发明来说是至关重要的。
1.铜表面上的涂敷膜的厚度必须薄：由于镶嵌工艺的考虑，最大厚度为20nm，最好是1-10nm。以这种方式获得至少3个主要性质：a)铜线的电阻率不受影响或增加不大于20％，b)各个铜导体之间搭桥可能造成的漏电被消除，以及c)铜导体或铜线不需要进一步整平。为了提供后续形成在其上的介质层的平整的顶部表面而不必整平后续的介质层的顶部表面，要求对铜导体/介质表面进行整平或基本的整平。一个表面上的台阶特征通过下一层被转移到该表面，特别是用CVD方法制作的表面。
2.涂敷膜的优选组分可以是Co-Sn-P、Co-W-P、Co-P或Pd。
3.具有涂敷膜的晶片在300℃下被退火2小时，以便进一步改善与铜表面的化学键合或金属键合，并减慢铜导体/介质界面处铜原子沿铜表面的扩散以及铜原子沿晶粒边界的扩散。铜导体/介质界面位于铜导体与形成在铜导体上的介质层之间。镶嵌工艺中的铜导体位于具有用铜导体填充沟槽之前制作在沟槽中的金属衬里的介质层中的沟槽中。
4.金属的选择性CVD或其它的淀积工艺也可以被用来在具有化学键合和/或金属键合的铜导体的表面上淀积金属膜，以便获得铜导体的更高的抗电迁移性。
附图说明
当结合附图考虑本发明的下列详细描述时，本发明的这些和其它的特点、目的、和优点将变得明显，其中：
图1是本发明一个实施方案的剖面图。
图2A-2D是本发明第二实施方案的各个制造阶段的剖面图。
图3A-3E是第三实施方案的各个制造阶段的剖面图。
图4是三层电迁移测试结构的剖面图。
图5曲线示出了顶部表面上具有和不具有金属薄膜的介质层沟槽中的铜导体和衬里的欧姆电阻对时间的关系。
具体实施方式
现参照附图，图1是含有用单镶嵌工艺制作的铜线和通孔的集成电路芯片10上的铜后端线(BEOL)结构例子的剖面图。
在图1中，集成电路芯片10具有衬底11，可以是例如Si、SiGe、Ge、SOI和GaAs。衬底11中可以制作典型FET晶体管19的源区16和漏区17以及栅18。在源区16和漏区17的二侧是衬底11上凹陷的氧化物区21和22。氧化物层23被制作在氧化物区21和22以及FET晶体管19上。在层23中形成源接触窗口，并用金属25通常是钨填充。层23和金属25被化学机械抛光(CMP)整平。例如由氮化硅组成的覆盖层26被制作在层23的上表面上。介质层27被制作在层26上，并在其中形成沟槽。衬里28被形成在沟槽的底部和侧壁上，然后用铜填充以形成线条29。用CMP对层27和线条29进行整平。在层27和线条29的上表面上制作覆盖层31。在覆盖层31上形成介质层32。在层31和32中形成通孔窗口，随之以在窗口中形成金属衬里33和诸如铜的金属以形成通孔34。用CMP方法整平层32和通孔34。在层32和通孔34上制作覆盖层36。在覆盖层36上制作介质层37。在层37和覆盖层36中形成沟槽或窗口。在层37和覆盖层36的沟槽中形成衬里38。用金属铜填充沟槽以形成线条39。用CMP方法整平层37和线条39。在层37和线条39上制作覆盖层42。覆盖层26、31和36是由不同于层23、27、32和37的介质组成的，可以是二氧化硅、类金刚石碳(DLC)、氟化DLC、聚亚芳基醚、SiCOH等。在1998年6月29日提出的No.09/107567中，描述了SiCOH，此处被列为参考来显示低k(介电常数)介质的一个例子。注意，BEOL是用单镶嵌铜工艺制造的，亦即，各个铜层被单独地加工，且线条31和39的顶部与介质8形成界面。
图2A-2D示出了用来制造单镶嵌铜线条的工艺顺序，说明了用无电镀方法选择性淀积形成金属覆盖层。在此工艺顺序中，如图2A所示，淀积介质层55-57和58。如图2B所示，用光刻工艺将图形转移到介质层56和57中。然后淀积衬里金属59，随之以淀积厚度大于图形深度的铜导体60。如图2C所示，用CMP清除过量的铜导体60和衬里59，以形成平整的表面。如图2D所示，薄的无电金属涂层63被选择性地淀积到铜导体60上。图2A-2D所示的工艺可以对下一个铜导体互连层重复。
图3是双重镶嵌工艺的工艺顺序，其中的铜线条和通孔被同时淀积。从图3A所示的平整的介质层65-67开始，通孔71的图形通过图3B所示的介质层67被转移，线条或通孔图形然后如图3C所示被转移到层67中，其间通孔71的通孔腐蚀继续通过介质层66和67直到下面先前形成的铜线(未示出)。作为变通，线条70的图形窗口可以首先通过介质层67被转移，然后可以将通孔图形转移到层67中以提供图3C所示的窗口。然后淀积衬里金属69，通常用电镀方法将铜淀积到二个图形中，并用CMP进行整平，以提供图3D所示的线条70和通孔71的结构。然后如图3E所示，在线条70的顶部表面上形成无电金属涂层74。结构继续到下一层时，要求重复图3E所示的制作平整介质层66’和67’的步骤。无电涂层74现在将线条70的铜表面分隔于制作在其上的平整介质66’。层23、27、32和37所用的材料可以被用于图2A-2D中的层55和57以及图3A-3E中的层65和67。层26、31、36和42所用的材料可以被用于图2A-2D中的层56以及图3A-3E中的层66。
在图2和3所示的单镶嵌工艺和双重镶嵌工艺二者中，借助于用金属层59、63、69和74整个包围铜导体，提供了可靠性方面的至关重要的改善。目前主要厂家的铜BEOL工艺仅仅提供图1所示的由衬里38形成的三面覆盖，而导体39的第四表面即顶部表面被示为与介质接触，此介质通常是覆盖介质层42，其界面是铜原子输运和原子空洞的根源。
图4所示的测试结构75被用于电迁移寿命测量。图4示出了具有SiNx/SiO2介质的三层镶嵌互连的剖面图。介质层67具有通过W通孔77连接到衬里69下表面和铜导体70第一端的下W线条76。铜导体70在三个表面上具有衬里69，且宽度为0.28μm。铜导体70被电镀。铜导体70的第二端通过衬里79被连接到铜导体80的下表面。电子流从W线条76流到铜导体80。用CMP整平铜导体70和介质层67的上表面。然后在铜导体70的上表面上制作金属膜74。氮化硅组成的介质层66’被制作在层67和铜导体70上。介质层67’被制作在层66’上。在介质层67’中形成沟槽和通孔，并在沟槽和通孔中制作衬里，随之以用铜导体80进行填充。用CMP对层67’和铜导体80进行整平。铜导体80被选择成宽而短，以防止铜导体80中的电迁移损伤。氮化硅组成的层82被制作在层67’和铜导体80上。介质层84被制作在层82上。具有各种各样无电淀积的金属涂层74的以及图1所示的无涂层的测试结构75，在294℃和25mA/mm2下被测量电迁移。
图5示出了在294℃下的电迁移测试，说明了三面具有金属衬里69并在铜导体70的顶部表面上涂敷有金属层74的铜线的优异的寿命。在图5中，纵坐标表示R/R0，而横坐标表示时间，单位为小时。注意，作为监视着迁移速率的时间的函数的电阻变化，在图5中未曾达到1.2的正常失效水平，表示甚至在未被涂敷的铜线的20倍失效时间之后，被涂敷的样品的电阻改变20％。图5示出了金属涂层74明显地改善了电迁移寿命。测试结构75中的铜导体70的电阻变化被监测为跟踪正在发生的铜原子迁移的程度的手段，电阻随时间改变得越多，铜原子输运就越多，且铜导体寿命就越短。如图5所示，在曲线91-94所示的未被涂敷的样品中，电阻急剧地增大，而在所有被金属膜74涂敷的样品中，如曲线97-99所示，电阻变化很慢。在此测试中，正常寿命被定义为相对于其原来电阻R0变化20％，且直至至少2200小时之后仍然没有达到，而顶部表面无涂层的铜线在100小时之内就失效。发现曲线97所示的采用CoWP涂层74的变化速率最低，但曲线98所示的CoSnP以及曲线99所示的Pd的所有涂层74同样提供长的寿命。可望此改善外推到使用温度100℃会给出二个数量级以上的电迁移和应力迁移寿命增加，这意味着电路设计者有极大的灵活性，并有效地消除了作为使用电流限制因素的电迁移。还发现，在标准的未被涂敷的样品中产生空洞的热循环条件下，在同一组被涂敷的样品中未观察到原子应力空洞。这一测试结果进一步支持了未被介质涂敷的铜的表面或界面是电迁移因而是可靠性退化的主要根源的假说。
虽然已经描述了借助于在铜导体上表面上形成具有金属对金属的化学键合和金属键合的导电膜来改善铜导体中的抗电迁移性和降低应力引起的迁移的结构和方法，但对于本技术的熟练人员来说，显然可以作出各种修正和变化而不偏离仅仅被所附权利要求的范围所限制的本发明的宽广范围。

Claims (36)

1.具有高抗电迁移性的导体的制作方法，它包含下列步骤：在衬底上制作介质层，在所述介质层中制作至少一个沟槽，在所述沟槽中形成金属衬里，在所述金属衬里上形成导体来填充所述沟槽，形成与所述介质层上表面共平面的所述导体的被整平的上表面，以及在所述导体的所述上表面上形成导电膜，所述导电膜形成金属对金属的金属键。
2.权利要求1的方法，其特征在于，所述形成导电膜的步骤包括用无电淀积方法制作所述导电膜的步骤，从而所述导体的所述上表面被防止了氧化和腐蚀，并提供了高的抗电迁移性和高的抗热应力空洞性。
3.权利要求2的方法，其特征在于，所述无电淀积膜的厚度为1-20nm。
4.权利要求2的方法，其特征在于，所述无电淀积膜的厚度为1-10nm。
5.权利要求2的方法，其特征在于，所述无电淀积步骤包括下列步骤：
首先将所述衬底浸入金属离子溶液，从而在所述导体的所述上表面上形成一个金属纳米粒子层，
然后将所述衬底再次浸入金属离子和次磷酸盐离子的无电络合物溶液，从而在所述导体的所述上表面上形成一个金属磷化物导电膜，以及
在惰性或还原气氛中，于至少300℃的温度下，对所述衬底退火至少2小时，从而在所述导体与所述金属磷化物导电膜之间得到优异的粘附性。
6.权利要求5的方法，其特征在于，略去所述再次浸入步骤。
7.权利要求5的方法，其特征在于，所述导电膜选自CoWP、CoSnP、CoP、Pd、In和W构成的组，且厚度为1-20nm。
8.权利要求2的方法，其特征在于，所述无电淀积步骤包括下列步骤：
首先将所述衬底浸入金属离子溶液，从而在所述导体的表面上形成一个金属纳米粒子层，
然后将所述衬底再次浸入金属离子和二甲氨基硼烷的无电络合物溶液，从而在所述导体的所述上表面上形成一个金属-硼的导电膜层，以及
在惰性或还原气氛中，于至少300℃的温度下，对所述衬底退火至少2小时，从而在所述导体与所述金属硼导电膜之间得到优异的粘附性。
9.权利要求1的方法，其特征在于，用诸如化学汽相淀积(CVD)、物理汽相淀积(PVD)、蒸发、溅射、以及金属热互扩散之类的物理方法，将所述导电膜涂敷在所述导体的表面上。
10.权利要求9的方法，其特征在于，所述导电膜选自Pd、In、W、及其混合物构成的组。
11.一种结构，它包含：
衬底上的介质层，
制作在所述衬底上的所述介质中的至少一个沟槽，
制作在所述沟槽中的金属衬里，
填充所述沟槽的所述衬里上的导体，
具有所述介质层的上表面的所述导体的被整平了的上表面，以及
所述导体所述上表面上的导电膜，所述导电膜形成金属对金属的化学键和金属键。
12.权利要求11的结构，其特征在于，所述导电膜选自CoWP、CoSnP、CoP、Pd、CoB、CoSnB、CoWB、In、NiB和W构成的组，从而防止所述导体的所述上表面被氧化和腐蚀。
13.权利要求12的结构，其特征在于，所述导电膜的厚度为1-20nm。
14.权利要求12的结构，还包括所述导体和所述介质层上所述导电膜上的绝缘介质覆盖层。
15.权利要求14的结构，其特征在于，所述绝缘介质覆盖层选自氮化硅、氧化硅、介电常数小于3.2的SICOH的绝缘化合物、类金刚石碳、氟化类金刚石碳、和聚亚芳基醚构成的组。
16.权利要求11的结构，其特征在于，所述导体选自铜和铜合金构成的组。
17.权利要求11的结构，其特征在于，所述衬底选自硅、硅锗、SOI和砷化镓构成的组。
18.具有高抗电迁移性的导体的制作方法，它包含下列步骤：
在衬底上形成图形化的导体，
在所述导体的所述表面上形成导电膜，所述导电膜形成金属对金属的金属键。
19.权利要求18的方法，其特征在于，所述形成导电膜的步骤包括用无电淀积方法制作所述导电膜的步骤，从而所述导体的所述表面被防止了氧化和腐蚀，并提供了高的抗电迁移性和高的抗热应力空洞性。
20.权利要求19的方法，其特征在于，所述无电淀积膜的厚度为1-20nm。
21.权利要求19的方法，其特征在于，所述无电淀积膜的厚度为1-10nm。
22.权利要求19的方法，其特征在于，所述无电淀积步骤包括下列步骤：
首先将所述衬底浸入金属离子溶液，从而在所述导体的所述表面上形成一个金属纳米粒子层，
然后将所述衬底再次浸入金属离子和次磷酸盐离子的无电络合物溶液，从而在所述导体的所述表面上形成一个金属磷化物导电膜，以及
在惰性或还原气氛中，于至少300℃的温度下，对所述衬底退火至少2小时，从而在所述导体与所述金属磷化物导电膜之间得到优异的粘附性。
23.权利要求22的方法，其特征在于，略去所述再次浸入步骤。
24.权利要求22的方法，其特征在于，所述导电膜选自CoWP、CoSnP、CoP、Pd、In和W构成的组，且厚度为1-20nm。
25.权利要求19的方法，其特征在于，所述无电淀积步骤包括下列步骤：
首先将所述衬底浸入金属离子溶液，从而在所述导体的表面上形成一个金属纳米粒子层，
然后将所述衬底再次浸入金属离子和二甲氨基硼烷的无电络合物溶液，从而在所述导体的所述表面上形成一个金属-硼的导电膜，以及
在惰性或还原气氛中，于至少300℃的温度下，对所述衬底退火至少2小时，从而在所述导体与所述金属硼导电膜之间得到优异的粘附性。
26.权利要求18的方法，其特征在于，用诸如化学汽相淀积(CVD)、物理汽相淀积(PVD)、蒸发、溅射、以及金属热互扩散之类的物理方法，将所述导电膜涂敷在所述导体的表面上。
27.权利要求26的方法，其特征在于，所述导电膜选自Pd、In、W、及其混合物构成的组。
28.一种结构，它包含：
衬底上的图形化导体，
所述衬底表面上的导电膜，所述导电膜形成金属对金属的金属键。
29.权利要求28的结构，其特征在于，所述导电膜选自CoWP、CoSnP、CoP、Pd、CoB、CoSnB、CoWB、In、NiB和W构成的组，从而防止所述导体的所述上表面被氧化和腐蚀。
30.权利要求29的结构，其特征在于，所述导电膜的厚度为1-20nm。
31.权利要求29的结构，还包括所述导体的所述导电膜上的绝缘介质覆盖层。
32.权利要求31的结构，其特征在于，所述绝缘介质覆盖层选自氮化硅、氧化硅、介电常数小于3.2的SICOH的绝缘化合物、类金刚石碳、氟化类金刚石碳、和聚亚芳基醚构成的组。
33.权利要求29的结构，其特征在于，所述导体选自铜和铜合金构成的组。
34.权利要求29的结构，其特征在于，所述衬底选自硅、硅锗、SOI和砷化镓构成的组。
35.权利要求8的方法，其特征在于，所述导电膜选自CoB、CoSnB、CoWB和NiB构成的组。
36.权利要求25的方法，其特征在于，所述导电膜选自CoB、CoSnB、CoWB和NiB构成的组。
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