CN1359608A - 半导体管芯的对称封装 - Google Patents
半导体管芯的对称封装 Download PDFInfo
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- CN1359608A CN1359608A CN00809717A CN00809717A CN1359608A CN 1359608 A CN1359608 A CN 1359608A CN 00809717 A CN00809717 A CN 00809717A CN 00809717 A CN00809717 A CN 00809717A CN 1359608 A CN1359608 A CN 1359608A
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- lead
- wire
- tube core
- heat sink
- lead frame
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Abstract
本发明公开了一种半导体封装,它包括多个具有至少一个缺口的金属引线(440)。
Description
本发明涉及与本发明一起共同拥有且共同提出的专利申请第[美国代理记事表(Attorney Docket)第M-7546号]号,它在此处被全文引用作为参考。
背景技术
呈集成电路芯片(IC)形态的半导体器件在其被结合进诸如计算机或蜂窝电话的产品中时一般必需安装在诸如印刷电路板的平坦表面上。现在,没有一种表面安装半导体封装技术能满足下一代分立功率半导体器件和IC的需要。
这种表面安装功率封装应当包括至少以下特征:
1.低电阻;
2.分流并减小器件金属互连内横向电阻(1ateral resistance)的能力;
3.低热阻;
4.垂直(通过背面)或横向(顶侧)实现大电流的能力;
5.可制造性高;
6.低固有材料成本(intrinsic material cost);
7.低制造成本;
8.功率应用中的可靠运行;
9.便于至少三个(且优选地更多)到半导体的隔离连接的能力;
10.低剖面(高度)和小覆盖面积。
功率半导体器件和IC有两种,因其具有低的导通态电压降(因此具有低功耗)而传导大电流的那些,以及因其耗费大量功率而传导“大”电流的那些。因为这种功率器件的各种各样的使用、结构和运行,所以所列的初始两个特征(即低电阻)可以代替第三特征(低热阻)而实现,但是理想地,一个封装应当既提供低电阻又提供低热阻。
第四个特征,即横向或垂直大电流流动,说明功率封装理想地应当是对横向或垂直功率器件两者均可应用,但是,两个方向中的至少一个应当是大电流可用的。
当然,封装必须是高度可制造的,因为功率晶体管在世界范围内得以每年几十亿个地大量使用。对于这种器件的供给者和可能的用户,任何内在的制造可重复性或产率问题将有严重的后果。
另一个特征是低成本,包括封装材料成本及其制造成本。当然,材料成本是基本的,因为诸如金引线、塑料铸模、铜引线框等特定材料是基于世界原材料市场的,不能通过半导体产量的简单增加而大幅改变。使用更少量材料的封装设计生产起来本质上更便宜。
功率应用中封装的可靠性意味着,它必须经受得住功率器件中通常遭遇到的运行条件,诸如电流尖脉冲、比正常遇到的更高的环境温度、明显的自加热、重复热瞬变导致的热震等。电流或加热的重复脉冲可以引起与疲劳相关的损伤,尤其在金相接合和界面处。更少的界面是优选的。
二极管、瞬变抑制器和熔断器需要二引出端封装,而支持至少三个连接线的封装对分立晶体管是有用的。对于各种智能功率半导体元件,四个连接线直至八个连接线是极为有用的。在八个不同的连接线以上,这种功率封装技术的使用集中在功率集成电路上。
低剖面表面安装封装,虽然不是普遍要求,但却使之便于PC板的制造,因为封装在低剖面封装中的功率器件具有与同一板上的其它IC相同的特性,并且因而避免了对特殊处理的需要。在如电池组、PCMCIA卡和蜂窝电话的一些情形下,低剖面封装在满足最终产品的临界厚度方面可能是至关重要的。
小覆盖区域通常是整个产品尺寸的根源,尤其在便携式电子设备中,在该电子设备中,尺寸是重要的消费者购买标准-越小越好。
在相关考虑中,板上封装覆盖区越小,且它所包含的半导体管芯越大,则给定尺寸的性能越大。
虽然这些目的可能看起来明显,但事实是,现在的功率半导体封装技术未充分地、节约成本地满足这些需要,并且在一些情况下根本不满足该需要。传统封装的许多缺点是使用键合引线的结果。键合引线提供了附加电阻,并且在其热传导上效率低下,尤其是连接到功率MOSFET(金属-氧化物-半导体场效应晶体管)、绝缘栅极双极晶体管,或双极晶体管中顶侧源极焊点上的引线。一些公司已经试图开发到栅极上的无键合引线连接(abond-wireless connection),但是,这些尝试仍未成功,而且这些公司已经不得不回到引线键合栅极连接上。
图1A示出了一种这样的对制造功率MOSFET的工艺流程的尝试,它包括与栅极键合引线联合的无键合引线源极连接。在此流程中,管芯和顶部引线框之间的环氧树脂管芯粘结(和局部固化)之后,然后将管芯翻转过来,并通过环氧树脂将其粘结到底部引线框上。因为通过连接杆施加到引线框的管芯粘结部分上的扭矩,所以维持均匀的界面环氧树脂层是非常困难的。此外,在此流程中,引线键合必需在无键合引线管芯粘结后发生。在进行引线键合后,模塑、修剪和成型还必需进行。
图1B说明了一种环氧树脂粘结到管芯442上的顶部引线框440。弯曲金属的“驼峰”引线框440(即,上升和下降的引线框)使均匀的管芯粘结操作很困难。在管芯粘结后,图1C的平面图说明了顶部引线框440的无键合引线部分444和用于引线键合栅极的更短的“跳板(diving board)”片446。即使使用束缚在一侧的连接杆,在引线键合过程中固定引线框440仍是困难的。
在顶部引线框440粘结到管芯442上后,使用导电环氧树脂管芯粘结底部引线框448,如图1D的横截面视图和图1E的平面图所示。在管芯粘结和固化过程中控制扭矩和压力对于可靠的产品是关键的。于是,使用键合引线450来引线键合栅极引线446,如图1F的透视图所示。在同一封装中混合键合引线和无键合引线的方法在成本上具有不足,因为管芯引线框或管芯跨接线(die-strap)系统必需被移动到不同的机器上以进行引线键合。处理产品占用时间且花钱。事实上,此方法在实现可制造性上有如此多的问题,以致于它可能永远不被商业化使用,并且可能被完全放弃而不管行业内多年的投资。管芯开裂、可变的导通电阻,以及在运行或老化(burn-in)过程中改变的导通电阻都是这种方法的症状。
注意,在引线键合的过程中,栅极引线446与其自由端几乎没有支撑的跳板是机械相似的。它的运动使栅极键合452的质量不可靠且易变。图1G示出了模塑(如虚线454所示)后的另一种透视图。设计的不对称致使这种方法的制造复杂且不能再现。
图2A的流程图中示出了另一种方法。在此方法中,管芯首先粘接到铜跨接线层上以形成管芯和跨接线组件,于是随后将管芯和跨接线组件粘接到传统引线框上。在此第二粘接后,部件仍然必须被引线键合以连接器件的栅极。其后,该结构被模塑、修剪和成型。
在图2B中,还是驼峰状材料片,在此情形中,将“跨接线”460对准管芯462。跨接线460具有一致的宽度(见图2C),因而必须被定位,以不覆盖栅极键合焊点464(见图2E),但却仍然接触源极。跨接线460在图2D的横截面视图和图2E的平面视图中被示为源极引线,该源极引线被环氧树脂粘接到管芯462上以形成管芯和跨接线组件461。关键是,驼峰引线框460底部466和管芯462的底表面优选地是共面的,以避免随后工艺中的问题。
图2F的横截面视图和图2G的平面视图中示出的底部引线框470看起来像普通的引线框。注意,当引线框作为图2F-2R中的分立部分而抽出时,事实上,该部分由连接杆(未示出)连接。虽然可想象地它可以被预成形(即已经被弯曲),这使它更加难以搬运,但是引线框470在其被粘接到管芯上前一般是平坦的。
在图2H和2I中,包括管芯462和铜跨接线460的管芯和跨接线组件461被对准底部引线框470,该引线框涂覆有环氧树脂“点”472。在这一点上,环氧树脂点472与诸如栅极焊点464的管芯表面特征不一致。图2J是被挤压到底部引线框470上的管芯和跨接线组件461的视图,它在图2I所示的横截面J-J处截取。明显的是,管芯462和跨接线460底部466的底表面的共面是同时实现两个良好的、低电阻的环氧树脂接合的关键,这两个接合中的一个在管芯462下面,而另一个在底部466下面。因为第二接合具有有限的面积,所以与图1G中示出的三引出端无键合引线封装相比,此区域导致了增大的电阻。在图2I中横截面K-K处截取的栅极键合区的视图示于图2K内。
在通过压力挤压环氧树脂后,环氧树脂应当理想地均匀分布在金属跨接线的整个底部上和管芯下,如图2L所示。然而,因为组件是非对称的,所以均匀压力难以可重复地实现。如图2M的横截面视图和图2N的平面视图所示,于是进行引线键合480,然后注射模塑以形成图2O和2P所示的塑料封壳482。
明显地,传送大电流的环氧树脂层的数量大于其它封装方法-图2Q所示的设计中的三层,即环氧树脂层484、486和488。如图2R所示,一种在引线框470下引入热沉(heat sink)492的选择包括另一环氧树脂层490。该设计完全依赖于环氧树脂层490以将热沉492固定在引线框470上,而没有任何将其“锁”在适当位置上的机构。此外,此设计具有该缺点,即粘接到管芯焊点上和热沉上的许多引线均一起被缩短了。这些引线大体上被“浪费”了,因为热沉能在没有它们时传送电流。
再者,尤其在许多环氧树脂管芯粘接的步骤中,设计的非对称性使此设计的大量可制造性成为可疑。明显地,大量的工艺步骤使之昂贵。狭缝引线框的非平坦表面(即包括栅极和源极连接的引线框)是特别成问题的,因为在顶侧管芯粘接过程中,任何下沉(downset)均使共面问题恶化。
在以上示出的无键合引线技术的两种尝试中,栅极焊点不通过无键合引线连接,而必须通过键合引线而电粘接到引线框上,理想地,键合引线在源极连接的同时进行。无键合引线栅极的接触仍未成功的原因在于在栅极和源极引线间缺乏共面。图3A-3H说明了三引出端无键合引线封装中的共面问题。在图3A中,下沉引线框402和硅管芯404(具有涂覆的导电环氧树脂点406)对准并如3B那样进行接触。理想地,恒定压力和最小扭矩将把栅极引线408(薄的孤立引线)和更宽的源极金属410这两者以相同的力挤压到管芯表面上。但是,实际上难以保证两个引线408和410的粘接表面共面,即意味着在同一水平面上。对于连接杆(未示出),容易的是,弯曲一个小量使得栅极引线408的粘接表面例如可以略为位于源极引线410的粘接表面上方。如图3C所示,此共面问题的结果是栅极引线408未以充足的力挤压管芯404以重新分布环氧树脂。结果,栅极引线408与栅极焊点412(示于图3A)将具有不良的(或没有)接触。
为了进一步阐明此问题,图3D说明了一个被正确挤压到环氧树脂中间层416上以得到与焊点418的良好接触的下沉引线414。在图3E中,下沉引线420平行于焊点418表面,但永不接触,这导致开路和无用的器件。在图3F中,引线422被弯曲而仅在其跟部接触,而在图3G中,仅引线424的尖部接触环氧树脂416。在图3H中,引线426仅接触环氧树脂416,但接触如此之轻微,以致于它未正确地重新分布环氧树脂416,这导致不良的电接触。
在无键合引线封装中出现的另一问题是相邻引线之间的短路,这是使管芯引线框粘接所用的液态环氧树脂或焊料铺展的结果。如图4A的横截面所示,环氧树脂430以非常大的力被挤压(或涂覆了非常多的环氧树脂),这导致源极引线框432和栅极引线框434之间的横向短路,如图4B中平面视图所示。
另一问题具体地针对垂直平坦型或槽栅极型DMOSFET的封装出现。该器件顶部表面的大部分被源极金属层覆盖,而栅极焊点与源极金属一般由2至15μm宽的间隙电隔离。顶部表面的外边界一般包括一金属环,该环与底部表面上的漏极短路,被称作等电位环或EQR,主要为了获得抵抗离子迁徙的提高的可靠性的目的而引入。此外部环是安装过程中源极或栅极连接之间意外短路的危险之源。硅延伸而再超过此环20至70μm。凸出的硅在尺寸上因晶片被切成独立管芯时的切割工艺而改变。管芯的此区域还以漏极电位偏置,并且还可能在封装过程中与连接至键合引线的源极或栅极短路。
发明内容
根据本发明的半导体封装包括:一半导体管芯,该管芯具有第一和第二主表面;电粘结在管芯第一主表面的第一引出端上的热沉;以及电粘结至管芯第二主表面的至少一引出端上的至少一引线。该引线由金属平坦薄片形成,并在管芯的对立边缘上方横向延伸。在引线经过管芯的每个对立边缘上方的位置上,在引线面对管芯的一侧在引线上形成缺口,从而确保引线不与邻近管芯边缘的第二主表面的一部分电接触。该管芯和至少一部分热沉包裹在诸如塑料的非导电材料内。
一般地,引线关于管芯的轴对称。引线相对端通常被弯曲,优选地在制造工艺结尾时,以形成能电安装到诸如印刷电路板的平坦物体上的表面。
因为引线关于管芯对称,所以常常不需要与引线框内的引线连接的中心连接杆。取而代之,引线在引线框内可以通过一对位于引线框相对侧上的连接杆连到一起。
在一组实施例中,管芯包括一个功率MOSFET,且至少两个电隔离的引线与管芯的第二主表面电接触,第一引线与源极引出端接触,而第二引线与栅极引出端接触。该热沉与管芯的漏极引出端电接触。在一些实施例中,多个引线与源极引出端接触。该多个引线中的各引线可以在它们接触源极引出端的区域内合并。引线和热沉用导电环氧树脂或焊料粘结到管芯上。
热沉可以包括一边缘和一个以上的缺口以在热沉和塑料封壳之间建立牢固连接。该封壳可以从热沉的一个或多于一个的边缘部分被阻挡。
一孔阵列可以形成在热沉被粘接到管芯第一主表面上的表面上。
在一组可选实施例中,引线弯离管芯以代替引线上的缺口或与引线上的缺口共同在引线和第二主表面邻近管芯边缘的部分之间形成间隔。
根据本发明的另一方面,半导体封装包括至少一个与半导体管芯表面接触的薄片金属引线。在引线与管芯接触的一侧上形成沟槽,该沟槽平行于引线边缘延伸。该沟槽抑制了诸如环氧树脂或焊料的管芯粘接材料(它在灼热时是液体)铺展出来形成短路。在许多实施例中,至少两个邻近的引线与管芯接触,且每根引线包括一个沟槽以防止短路在邻近引线间形成。
本发明还包括一种制造在半导体封装中使用的引线框的方法。该工艺包括构图金属薄片以形成引线框,并在引线中的至少一根的表面上形成缺口。该缺口可以通过刻蚀或冲压金属形成。缺口一般具有等于金属薄片厚度的10%至80%的深度。该工艺还可以包括将引线框粘接到半导体管芯的第一主表面上,使得该缺口覆盖管芯的至少一个边缘。在许多实施例中,在引线框上形成至少两个缺口,且该引线框粘接在管芯上,使得至少两个缺口重叠在管芯的对立边缘上。该工艺还可以包括将热沉粘接到管芯的第二表面上。
本发明还包括包含不只一个管芯的封装,即在引线框不包含中心连接杆的封装中得以具体实现的排列。
附图说明
图1A是制造包括无键合引线源极连接和键合引线栅极连接的功率MOSFET封装的公知工艺的流程图;
图1B-1G是说明图1A工艺的视图;
图2A是制造包括管芯和跨接线组件的功率MOSFET封装的公知工艺的流程图;
图2B-2R是示出图2A工艺的视图;
图3A-3H示出了封装设计中引线共面的问题;
图4A和4B示出了一种方式,形成连接中使用的环氧树脂或焊料通过该方式可以向外铺展,从而在邻近引线间导致短路;
图5是根据本发明制造半导体封装的工艺顺序的流程图;
图6A-6F示出图5所述的工艺步骤;
图7A-7H示出根据本发明将至少两个方片(dice)粘接到条形引线框上的工艺步骤;
图8A-8F示出首先将管芯粘接到引线框上,然后粘接到热沉上的工艺步骤;
图8G-8J示出首先将管芯粘接到热沉上,然后粘接到引线框上的工艺步骤;
图9A-9D示出根据本发明的塑料封壳的透视图,示出了显露热沉的各种方式;
图9E-9H示出图9A-9D所示塑料封壳的仰视图;
图10A和10B分别是包括带缺口的T型热沉的封壳的截面图和仰视图,该热沉具有将热沉固定在封壳内的边;
图10C是与图10A和10B所示的封壳相似的封壳的横截面视图,不同之处在于热沉从塑料封壳的底部凸出;
图10D是一种热沉的横截面视图,该热沉沿其侧部具有第二缺口以进一步将热沉固定在封壳内;
图10E是具有边但没有缺口的T形热沉的横截面视图;
图10F和10G分别是一种热沉的横截面视图和仰视图,该热沉具有边和在边上形成的一系列孔;
图10H和10I分别是一种热沉的横截面视图和仰视图,该热沉具有绕其周边形成的一系列孔或凹陷,以进一步固定塑料封壳;
图10J和10K分别是热沉和管芯的横截面视图和仰视图,该热沉具有在其顶表面形成的孔或凹陷的阵列;
图10L是包括图10A-10K所示的若干特征的半导体封装的横截面视图;
图11A和11B分别示出引线框的俯视图和横截面视图,该引线框包括防止环氧树脂或焊料在邻近引线间形成短路的沟槽;
图12A-12F示出引线的各种形状的平面图,该形状可以根据本发明形成;以及
图13A-13F示出一可选实施例,其中,引线框被弯曲以确保其与管芯边缘隔开。
具体实施方式
图5示出根据本发明制造包括对称引线框的半导体封装的工艺顺序。该工艺主要使用了三个部件:一个半导体管芯、一个对称引线框和一个粘接在管芯底部的热沉。有两种可选的工艺流程。在第一工艺中,首先使用导电环氧树脂或软焊料将管芯粘接到对称引线框上。如果使用环氧树脂,该环氧树脂必须固化。然后再次使用环氧树脂或焊料将热沉粘接到管芯底部。或者,首先将管芯粘接到热沉上,然后粘接到引线框上。在每种情况中,结果均是包括热沉、管芯和对称引线框的夹层结构。
然后在管芯周围喷射模塑塑料封壳,修剪引线框以去除外部连接杆,并弯曲或成形引线以允许它们连接到诸如电路板的平坦表面上。
图6A-6F示出优选工艺。该工艺用于封装诸如功率MOSFET的三引出端管芯。MOSFET110包括源极引出端112、栅极引出端114和在管芯110底面上的漏极引出端(未示出)。
如图6A所示,引线框100包括将要被粘接到源极引出端112上的较大的中心部分102,和将要被粘接到栅极引出端114上的较细引线104。部分102和引线104通过连接杆107和109连在一起。在部分102上形成六个切口106,形成总共八个源极引线。引线框100一般由诸如铝或铜的金属薄片形成,并且为3至15密耳厚,6-7密耳是常见厚度。
图6B示出引线框100的下侧。在部分102中,缺口116和118在部分102将要重叠管芯110的边缘的位置上形成。相似地,缺口120和122在引线104上形成。缺口116、118、120和122可以具有在引线框100的总厚度的10%至80%的范围内变化的深度。一般地,缺口116、118、120和122的深度将大约为引线框100的厚度的20%。例如,如果引线框100为6或7密耳厚,则缺口将大约为2密耳(50μm)深。缺口116、118、120和122可以使用公知的“半刻蚀”工艺从引线框上刻蚀,或者它们可以使用还可以用于形成孔106的冲压机形成。
缺口116、118、120和122需要足够宽,以容许管芯放置的偏差,和用于分割小方片(dice)的锯条宽度(称为“切口”)的变化。一般地,缺口为4密耳宽和2密耳深。
图6C示出通过环氧树脂层124粘接到管芯110上的引线框100,其中缺口116、118、120和122悬在管芯110的各边缘之上。这确保引线框100不接触管芯110的边缘,如上所述,该边缘可以包括诸如等电位环(EQR)的敏感元件,该等电位环以管芯背侧的电压偏置。环氧树脂124可以涂覆在引线框100上或管芯110上,尽管环氧树脂一般涂覆在引线框上。然后,引线框100和管芯110被放置在管芯粘接机上,它们在此粘接机中被挤压到一起。然后将环氧树脂局部或全部固化,使得其与引线框100和管芯110上的接触点、面或区域发生化学反应。
图6D示出了引线框100和管芯110与粘接到管芯110背侧上的热沉126的结合。热沉126按与上述相同的方式用环氧树脂粘接到管芯110上。热沉126可以用铜制造,并包含边缘128,其功能在以下描述。
然后,该结构被包覆在注射模塑塑料得封壳(未示出)内,并且如图6E所示,连接杆107和109被修剪掉,产生6根连接到管芯110源极引出端上的引线130A-130F,和2根连接到管芯110栅极引出端上的引线132A和132B。清楚的是,引线130A-130F以及132A和132B形成关于管芯110的轴131对称的结构。此外,直到引线从引线框上剪下时,引线仅由外连接杆107和109保持稳定,而且不需要任何中心连接杆,该中心连接杆对于以上引用的申请[美国代理记事表第M-7546号]所述的非对称设计产生扭曲和翘曲。
图6F示出引线130A-130F以及132A和132B已经被弯曲,使得引线外侧部分的底部被弯曲平坦且共面,并能与诸如印刷电路板的平坦表面接触之后的结构。图6F还示出了包裹管芯110的塑料封壳134。塑料封壳134未覆盖热沉126的底表面,该底表面保持暴露以向管芯110的背侧提供电接触。在图6F中,热沉126的边缘也保持暴露(如箭头表示),以允许直观确认用于在热沉126和印刷电路板之间形成连接的环氧树脂或焊料已正确地润湿和流动(并且在环氧树脂的情形中,均匀地分布),以建立良好的电连接。
如上所述,热沉126是如铜的金属块。虽然热沉126用以将热传离管芯110,但是任何金属块可用于取代热沉126,无论在具体应用中它是否主要用作“热沉”或热导体。在一些应用中,金属块主要可用作到管芯背侧的低电阻连接。于是,如此处所使用的,术语“热沉”包括用于与管芯背侧(底部)形成电和/或热连接的任何金属块或片。
一个单独的引线框可以包含图6A所示的源极和栅极引线的多个重复。例如,图7A所示的引线框140包括栅极引线140G1和140G2以及源极引线140S1和140S2。图7B示出具有定位在引线框上方的小方片142A和142B的引线框140,图7C示出粘接在引线框140上的小方片142A和142B。图7D分别示出粘接在小方片142A和142B上的热沉144A和144B。最后,在图7E中,小方片142A和142B分别包裹在塑料封壳146A和146B内。
在塑料封壳已经模塑后,连接杆被修剪掉,留下图7F所示的具有自封装的每侧伸出的四根引线的结构。如上所述,引线148A中的6根连接到源极引出端,而引线148A中的2根连接到栅极引出端。引线148A于是被弯曲,以形成表面安装封装,如图7G所示。
还可以将整个结构模塑到多管芯塑料封壳149内,该封壳包括小方片142A和142B两者,并具有8根引线,而不是4根引线,如图7H所示。使用本发明的引线框,这是非常方便的,因为在许多实施例中,没有将在塑料封壳内的邻近小方片之间产生电连接的中心连接杆。
图8A示出定位在管芯142A上方的引线框140的横截面视图,具有在引线框140表面上的环氧树脂点150。图8B示出粘接到引线框140上的管芯142。环氧树脂点150已铺展开,以形成单环氧树脂层152。注意,引线框140中的缺口重叠在管芯142A的边缘上方。图8C示出定位在热沉144A上方的管芯142A,而图8D示出通过环氧树脂层154粘接的管芯142A和热沉144A。图8E示出在塑料封壳156已经绕管芯142A和热沉144A喷射模塑后的结构,引线148A从每一侧伸出。图8F中,引线148A已经被弯曲,以形成表面安装封装。注意,热沉144A的底面得以显露。
如图8G-8J所示,粘接工艺可以颠倒,即先将管芯142A粘接到热沉144A上,然后粘接到引线框140上。
图9A-9D是透视图,示出暴露热沉的一条或一条以上边缘以允许对热沉和安装它的表面之间的粘结的直观检测的不同方式。图9A中,热沉144A的整个周边得以显露。图9B中,热沉144A的对立的较短边缘得以显露。图9C中,热沉144A的对立的较长边缘得以显露。图9D中,热沉144A的两条对立边缘得以显露,且将塑料封壳156开口以允许其它边缘的片断得以显露。图9E-9H分别是图9A-9D所示结构的仰视图,其中,虚线代表塑料封壳的边缘。
图10A示出带缺口的T形热沉144A,该热沉包括如上所述的边160以及在边160下侧上的缺口158。此布置将热沉“锁”在塑料封壳156上,并防止了热沉和重叠的管芯(图10A中未示出)之间的分层。图10B是图10A所示结构的仰视图。图10C示出一种变体的横截面视图,其中热沉144的底部略微从塑料封壳156凸出。
在图10D所示的布置中,缺口162在热沉144A的底部附近形成,进一步强化了塑料封壳和热沉之间的结合。缺口162可以沿热沉144A的所有或部分侧面行进。图10E是热沉144A的另一形式的横截面视图,该热沉包括边160但不包括缺口。图10F和10G示出一种可选热沉144A,它具有在边160周围间隔形成的孔164。这进一步巩固了热沉和环绕的塑料封壳之间的粘结。
T形热沉144的再一种形式示于图10H和10I,其中在热沉的顶部表面上形成一系列孔166。在图10J和10K所示的实施例中,孔168还形成在将要放置管芯142A的位置上。孔168为用于粘结管芯142A和热沉144A的环氧树脂或焊料提供了容器,从而增加了这些元件之间的结合。例如,孔166和168在直径上可以为10至50μm。
图10L示出了结合以上描述的诸多特征的一个实施例,包括边160、缺口158、被塑料填充的孔166和被管芯粘接环氧树脂或焊料填充的孔168。
如上所述,当液态环氧树脂或焊料因管芯和引线框之间的压力而铺展开时,相邻引线之间的短路可能发生。此问题的一种解决方案示于图11A和11B,其中,沟槽170和172在相邻引线140G1和140S1内形成。沟槽170和172提供了在引线框140被挤压到管芯142A上时环氧树脂可以扩展的空间。沟槽170和172被示出比重叠在管芯142A边缘上方的缺口174窄,但是并非必须这样。例如,沟槽可以0.25至4密耳宽(一般1密耳)和1至4密耳深。优选地,各沟槽的深度和宽度是相等的。
沟槽可以沿任何引线的边缘形成,在该边缘存在铺展的环氧树脂或焊料导致的短路危险。
在根据本发明的引线框中,引线可以采取许多种形状和图案。图12A-12F的平面图中示出了若干可能性。图12A示出了粘接到管芯182和热沉180上的条形引线184,一种用于封装二极管和其它二引出端器件的结构。图12B中,引线184具有接触管芯的较宽部分184A。图12C示出分别具有粘接到管芯182上的较宽部分190A和192A的引线190和192,一种用于封装双二极管、双极晶体管、功率MOSFET、JFET(结型场效应晶体管)和许多其它三引出端器件的具有三个分立的电引出端的结构。图12D中,条形引线200与具有较宽部分202A的引线202结合。图12E示出与具有较宽部分212A的趾状引线212结合的条形引线210,一种用于封装具有三个电连接的器件的结构,在该器件中需要超过三个的管脚。最后,图12F示出与趾状引线222结合的具有偏移部分的条形引线220。
作为对重叠在管芯边缘上方的缺口的另一种方案,在本发明的另一实施例中,引线框被弯曲以形成引线框经过管芯边缘上方的另一种方案。例如,图13A中,引线框240包括在引线框240和管芯250边缘间提供间隔的弯曲246和248。图13B示出粘接到管芯250上的引线框240,而图13C示出从管芯底部观察的同样结构。图13D中,热沉260粘接到管芯250底部上。完成后的结构在图13E中从热沉的底部示出,而在图13F中从引线框240的顶部示出。
此处的公开内容是说明性的,而不是限制性的。虽然根据本发明的具体实施例已经得以描述,但是,对本领域技术人员而言,明显的是,本发明的主旨包括大范围的备选实施例。
Claims (3)
1.一种半导体封装,包括:
具有第一和第二主表面的半导体管芯;
粘接至管芯第一表面上的热沉;
粘接至管芯第二表面上的引线,所述引线在管芯的对立边缘上方延伸,在引线面对管芯的一侧上在引线上形成缺口,所述缺口位于引线越过管芯边缘的位置上;以及
包裹该管芯以及引线和热沉的至少一部分的非导电封壳,引线的相对端从封壳伸出。
2.如权利要求1所述的半导体封装,其特征在于,引线关于管芯的轴对称。
3.如权利要求2所述的半导体封装,其特征在于,在引线越过管芯第一边缘的位置上在引线上形成第一缺口,而在引线越过管芯第二边缘的位置上在引线上形成第二缺口。
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Families Citing this family (134)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6143981A (en) | 1998-06-24 | 2000-11-07 | Amkor Technology, Inc. | Plastic integrated circuit package and method and leadframe for making the package |
JP3871486B2 (ja) * | 1999-02-17 | 2007-01-24 | 株式会社ルネサステクノロジ | 半導体装置 |
US6740969B1 (en) * | 1999-08-25 | 2004-05-25 | Renesas Technology Corp. | Electronic device |
KR20010037247A (ko) * | 1999-10-15 | 2001-05-07 | 마이클 디. 오브라이언 | 반도체패키지 |
US6459147B1 (en) | 2000-03-27 | 2002-10-01 | Amkor Technology, Inc. | Attaching semiconductor dies to substrates with conductive straps |
US6521982B1 (en) * | 2000-06-02 | 2003-02-18 | Amkor Technology, Inc. | Packaging high power integrated circuit devices |
JP3510838B2 (ja) * | 2000-03-24 | 2004-03-29 | 三洋電機株式会社 | 半導体装置およびその製造方法 |
US7042068B2 (en) | 2000-04-27 | 2006-05-09 | Amkor Technology, Inc. | Leadframe and semiconductor package made using the leadframe |
JP3602453B2 (ja) * | 2000-08-31 | 2004-12-15 | Necエレクトロニクス株式会社 | 半導体装置 |
CN1222092C (zh) * | 2000-11-29 | 2005-10-05 | 三菱化学株式会社 | 半导体发光器件 |
US6566164B1 (en) | 2000-12-07 | 2003-05-20 | Amkor Technology, Inc. | Exposed copper strap in a semiconductor package |
US6777786B2 (en) * | 2001-03-12 | 2004-08-17 | Fairchild Semiconductor Corporation | Semiconductor device including stacked dies mounted on a leadframe |
US6545345B1 (en) | 2001-03-20 | 2003-04-08 | Amkor Technology, Inc. | Mounting for a package containing a chip |
KR100369393B1 (ko) | 2001-03-27 | 2003-02-05 | 앰코 테크놀로지 코리아 주식회사 | 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법 |
US6756658B1 (en) | 2001-04-06 | 2004-06-29 | Amkor Technology, Inc. | Making two lead surface mounting high power microleadframe semiconductor packages |
US6630726B1 (en) | 2001-11-07 | 2003-10-07 | Amkor Technology, Inc. | Power semiconductor package with strap |
US6608366B1 (en) | 2002-04-15 | 2003-08-19 | Harry J. Fogelson | Lead frame with plated end leads |
US6707148B1 (en) * | 2002-05-21 | 2004-03-16 | National Semiconductor Corporation | Bumped integrated circuits for optical applications |
JP2004079760A (ja) * | 2002-08-19 | 2004-03-11 | Nec Electronics Corp | 半導体装置及びその組立方法 |
US6818973B1 (en) | 2002-09-09 | 2004-11-16 | Amkor Technology, Inc. | Exposed lead QFP package fabricated through the use of a partial saw process |
US6905914B1 (en) | 2002-11-08 | 2005-06-14 | Amkor Technology, Inc. | Wafer level package and fabrication method |
US7723210B2 (en) | 2002-11-08 | 2010-05-25 | Amkor Technology, Inc. | Direct-write wafer level chip scale package |
US6798047B1 (en) | 2002-12-26 | 2004-09-28 | Amkor Technology, Inc. | Pre-molded leadframe |
US6750545B1 (en) | 2003-02-28 | 2004-06-15 | Amkor Technology, Inc. | Semiconductor package capable of die stacking |
US6794740B1 (en) | 2003-03-13 | 2004-09-21 | Amkor Technology, Inc. | Leadframe package for semiconductor devices |
US6919625B2 (en) * | 2003-07-10 | 2005-07-19 | General Semiconductor, Inc. | Surface mount multichip devices |
JP4294405B2 (ja) * | 2003-07-31 | 2009-07-15 | 株式会社ルネサステクノロジ | 半導体装置 |
DE10345247B4 (de) * | 2003-09-29 | 2007-10-04 | Infineon Technologies Ag | Verwendung von Leiterbahnen als Krallkörper |
DE10352079A1 (de) * | 2003-11-08 | 2005-06-02 | Robert Bosch Gmbh | Elektromotor, sowie Verfahren zur Herstellung eines solchen |
US7432595B2 (en) * | 2003-12-04 | 2008-10-07 | Great Wall Semiconductor Corporation | System and method to reduce metal series resistance of bumped chip |
WO2005059957A2 (en) * | 2003-12-12 | 2005-06-30 | Great Wall Semiconductor Corporation | Metal interconnect system and method for direct die attachment |
JP4302607B2 (ja) * | 2004-01-30 | 2009-07-29 | 株式会社デンソー | 半導体装置 |
US7132314B2 (en) * | 2004-05-28 | 2006-11-07 | Texas Instruments Incorporated | System and method for forming one or more integrated circuit packages using a flexible leadframe structure |
DE102004041088B4 (de) * | 2004-08-24 | 2009-07-02 | Infineon Technologies Ag | Halbleiterbauteil in Flachleitertechnik mit einem Halbleiterchip und Verfahren zu seiner Herstellung |
US7202113B2 (en) * | 2005-06-09 | 2007-04-10 | Ming Sun | Wafer level bumpless method of making a flip chip mounted semiconductor device package |
US8334583B2 (en) * | 2005-07-20 | 2012-12-18 | Infineon Technologies Ag | Leadframe strip and mold apparatus for an electronic component and method of encapsulating an electronic component |
JP4764692B2 (ja) * | 2005-09-29 | 2011-09-07 | 日立オートモティブシステムズ株式会社 | 半導体モジュール |
US7786555B2 (en) * | 2005-10-20 | 2010-08-31 | Diodes, Incorporated | Semiconductor devices with multiple heat sinks |
US7507603B1 (en) | 2005-12-02 | 2009-03-24 | Amkor Technology, Inc. | Etch singulated semiconductor package |
US7572681B1 (en) | 2005-12-08 | 2009-08-11 | Amkor Technology, Inc. | Embedded electronic component package |
WO2007075742A2 (en) | 2005-12-21 | 2007-07-05 | Cree Led Lighting Solutions, Inc. | Lighting device |
US7572675B2 (en) * | 2006-01-24 | 2009-08-11 | Asm Technology Singapore Pte Ltd. | Mold flash removal process for electronic devices |
US7648257B2 (en) * | 2006-04-21 | 2010-01-19 | Cree, Inc. | Light emitting diode packages |
US7902660B1 (en) | 2006-05-24 | 2011-03-08 | Amkor Technology, Inc. | Substrate for semiconductor device and manufacturing method thereof |
US7968998B1 (en) | 2006-06-21 | 2011-06-28 | Amkor Technology, Inc. | Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package |
JP5036819B2 (ja) * | 2006-09-18 | 2012-09-26 | クリー インコーポレイテッド | 照明装置、照明アセンブリー、取付体、および、これらを用いる方法 |
WO2008036873A2 (en) * | 2006-09-21 | 2008-03-27 | Cree Led Lighting Solutions, Inc. | Lighting assemblies, methods of installing same, and methods of replacing lights |
CN101611258A (zh) * | 2006-11-14 | 2009-12-23 | 科锐Led照明科技公司 | 光引擎组件 |
US8439531B2 (en) * | 2006-11-14 | 2013-05-14 | Cree, Inc. | Lighting assemblies and components for lighting assemblies |
US7687893B2 (en) | 2006-12-27 | 2010-03-30 | Amkor Technology, Inc. | Semiconductor package having leadframe with exposed anchor pads |
US7829990B1 (en) | 2007-01-18 | 2010-11-09 | Amkor Technology, Inc. | Stackable semiconductor package including laminate interposer |
US7982297B1 (en) | 2007-03-06 | 2011-07-19 | Amkor Technology, Inc. | Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same |
JP4489094B2 (ja) * | 2007-04-27 | 2010-06-23 | 株式会社東芝 | 半導体パッケージ |
US7967480B2 (en) * | 2007-05-03 | 2011-06-28 | Cree, Inc. | Lighting fixture |
TWI426204B (zh) | 2007-05-07 | 2014-02-11 | Cree Inc | 照明設備及照明裝置 |
US7977774B2 (en) | 2007-07-10 | 2011-07-12 | Amkor Technology, Inc. | Fusion quad flat semiconductor package |
US7687899B1 (en) | 2007-08-07 | 2010-03-30 | Amkor Technology, Inc. | Dual laminate package structure with embedded elements |
US7777351B1 (en) | 2007-10-01 | 2010-08-17 | Amkor Technology, Inc. | Thin stacked interposer package |
US8089159B1 (en) | 2007-10-03 | 2012-01-03 | Amkor Technology, Inc. | Semiconductor package with increased I/O density and method of making the same |
US7821111B2 (en) * | 2007-10-05 | 2010-10-26 | Texas Instruments Incorporated | Semiconductor device having grooved leads to confine solder wicking |
US7847386B1 (en) | 2007-11-05 | 2010-12-07 | Amkor Technology, Inc. | Reduced size stacked semiconductor package and method of making the same |
WO2009081723A1 (ja) * | 2007-12-20 | 2009-07-02 | Fuji Electric Device Technology Co., Ltd. | 半導体装置およびその製造方法 |
US7800219B2 (en) * | 2008-01-02 | 2010-09-21 | Fairchild Semiconductor Corporation | High-power semiconductor die packages with integrated heat-sink capability and methods of manufacturing the same |
US7960845B2 (en) | 2008-01-03 | 2011-06-14 | Linear Technology Corporation | Flexible contactless wire bonding structure and methodology for semiconductor device |
US7956453B1 (en) | 2008-01-16 | 2011-06-07 | Amkor Technology, Inc. | Semiconductor package with patterning layer and method of making same |
US7723852B1 (en) | 2008-01-21 | 2010-05-25 | Amkor Technology, Inc. | Stacked semiconductor package and method of making same |
US7812430B2 (en) * | 2008-03-04 | 2010-10-12 | Powertech Technology Inc. | Leadframe and semiconductor package having downset baffle paddles |
US8067821B1 (en) | 2008-04-10 | 2011-11-29 | Amkor Technology, Inc. | Flat semiconductor package with half package molding |
US7768135B1 (en) | 2008-04-17 | 2010-08-03 | Amkor Technology, Inc. | Semiconductor package with fast power-up cycle and method of making same |
US7808084B1 (en) | 2008-05-06 | 2010-10-05 | Amkor Technology, Inc. | Semiconductor package with half-etched locking features |
US7619307B1 (en) * | 2008-06-05 | 2009-11-17 | Powertech Technology Inc. | Leadframe-based semiconductor package having arched bend in a supporting bar and leadframe for the package |
US8240875B2 (en) | 2008-06-25 | 2012-08-14 | Cree, Inc. | Solid state linear array modules for general illumination |
US8125064B1 (en) | 2008-07-28 | 2012-02-28 | Amkor Technology, Inc. | Increased I/O semiconductor package and method of making same |
US8184453B1 (en) | 2008-07-31 | 2012-05-22 | Amkor Technology, Inc. | Increased capacity semiconductor package |
US7902665B2 (en) * | 2008-09-02 | 2011-03-08 | Linear Technology Corporation | Semiconductor device having a suspended isolating interconnect |
US7847392B1 (en) | 2008-09-30 | 2010-12-07 | Amkor Technology, Inc. | Semiconductor device including leadframe with increased I/O |
US7989933B1 (en) | 2008-10-06 | 2011-08-02 | Amkor Technology, Inc. | Increased I/O leadframe and semiconductor device including same |
US8008758B1 (en) | 2008-10-27 | 2011-08-30 | Amkor Technology, Inc. | Semiconductor device with increased I/O leadframe |
US8089145B1 (en) | 2008-11-17 | 2012-01-03 | Amkor Technology, Inc. | Semiconductor device including increased capacity leadframe |
US8072050B1 (en) | 2008-11-18 | 2011-12-06 | Amkor Technology, Inc. | Semiconductor device with increased I/O leadframe including passive device |
US7875963B1 (en) | 2008-11-21 | 2011-01-25 | Amkor Technology, Inc. | Semiconductor device including leadframe having power bars and increased I/O |
US8124449B2 (en) | 2008-12-02 | 2012-02-28 | Infineon Technologies Ag | Device including a semiconductor chip and metal foils |
US7982298B1 (en) | 2008-12-03 | 2011-07-19 | Amkor Technology, Inc. | Package in package semiconductor device |
US8487420B1 (en) | 2008-12-08 | 2013-07-16 | Amkor Technology, Inc. | Package in package semiconductor device with film over wire |
US8680656B1 (en) | 2009-01-05 | 2014-03-25 | Amkor Technology, Inc. | Leadframe structure for concentrated photovoltaic receiver package |
US20170117214A1 (en) | 2009-01-05 | 2017-04-27 | Amkor Technology, Inc. | Semiconductor device with through-mold via |
US8058715B1 (en) | 2009-01-09 | 2011-11-15 | Amkor Technology, Inc. | Package in package device for RF transceiver module |
US8026589B1 (en) | 2009-02-23 | 2011-09-27 | Amkor Technology, Inc. | Reduced profile stackable semiconductor package |
US7960818B1 (en) | 2009-03-04 | 2011-06-14 | Amkor Technology, Inc. | Conformal shield on punch QFN semiconductor package |
US8575742B1 (en) | 2009-04-06 | 2013-11-05 | Amkor Technology, Inc. | Semiconductor device with increased I/O leadframe including power bars |
US8796561B1 (en) | 2009-10-05 | 2014-08-05 | Amkor Technology, Inc. | Fan out build up substrate stackable package and method |
US8937381B1 (en) | 2009-12-03 | 2015-01-20 | Amkor Technology, Inc. | Thin stackable package and method |
US9691734B1 (en) | 2009-12-07 | 2017-06-27 | Amkor Technology, Inc. | Method of forming a plurality of electronic component packages |
US8324511B1 (en) | 2010-04-06 | 2012-12-04 | Amkor Technology, Inc. | Through via nub reveal method and structure |
US8294276B1 (en) | 2010-05-27 | 2012-10-23 | Amkor Technology, Inc. | Semiconductor device and fabricating method thereof |
US8440554B1 (en) | 2010-08-02 | 2013-05-14 | Amkor Technology, Inc. | Through via connected backside embedded circuit features structure and method |
US8487445B1 (en) | 2010-10-05 | 2013-07-16 | Amkor Technology, Inc. | Semiconductor device having through electrodes protruding from dielectric layer |
US8791501B1 (en) | 2010-12-03 | 2014-07-29 | Amkor Technology, Inc. | Integrated passive device structure and method |
US8674485B1 (en) | 2010-12-08 | 2014-03-18 | Amkor Technology, Inc. | Semiconductor device including leadframe with downsets |
CN102725844B (zh) * | 2010-12-10 | 2016-03-30 | 松下知识产权经营株式会社 | 导电通路、使用该导电通路的半导体装置以及它们的制造方法 |
US8390130B1 (en) | 2011-01-06 | 2013-03-05 | Amkor Technology, Inc. | Through via recessed reveal structure and method |
JP5822468B2 (ja) | 2011-01-11 | 2015-11-24 | ローム株式会社 | 半導体装置 |
US8648450B1 (en) | 2011-01-27 | 2014-02-11 | Amkor Technology, Inc. | Semiconductor device including leadframe with a combination of leads and lands |
TWI557183B (zh) | 2015-12-16 | 2016-11-11 | 財團法人工業技術研究院 | 矽氧烷組成物、以及包含其之光電裝置 |
CN102986025B (zh) * | 2011-04-05 | 2015-04-22 | 松下电器产业株式会社 | 密封型半导体装置的制造方法 |
US8304871B2 (en) * | 2011-04-05 | 2012-11-06 | Texas Instruments Incorporated | Exposed die package for direct surface mounting |
JP5615757B2 (ja) * | 2011-04-06 | 2014-10-29 | 新電元工業株式会社 | 半導体装置、接続子、および、半導体装置の製造方法 |
US20190097524A1 (en) * | 2011-09-13 | 2019-03-28 | Fsp Technology Inc. | Circuit having snubber circuit in power supply device |
US20160277017A1 (en) * | 2011-09-13 | 2016-09-22 | Fsp Technology Inc. | Snubber circuit |
US8552548B1 (en) | 2011-11-29 | 2013-10-08 | Amkor Technology, Inc. | Conductive pad on protruding through electrode semiconductor device |
JP2013149779A (ja) * | 2012-01-19 | 2013-08-01 | Semiconductor Components Industries Llc | 半導体装置 |
US9704725B1 (en) | 2012-03-06 | 2017-07-11 | Amkor Technology, Inc. | Semiconductor device with leadframe configured to facilitate reduced burr formation |
US9129943B1 (en) | 2012-03-29 | 2015-09-08 | Amkor Technology, Inc. | Embedded component package and fabrication method |
US9048298B1 (en) | 2012-03-29 | 2015-06-02 | Amkor Technology, Inc. | Backside warpage control structure and fabrication method |
CN103367344B (zh) * | 2012-04-11 | 2016-04-27 | 光宝电子(广州)有限公司 | 连板料片、发光二极管封装品及发光二极管灯条 |
TWI488341B (zh) * | 2012-04-11 | 2015-06-11 | Lite On Electronics Guangzhou | 連板料片、發光二極體封裝品及發光二極體燈條 |
JP2014203861A (ja) * | 2013-04-02 | 2014-10-27 | 三菱電機株式会社 | 半導体装置および半導体モジュール |
KR101486790B1 (ko) | 2013-05-02 | 2015-01-28 | 앰코 테크놀로지 코리아 주식회사 | 강성보강부를 갖는 마이크로 리드프레임 |
KR101563911B1 (ko) | 2013-10-24 | 2015-10-28 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 |
JP2015142072A (ja) * | 2014-01-30 | 2015-08-03 | 株式会社東芝 | 半導体装置 |
US9673122B2 (en) | 2014-05-02 | 2017-06-06 | Amkor Technology, Inc. | Micro lead frame structure having reinforcing portions and method |
US9379193B2 (en) * | 2014-08-07 | 2016-06-28 | Semiconductor Components Industries, Llc | Semiconductor package for a lateral device and related methods |
CN110379718A (zh) * | 2014-10-24 | 2019-10-25 | 意法半导体股份有限公司 | 具有改进电可接入性的封装结构的电子装置和制造方法 |
DE102015104996B4 (de) * | 2015-03-31 | 2020-06-18 | Infineon Technologies Austria Ag | Halbleitervorrichtungen mit Steuer- und Lastleitungen von entgegengesetzter Richtung |
JP6394489B2 (ja) * | 2015-05-11 | 2018-09-26 | 株式会社デンソー | 半導体装置 |
US11056422B2 (en) * | 2018-05-29 | 2021-07-06 | Shindengen Electric Manufacturing Co., Ltd. | Semiconductor module |
US20210063099A1 (en) | 2019-08-28 | 2021-03-04 | Carbice Corporation | Flexible and conformable polymer-based heat sinks and methods of making and using thereof |
USD904322S1 (en) | 2019-08-28 | 2020-12-08 | Carbice Corporation | Flexible heat sink |
USD906269S1 (en) | 2019-08-28 | 2020-12-29 | Carbice Corporation | Flexible heat sink |
USD903610S1 (en) | 2019-08-28 | 2020-12-01 | Carbice Corporation | Flexible heat sink |
EP3790047B1 (en) * | 2019-09-05 | 2022-03-02 | Infineon Technologies AG | Multi-chip-package |
IT202000008269A1 (it) | 2020-04-17 | 2021-10-17 | St Microelectronics Srl | Dispositivo elettronico di potenza incapsulato impilabile per montaggio superficiale e disposizione circuitale |
NL2026503B1 (en) * | 2020-09-18 | 2022-05-23 | Ampleon Netherlands Bv | Molded RF power package |
US11908771B2 (en) * | 2021-11-12 | 2024-02-20 | Infineon Technologies Ag | Power semiconductor device with dual heat dissipation structures |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0206771B1 (en) * | 1985-06-20 | 1992-03-11 | Kabushiki Kaisha Toshiba | Packaged semiconductor device |
JPH02155256A (ja) * | 1988-12-08 | 1990-06-14 | Mitsubishi Electric Corp | 半導体装置 |
US5105259A (en) * | 1990-09-28 | 1992-04-14 | Motorola, Inc. | Thermally enhanced semiconductor device utilizing a vacuum to ultimately enhance thermal dissipation |
JPH05211250A (ja) * | 1992-01-30 | 1993-08-20 | Nec Corp | 樹脂封止型半導体装置 |
US5177669A (en) * | 1992-03-02 | 1993-01-05 | Motorola, Inc. | Molded ring integrated circuit package |
US5652461A (en) * | 1992-06-03 | 1997-07-29 | Seiko Epson Corporation | Semiconductor device with a convex heat sink |
US5598034A (en) * | 1992-07-22 | 1997-01-28 | Vlsi Packaging Corporation | Plastic packaging of microelectronic circuit devices |
US5485037A (en) * | 1993-04-12 | 1996-01-16 | Amkor Electronics, Inc. | Semiconductor device having a thermal dissipator and electromagnetic shielding |
JP3329073B2 (ja) * | 1993-06-04 | 2002-09-30 | セイコーエプソン株式会社 | 半導体装置およびその製造方法 |
US5625226A (en) * | 1994-09-19 | 1997-04-29 | International Rectifier Corporation | Surface mount package with improved heat transfer |
US5545921A (en) * | 1994-11-04 | 1996-08-13 | International Business Machines, Corporation | Personalized area leadframe coining or half etching for reduced mechanical stress at device edge |
JP3170182B2 (ja) * | 1995-08-15 | 2001-05-28 | 株式会社東芝 | 樹脂封止型半導体装置及びその製造方法 |
US6005286A (en) * | 1997-10-06 | 1999-12-21 | Micron Technology, Inc. | Increasing the gap between a lead frame and a semiconductor die |
KR100259080B1 (ko) * | 1998-02-11 | 2000-06-15 | 김영환 | 히트 스프레드를 갖는 리드 프레임 및 이를 이용한반도체 패키지 |
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WO2000074460A1 (en) | 2000-12-07 |
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AU5175200A (en) | 2000-12-18 |
US6256200B1 (en) | 2001-07-03 |
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