CN1348210A - 用选择性外延淀积制造应变硅cmos结构的方法 - Google Patents

用选择性外延淀积制造应变硅cmos结构的方法 Download PDF

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CN1348210A
CN1348210A CN01123081A CN01123081A CN1348210A CN 1348210 A CN1348210 A CN 1348210A CN 01123081 A CN01123081 A CN 01123081A CN 01123081 A CN01123081 A CN 01123081A CN 1348210 A CN1348210 A CN 1348210A
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K·里姆
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Abstract

制作了一种应变硅CMOS结构,其制作步骤包括:在衬底表面上制作SiGe弛豫层;在所述SiGe弛豫层中制作隔离区和阱注入区;以及在所述SiGe弛豫层上制作应变硅层。这些工艺步骤可以结合常规的栅工艺步骤用在应变MOSFET结构的制作过程中。

Description

用选择性外延淀积制造应 变硅CMOS结构的方法
发明的领域
本发明涉及到互补金属氧化物半导体(CMOS)器件的制造，确切地说是涉及到制作硅CMOS结构，其中在进行各个高温处理步骤之后以及在进行各个通常消耗硅的工艺步骤之后，制作结构的应变硅沟道层。
发明的背景
在半导体工业中，“SiGe CMOS上的应变Si”主要指的是在由外延生长在相对厚(大约300-20000)的SiGe弛豫层顶部上的相对薄(大约50-300)的应变Si层组成的衬底上制造的CMOS器件。过去的出版物已经表明了在应变Si层中获得高的电子和空穴迁移率的可能性。新近的出版物已经在实验上显示了应变硅能够被用作金属氧化物场效应晶体管(MOSFET)的沟道区，并已经表明，比之在常规硅衬底上制造的器件，器件的性能在这种结构中得到了增强。
实现应变硅CMOS工艺的困难之一是在制造过程中需要保护应变层免受高温处理步骤的影响。在高温处理步骤中暴露，通常使应变层中的应变发生驰豫。而且，典型用于阱制作的离子注入可能损伤应变硅层，使器件性质退化并减弱采用应变硅层所能够得到的性能增强。
而且，应变层越薄，应变层就能够承受越大的热应力而没有可觉察到的器件退化。然而，包括氧化和腐蚀(例如化学腐蚀和干法腐蚀)的各种处理步骤消耗顶部硅层；于是，在目前的应变CMOS器件的处理中，外延应变硅层必须足够厚，以便弥补氧化和/或腐蚀过程中可能发生的潜在厚度损失。
考虑到现有技术应变硅CMOS工艺的上述缺点，对于开发基本上消除现有技术各种问题的新的改进了的方法，一直存在着需求。亦即，需要一种提供应变硅CMOS器件的方法，其中在已经完成大部分高温CMOS处理步骤之后，以及在已经完成大部分消耗硅的处理步骤之后，制作应变硅层。这种方法可能提供比现有技术应变硅CMOS器件可能提供的性能更高的器件。
发明的概述
本发明的目的是提供一种应变硅CMOS器件，其中的应变硅层不受高温预定处理步骤的不利影响。
本发明的另一目的是提供一种应变硅CMOS器件，其中的应变硅层不被已知要消耗有源器件区中的硅的处理步骤消耗，从而尽可能减小应变硅层的所需厚度。
本发明的再一目的是提供能够与现有FET工艺步骤兼容的制造应变硅层的工艺步骤。
在本发明中，利用在已经完成大部分高温处理步骤之后以及在已经完成消耗硅的处理步骤之后制作应变硅层的本发明的方法，能够达到这些和其它的目的和优点。
具体地说，本发明的方法包含下列步骤：
(a)在衬底表面上制作SiGe弛豫层；
(b)在所述SiGe弛豫层上制作隔离区和阱注入区；以及
(c)在所述SiGe弛豫层上制作应变硅层。
在本发明的一个实施方案中，在进行上述步骤(b)之前，在SiGe驰豫层上制作一个可选的覆盖层。当存在覆盖层时，通常在制作应变硅层之前清除此覆盖层，并在原先被覆盖层占据的区域中制作应变硅层。
在本发明中，可以用选择性外延生长工艺来制作应变硅层，其中仅仅在被暴露的SiGe驰豫层区域中制作应变硅层。作为变通，在制作应变硅层过程中，可以采用非选择性外延工艺。若采用非选择性外延生长工艺，则应变硅层被制作在整个结构上，并用光刻和腐蚀方法来清除隔离区上的应变硅层。
上述的本发明工艺步骤可以结合包括栅介质制作、栅叠层制作、源/漏扩散注入等的能够在应变硅层上制作FET的常规栅工艺步骤使用。
附图的简要说明
图1-3示出了本发明的各个工艺步骤。
图4示出了能够结合常规栅制造工艺步骤用图1-3所示的本发明的基本工艺步骤制造的硅CMOS器件。
图5-8示出了本发明的一个变通实施方案，其中使用了覆盖层。
本发明的详细描述
以下参照本申请的附图来更详细地描述本发明。要指出的是，在附图中，相似的参考号被用来表示相似的和/或相应的元件。
首先参照图1-3，示出了本发明的基本工艺步骤。具体地说，图1示出了在进行本发明的步骤(a)之后，亦即在衬底10表面上制作SiGe弛豫层12之后制作的基本结构。利用能够在衬底上制作这种层的任何常规工艺，在衬底10表面上制作SiGe弛豫层。例如，可以用例如美国专利No.5158907所述的常规生长工艺、常规切克劳斯基拉晶工艺、或美国专利No.5847419所述的固相再生长外延，来制作SiGe弛豫层，此处将上述各个美国专利的内容列为参考。
SiGe弛豫层被制作在衬底上，这些衬底可以包括诸如Si、Ge、SiGe、GaAs、InAs、InP以及所有其它III-V族半导体之类的半导体材料，或作为变通，衬底可以由诸如Si/SiGe或绝缘体上硅(SOI)之类层状衬底组成。
要指出的是，用来制备SiGe弛豫层的方法或衬底的细节对本发明并不重要。但本发明的关键情况是最终将成为CMOS器件的沟道的应变硅层不出现在工艺的这一阶段。这是与现有技术工艺不同的，在现有技术工艺中，一般在这一阶段制作应变层。
在本发明的一个实施方案中(见图5-8)，可以在SiGe弛豫层顶部制作可选的覆盖层13。当采用覆盖层时，用诸如化学气相淀积(CVD)、等离子体辅助CVD、溅射、蒸发、甩涂之类的常规淀积工艺和其它相似的淀积工艺来制作。在本发明中，可以使用诸如介电膜或半导体层之类的能够用作保护层的任何材料。例如，可以用SiO2、Si3N4、SiGe、或Si作为覆盖层13。
图2(以及图6)示出了在结构中制作隔离区14和阱注入区16之后得到的结构。应该指出的是，虽然附图说明了结构中的沟槽隔离区的制作，但本发明完全可以具有本技术领域熟练人员众所周知的LOCOS(硅的局部氧化)隔离区或其它类似的隔离区。
用本技术众所周知的常规工艺技术来制作隔离区。在沟槽隔离区的情况下，如附图所示，借助于用常规光刻(光抗蚀剂曝光和显影)确定隔离区域的面积、用诸如反应离子刻蚀(RIE)、等离子体刻蚀、或离子束刻蚀之类的常规干法腐蚀工艺穿过图形化的光刻胶在结构中腐蚀沟槽、用诸如SiO2、Si3N4之类的常规沟槽衬垫材料可选地填充腐蚀的沟槽、用诸如SiO2的沟槽介电材料填充腐蚀的沟槽、以及若有需要再进行诸如化学机械抛光(CMP)或研磨之类的常规整平工艺，来制作隔离区。
要指出的是，在腐蚀沟槽之后，利用本技术领域熟练人员众所周知的任何常规剥离工艺，清除图形化的光抗蚀剂。当结构包括覆盖层时，沟槽被腐蚀穿过覆盖层进入SiGe弛豫层，并在其中制作隔离区，见图6。
通常，在制作隔离区之后，用本技术领域熟练人员众所周知的常规离子注入和激活退火工艺，在结构中形成包括p阱或n阱的阱注入16。离子剂量和注入剂能量可以根据待要注入的掺杂剂的类型以及阱注入剂的所希望的深度而变化。而且，本发明所用的激活退火温度和时间也可以变化。应该指出的是，无论离子注入还是退火条件，对本发明都不重要。
用本技术领域熟练人员众所周知的常规离子注入工艺，还可以形成阈值调整注入或所谓穿通注入(为清晰起见，图中未示出)。
要指出的是，在本发明的这一阶段，执行大部分高温预定工艺步骤和离子注入步骤。由于本工艺这一步骤时的结构不包括任何应变硅层，故应变层不受高温工艺或离子注入的不利影响。
当存在可选的覆盖层时，可以用常规干法或湿法化学腐蚀工艺来清除某些或全部覆盖层，或可以使用CMP(见图7，其中所有的覆盖层被清除)。如图7-8所示，这一步骤在其中可能制作应变硅层的结构中形成空腔17。
现在可以在图2或7所示的结构上进行常规湿法化学清洗步骤。并接着如图3(以及图8)所示，利用选择性外延(“epi”)工艺或非选择性epi工艺，在结构上制作应变硅层18。具体地说，在制作应变硅层的过程中，可以使用CVD或分子束外延。
本发明中优选的选择性外延工艺，仅仅在存在SiGe弛豫层的器件区域上生长应变硅层。用选择性外延工艺，在隔离区上不出现生长。能够在SiGe弛豫层上生长应变硅层的任何常规选择性外延工艺都可以在本发明中使用。
非选择性外延工艺在包括隔离区的结构的所有部分上形成应变硅层。当采用这种工艺时，在后续步骤中用常规光刻和腐蚀来清除生长在隔离区上的材料。
图4示出了能够用图1-3所示的工艺步骤结合能够在结构中形成栅区的常规工艺步骤制作的最终应变硅CMOS结构。具体地说，图4中的结构包括衬底10、SiGe弛豫层12、隔离区14、阱注入16、应变硅层18、栅介质20、栅导体22、侧壁间隔24、以及源/漏扩散区26。用图8所示的应变硅层状结构可以形成一种相似的结构。
要指出的是，图4所示的栅区是用本技术众所周知的常规栅制作工艺技术制作的。这包括通过淀积或热生长制作栅介质20、在栅介质上淀积栅导体22、用光刻和腐蚀对栅区进行图形化、用淀积和腐蚀方法形成间隔24、以及用离子注入和退火形成扩散区。由于这种栅制作工艺对本技术领域熟练人员来说是众所周知的，敌此处不对其进行详细描述。
栅区也由本技术领域熟练人员众所周知的常规材料组成。例如，栅介质20可以由SiO2、Al2O3、ZrO2或其它相似的氧化物组成，栅导体22可以由导电金属例如W、Pt、Co、或Ti；多晶硅；包括多晶硅和导电金属层的叠层；诸如WSix的金属硅化物；包括多晶硅和金属硅化物的叠层；或其它相似的导电材料组成。而间隔24由SiO2或SiN组成。也可以用诸如SiN的硬掩蔽材料覆盖栅导体。
虽然对于其优选实施方案已经具体地描述了本发明，但本技术领域的熟练人员可以理解，可以在形式和内容上作出上述和其它的改变而不偏离本发明的构思与范围。因此认为本发明不局限于所述的准确形式和细节，而是在所附权利要求的范围内。

Claims (12)

1.一种制造其中制作有应变硅层的CMOS结构的方法，所述方法包含下列步骤：
(a)在衬底表面上制作SiGe弛豫层；
(b)在所述SiGe弛豫层中制作隔离区和阱注入区；以及
(c)在所述SiGe弛豫层上制作应变硅层。
2.权利要求1的方法还包含，在进行步骤(b)之前，在所述SiGe驰豫层上制作覆盖层。
3.权利要求1的方法，其中用生长工艺、切克劳斯基拉晶工艺、或固相再生长外延，来制作所述SiGe弛豫层。
4.权利要求1的方法，其中所述衬底由Si、Ge、SiGe、GaAs、InAs、InP、Si/SiGe、或绝缘体上硅组成。
5.权利要求1的方法，其中所述隔离区是LOCOS区域的沟槽隔离区。
6.权利要求5的方法，其中所述隔离是沟槽隔离区，它的制作方法是：(i)将光抗蚀剂涂敷到所述SiGe驰豫层；(ii)对光抗蚀剂进行曝光和显影，以便在其中形成图形；(iii)穿过所述图形进行腐蚀，在所述SiGe驰豫层中形成沟槽；(iv)用介电材料填充所述沟槽；以及(v)整平。
7.权利要求1的方法，其中用离子注入和激活退火来形成所述阱注入。
8.权利要求1的方法，其中用选择性外延工艺或非选择性外延工艺来制作所述应变硅层。
9.权利要求1的方法，其中用化学气相淀积或分子束外延来制作所述应变硅层。
10.权利要求2的方法，其中在进行步骤(c)之前，清除所述覆盖层的一部分或全部，以便在所述隔离区之间形成空腔，从而形成所述应变硅层。
11.权利要求1的方法还包含其它的栅制作工艺步骤。
12.权利要求11的方法，其中所述其它的栅制作工艺步骤包括：(i)在所述应变硅层上制作栅介质；(ii)在所述栅介质上制作栅叠层；(iii)在所述栅叠层上制作侧壁间隔；以及(iv)在所述结构中制作源/漏扩散区。
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