CN1332471A - Method for manufacture of semiconductor device - Google Patents

Method for manufacture of semiconductor device Download PDF

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Publication number
CN1332471A
CN1332471A CN01122829A CN01122829A CN1332471A CN 1332471 A CN1332471 A CN 1332471A CN 01122829 A CN01122829 A CN 01122829A CN 01122829 A CN01122829 A CN 01122829A CN 1332471 A CN1332471 A CN 1332471A
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CN
China
Prior art keywords
semiconductor device
bonding sheet
mentioned
substrate
manufacture method
Prior art date
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Granted
Application number
CN01122829A
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Chinese (zh)
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CN1183585C (en
Inventor
池谷浩司
谷孝行
涩谷隆生
兵藤治雄
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Publication of CN1332471A publication Critical patent/CN1332471A/en
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Publication of CN1183585C publication Critical patent/CN1183585C/en
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Dicing (AREA)

Abstract

The present invention discloses a method for manufacturing semiconductor device to solve the problem that conventionally the workability deteriorates significantly, because individual semiconductor devices of micropackage are separated from a lead frame after transfer molding and handling becomes extremely difficult due to the discrimination of the surface and rear or the position of a lead at measurement or taping times. Therefore, the present invention is characterized in that a semiconductor chip is bonded to each mounting part of a substrate, having a plurality of mounting parts, each semiconductor chip bonded to each mounting part is coated with a common resin layer, the substrate is abutted against the resin layer and stuck to a viscous sheet, and then dicing and measurement are performed under such a state. Measurements can be performed in a state, where individual semiconductor devices are not separated but are supported integrally with the viscous sheet.

Description

The manufacture method of semiconductor device
Technical field
The present invention relates to the manufacture method of semiconductor device, particularly relate to and spending lead-in wire and dwindle packaging appearance and reduce erection space, the manufacture method of the semiconductor device that can reduce cost significantly.
Background technology
In the manufacturing of semiconductor device, carry out following technology, from the wafer cutting and separating semiconductor chip be fixed on the lead frame, inject the transfer modling that carries out by mould and resin the semiconductor chip sealing that is fixed on the lead frame, sealed semiconductor chip separation is semiconductor device one by one.This lead frame uses the frame of rectangle or annular, all is being to seal a plurality of semiconductor device in once sealing technology simultaneously under each situation.
Figure 12 illustrates transfer modling technology.In transfer modling technology, bonding by mold, the be adhesively fixed lead frame 2 of semiconductor chip 1 of line is arranged on the inside of the cavity 4 that is formed by mould 3A, 3B up and down, by injection ring epoxy resins in cavity 4, carries out the sealing of semiconductor chip 1.After such transfer modling technology, lead frame 2 is cut off according to each semiconductor chip 1, make independent semiconductor device (for example the spy opens flat 05-129473 number).
At this moment, as shown in figure 13, a plurality of cavity 4a～4f are set, are used to import the resin source 5 of resin, runner gate 6 and the cast gate 7 that is used for flowing into to each cavity 4a～4f resin from runner gate 6 on the surface of mould 3B.These all are arranged on the lip-deep groove of mould 3B.If rectangular lead frame then for example carries 10 semiconductor chips 1 on a lead frame,, 10 cavitys 4 and 10 cast gates 7 and 1 runner gate 6 are set corresponding to a lead frame.And, on mould 3 surfaces, for example be provided with and 20 cavitys 4 that lead frame is suitable.
Figure 14 illustrates the semiconductor device of making by above-mentioned transfer modling.The semiconductor chip 1 that has formed elements such as transistor is fixedly mounted by scolders such as scolding tin 9 on the island 8 of lead frame, connects the electrode pad and lead-in wire 10 of semiconductor chips 1 with line 11.The peripheral part of semiconductor chip 1 is covered by the resin consistent with above-mentioned cavity shape 12, derives the fore-end of lead terminal 10 in the outside of resin 12.
In encapsulation in the past, because the outside lead terminal 10 that connects usefulness is given prominence to from resin 12, therefore must consider erection space to lead terminal 10 to the distance of head portion, exist erection space much larger than the such shortcoming of the overall dimension of resin 12.
In addition, in transfer modling technology in the past, owing to harden continue adding under the pressure status, therefore hardening of resin in runner gate 6 and cast gate 7, the resin that remains in these runner gate 6 grades becomes the waste treatment part.Therefore, state in the use in the method for lead frame, owing in each of the semiconductor device that will make cast gate 7 is set, the utilization ratio that therefore exists resin is poor, the so less shortcoming of number of the semiconductor device that can make with respect to the quantity of resin.
And then, be separated into the independent semiconductor device of small encapsulation after the transfer modling from lead frame, therefore exist the judgement of positive and negative when measuring or tying up or lead-in wire position etc. and extremely be difficult to handle, operation worsens such shortcoming significantly.
Summary of the invention
The present invention produces in view of above problem, and its purpose is to provide a kind of and saves material, dwindles erection space, reduces cost and also can improve the manufacture method of the semiconductor device of operating efficiency.
The invention is characterized on partly each of this lift-launchs fixedly semiconductor chip with a plurality of substrates that carry part, with common resin bed carrying after above-mentioned each each of above-mentioned semiconductor chip of carrying part has covered, aforesaid substrate and above-mentioned resin bed overlap joint is sticked on the bonding sheet, under the state that sticks on the above-mentioned bonding sheet, cut and measure, be not separated into independent semiconductor device thus and under the state that is supported for one with bonding sheet, measure.
In addition, in the present invention, be characterised in that on partly each of this lift-launchs fixedly semiconductor chip with a plurality of substrates that carry part, with common resin bed being fixed on after above-mentioned each each of above-mentioned semiconductor chip of carrying part covered, aforesaid substrate and above-mentioned resin bed overlap joint is sticked on the bonding sheet, cut and measure sticking under the state of above-mentioned bonding sheet, and then, directly be housed in carrying and be with sticking on semiconductor device on the above-mentioned bonding sheet, can not carry out operation under the one state up to being housed in carrying being supported for not being separated into independent semiconductor device before going up thus with bonding sheet.
Description of drawings
Fig. 1 is the perspective view that is used to illustrate manufacture method of the present invention.
Fig. 2 is (A) plane graph (B) profile that is used to illustrate manufacture method of the present invention.
Fig. 3 is the plane graph that is used to illustrate manufacture method of the present invention.
Fig. 4 is the profile that is used to illustrate manufacture method of the present invention.
Fig. 5 is (A) profile (B) plane graph that is used to illustrate manufacture method of the present invention.
Fig. 6 is (A) profile (B) plane graph that is used to illustrate manufacture method of the present invention.
Fig. 7 is (A) profile (B) plane graph that is used to illustrate manufacture method of the present invention.
Fig. 8 is (A) profile (B) plane graph that is used to illustrate manufacture method of the present invention.
Fig. 9 is (A) profile (B) plane graph that is used to illustrate manufacture method of the present invention.
Figure 10 is (A) plane graph (B) profile (C) profile that is used to illustrate manufacture method of the present invention.
Figure 11 is (A) perspective view (B) perspective view that is used to illustrate manufacture method of the present invention
Figure 12 is used to illustrate the profile of example in the past.
Figure 13 is used to illustrate the plane graph of example in the past.
Figure 14 is used to illustrate the profile of example in the past.
The embodiment of invention
Below explain example of the present invention.
The 1st technology of the present invention prepares to have a plurality of substrates that carry part as extremely shown in Figure 3 from Fig. 1.
At first, as shown in Figure 1, prepare to have arranged a plurality of lift-launch parts 20 corresponding to 1 semiconductor device, for example, arranged 100 bulk substrate 21 in length and breadth with 10 row, 10 row.Substrate 21 is insulated substrates of being made by pottery or glass epoxide etc., and they are piled up a slice or multi-disc, has to amount to the thickness of slab that thickness of slab 200～350 μ m can keep the mechanical strength in the manufacturing process.
Carry on the surface of part 20 at each of substrate 21, form the conductive pattern that the printing of metal-to-metal adhesives such as tungsten and the plating by gold form.In addition, in the back side of substrate 21 side, form electrode pattern as external connecting electrode.
Fig. 2 (A) is the plane graph that the conductive pattern on the surface that is formed on substrate 21 is shown, and Fig. 2 (B) is the profile of substrate 21.
Each lift-launch part 20 that with dashed lines surrounds for example has the rectangular shape of long limit * minor face 1.0mm * 0.8mm, and they are spaced from each other the interval of 20～50 μ m and arrange in length and breadth.Above-mentioned interval becomes the line of cut 24 in the aftermentioned technology.Conductive pattern forms island shape part 25 and lead portion 26 in each carries part 20, these figures are identical shaped in each carries part 20.Island shape part 25 is the positions of carrying semiconductor chip, and lead portion 26 is the positions that are connected with the electrode pad line of semiconductor chip.Prolong with the figure that 2 article of the 1st coupling part 27 connected from island shape part 25.Their live width is narrower than island shape part 25, for example prolongs with the 0.1mm live width.The 1st coupling part 27 strides across line of cut 24 and is connected with the lead portion 26 of adjacent lift-launch part 20.And then, extend from lead portion 26 each the 2nd coupling parts 28 along the direction vertical with the 1st coupling part 27, stride across line of cut 24 and be connected with the lead portion 26 of adjacent lift-launch part 20.The common coupling part 29 on every side of carrying 20 groups of parts is surrounded in the 2nd coupling part 28 and then connection.Extend by the 1st and the 2nd coupling part 27,28 like this, each island shape part 25 of carrying part 20 is electrically coupled together jointly with lead portion 26.This be for carry out gold etc. when electroplating as common electrode.
With reference to Fig. 2 (B), on insulated substrate 21, in each lift-launch part 20, through hole 30 is set.The inside of through hole 30 is buried electric conducting materials such as tungsten underground.And corresponding to each through hole 30, a side forms outer electrode 31 overleaf.
The plane graph of the figure of outer electrode 31a～31d when Fig. 3 shows from the back side one side observation substrate 21.These outer electrodes 31a, 31b, 31c, 31d retreat about 0.05～0.1mm from the edge that carries part 20, and with independently figure formation separately.However, on electric, be connected to common coupling part 29 through each through hole 30.Thus, in the galvanoplastic of conductive pattern, can on all conductive patterns, form Gold plated Layer as an electrode.In addition, intersection secant 24 can only make the 1st and the 2nd coupling part 27,28 of line width.
The 2nd technology of the present invention as shown in Figure 4, be carry part each on fixing semiconductor chip, carry out line and connect.
Each of substrate 21 that has formed Gold plated Layer carries part 20, and it is bonding or mold is bonding that semiconductor chip 33 is carried out line.Semiconductor chip 33 by adhesive securement such as Ag glue, connects the electrode pad and the lead portion 32a of semiconductor chips 33,32b with each bar line 34 on the surface of island shape part 25.As semiconductor chip 33, form bipolar transistor, the active element of 3 terminals such as power MOSFET.Carried under the situation of ambipolar element, be connected the outer electrode 31a of island shape part 25,31b is a collector terminal, is connected the outer electrode 31c of lead portion 26, and 31d becomes the Base-Emitter electrode.
Secondly, the 3rd technology of the present invention with resin bed covered substrate surface, covers each that is fixed on each semiconductor chip that carries part as shown in Figure 5 with common resin bed.
Shown in Fig. 5 (A), from the dispenser (not shown) that the moves to substrate 21 tops a certain amount of epoxy series liquid resin (cast encapsulation) that drips, with all semiconductor chips 33 of common resin bed 35 coverings.For example, carrying on the plate base 21 under the situation of 100 semiconductor chips 33,100 all semiconductor chips 33 are being covered together.As the aforesaid liquid resin, use for example CV576AN (SUNX system).The dripping resin has surface tension because ratio of viscosities is higher, so its surface curvature.
Then, shown in Fig. 5 (B), by 100～200 ℃, the heat treatment of a few hours (thermalization) makes after its sclerosis, is the Surface Machining of resin bed 35 tabular surface by the grinding flexure plane the resin bed 35 that drips.Cutter sweep is used in grinding, the surface of resin bed 35 is evened up and is exceeded certain height from substrate 21 by the surface of cutting blade 36 cutting resin beds 35.In this technology, the thickness of resin bed 35 is formed 0.3～1.0mm.Tabular surface is expanded to its end, makes at least when being positioned at outermost semiconductor chip 33 and being separated into independent semiconductor device, can constitute the resin profile of standardized package dimension.Prepare the blade of multiple thickness of slab in the above-mentioned blade, use thicker blade, by cutting repeatedly, the overall tabular surface that forms.
In addition, also can consider before the resin bed 35 that drips is hardened, to push the face that smooth moulding material forms smooth and level on the surface of resin bed 35, the method for hardening then.
Secondly, the 4th technology of the present invention snaps on the substrate 21 resin bed 35 as shown in Figure 6, pastes bonding sheet 50.
Shown in Fig. 6 (A),, on the surface of resin bed 35, paste bonding sheet 50 (for example, trade name: UV sheet, リ Application テ Star Network Co., Ltd. system) substrate 21 counter-rotatings.By becoming resin bed 35 Surface Machining smooth in the technology in front and being the face of level for the surface of substrate 21, even therefore stick on resin bed 35 1 sides substrate 21 is not tilted, keep the precision of its horizontal vertical.
Shown in Fig. 6 (B), on the system endless metal frame 51 that goes to go between, paste the periphery of bonding sheet 50, be provided with at the middle body of bonding sheet 50 and paste 6 substrates 21 at interval.
Secondly, the 5th technology of the present invention from the back side one side of substrate, is carried part at each as shown in Figure 7, and cutting substrate and resin bed are separated into semiconductor device one by one.
Shown in Fig. 7 (A), be separated into each semiconductor device at each overlap 20 cut-out substrate and resin bed 35.The cutting blade 36 of cutter sweep is used in cutting, along line of cut 24 cutting resin layer 35 and substrate 21 simultaneously, carries part 20 at each thus and forms the semiconductor device of having cut apart.Above-mentioned cutting blade 36 cuts with the cutting depth on the surface that reaches bonding sheet 50 in cutting technique.At this moment, the mark that can observe from the back side automatic identification of one side of substrate 21 in cutter sweep one side (for example, being formed on the through hole of peripheral part of substrate 21 or the part of Gold plated Layer) cuts as benchmark with it.In addition, electrode pattern 31a, 31b, 31c, 31d or island shape part 25 adopt the graphic designs that does not contact cutting blade 36.Its objective is because the cuttability of Gold plated Layer is poor, thereby prevent to produce the Gold plated Layer burr as far as possible.Thereby the part that cutting blade 36 contacts with Gold plated Layer only is to be the 1st and the 2nd coupling part 27,28 of control purpose with the conduction.
Shown in Fig. 7 (B), periphery sticks on the multi-piece substrate 21 pasted on the bonding sheet 50 on the metal frame 51 according to each sheet identification line of cut 24, separate with cutter sweep each bar line of cut 24, then metal frame 51 is revolved each the bar line of cut 24 that turn 90 degrees along line direction and separate along longitudinal direction.Paste on the bonding sheet 50 with its original state by each semiconductor device by using bonding agent that cuts separated, rather than separated dispersedly by single.
Secondly, the present invention's the 6th technology carries out being supported on integratedly the mensuration of each semiconductor device characteristic on the bonding sheet 50 as shown in Figure 8.
Shown in Fig. 8 (A), the pin 52 of contact probe on the outer electrode 31a～31d that is exposed to the back side one side from the substrate 21 that is supported on each semiconductor device on the bonding sheet 50 integratedly, the characterisitic parameter of single each semiconductor device of mensuration carries out good and bad judgement, marks with magnetic ink on defective products.
Shown in Fig. 8 (B), on metal frame 51, pasting multi-piece substrate 21, owing to single semiconductor device in the state lower support of cutting technique,, just can extremely easily carry out in large quantities therefore by metal frame 51 is only sent 1 size of semiconductor device along longitudinal direction and transverse direction.That is, can not need the judgement of semiconductor device positive and negative and the emitter of outer electrode, base stage, the judgement of the classification of collector electrode etc.
And then the 7th technology of the present invention directly is housed in carrying and is with on 41 being supported on each semiconductor device 40 on the bonding sheet 50 integratedly as shown in Figure 9.
Shown in Fig. 9 (A), be supported on each semiconductor device 40 that the test on the bonding sheet 50 finishes integratedly and only discern good product, break away from from bonding sheet 50 by absorption collet chuck 53 and accommodate carrying with in 41 the accepting hole.
Shown in Fig. 9 (B), owing on metal frame 51, pasting multi-piece substrate 21, the single semiconductor device 40 of state lower support in cutting, therefore when accommodating with 41, carrying can make metal frame 51 only move to the position of needed semiconductor device 40, can carry out with needed minimal action, therefore can extremely easily and in large quantities carry out.
Figure 10 is illustrated in (A) plane graph (B) AA line profile (C) BB line profile of the carrying band that uses in this technology.Band body 41 is thickness 0.5～1.0mm, and width 6～15mm, the parts of the band shape of the tens of m of length, material are the such paper of corrugated board.On band body 41, wear through hole 42 with certain interval.In addition, be formed for sending hole 43 to what band body 41 was sent at certain interval.This through hole 42 and send hole 43 to and be processed to form by die stamping.The thickness of band body 41 and through hole 42 be dimensioned to the size that can accommodate the electronic unit 40 that will tie up.
In the back side of band body 41 side, paste the bottom of the 1st band 44 and the filling through hole 42 of transparent membrane shape.In the surface of band body 41 side, paste the top of the 2nd band 45 and the filling through hole 43 of transparent membrane shape equally.The 2nd band 45 is pasted with near adhesive portion the lateral parts 46 and band body 41.In addition, the 1st band 44 is also pasted in position identical with the 2nd band 45 and band body 41.These are pasted from film top by carrying out with the heater block hot pressing that has corresponding to the heating part of adhesive portion 46, and this is the stickup under the state that can peel off by both's drawing film.
At last, Figure 11 is the perspective view that each semiconductor device of finishing according to above-mentioned technology is shown.4 sides are formed by the section of resin bed 35 and substrate 21 around encapsulation, and the surface of the top resin bed 35 by planarization of encapsulation forms, and the following back side one side by insulated substrate 21 of encapsulation forms.
The length of this semiconductor device * wide * height has for example such size of 1.0mm * 0.6mm * 0.5mm.On substrate 21, cover resin bed 35 sealing semiconductor chips 33 about 0.5mm.Semiconductor chip 33 has the thickness about about 150 μ m.Island shape part 25 retreats with the end face of lead portion 26 from encapsulation, and only the cut-off parts of the 1st and the 2nd coupling part 27,28 is exposed to package side surface.
Outer electrode 31a～31d is at 4 angles of substrate 21, with the big minispread about 0.2 * 0.3mm, for the center line of packaging appearance with (up and down) relative pattern arrangement about becoming.This symmetric arrays is owing to be difficult to carry out the polarity judgement of electrode, and therefore preferably at formation of the surface of resin bed 35 side or printing recess etc., the mark of polarity is represented in mint-mark.
Therefore the semiconductor device that is formed by above-mentioned manufacture method compares with the situation of encapsulation one by one owing to compile a plurality of element resin-encapsulated, can reduce useless resin material, the reduction fee of material.In addition,, therefore compare, can reduce packaging appearance significantly with transfer modling method in the past owing to do not use lead frame.And then, because the outside terminal that connects usefulness is formed on the back side of substrate 21, and not outstanding from packaging appearance, therefore can reduce the Unit Installation area significantly.
And then above-mentioned manufacture method is not in substrate 21 1 sides but pastes bonding sheet 50 in resin bed 35 1 sides and cut.For example stick under the situation of substrate 21 1 sides, the bonding agent of bonding sheet 50 is attached to the surface of electrode pattern 31a～31d when scraper element.If under the residual state of this bonding agent, element is put in the automatic installation apparatus, then has the danger of the welding characteristic deterioration that makes the electrode pattern 31a～31d when installing.In addition, also has danger at electrode pattern 31a～31d surface adhesion dust.And if, can eliminate these drawbacks by sticking on resin bed 35 1 sides according to the present invention.
And then, when resin bed 35 1 sides are pasted bonding sheet 50,, can keep and vertical-horizontal precision identical when substrate 21 1 sides are pasted bonding sheet 50 by the Surface Machining of resin bed 35 being become level and smooth face.
In addition, illustrated in the above-described embodiments to seal the example that 3 terminal components form 4 outer electrodes, and for example under the situation of 2 semiconductor chips of sealing or sealing integrated circuit, can have been implemented too.
The invention effect
If according to the present invention, then the 1st, because after having covered with resin bed, peripheral Stick on the bonding sheet on the metal frame and paste after the multi-piece substrate, can under its state, carry out From cutting technique and measure technology, although therefore can realize be small packaging structure but still So be rich in the manufacture method of the semiconductor devices of mass production.
The 2nd, because a plurality of substrates of on the sticking tablet that periphery is sticked on metal frame, pasting State under directly carry out to the accommodating of carrying belt, even therefore each semiconductor devices is small Encapsulation also can be carried out processing under the substrate state, can realize extremely being rich in mass production The manufacture method of semiconductor devices.
The 3rd, use tree by the semiconductor devices that above-mentioned manufacture method forms owing to compile a plurality of elements Fat encapsulates, and therefore compares with situation about encapsulating one by one, can reduce useless Resin material reduces fee of material. In addition, owing to do not use lead frame, therefore with in the past biography Pass molding methods relatively, can reduce significantly packaging appearance. And then, owing to the back of the body at substrate Face forms the outside terminal that connects usefulness, and the profile from encapsulation is not outstanding, therefore can be significantly Reduce the erection space of device. Thereby can provide the product that has taken into full account environment.
The 4th, if according to the present invention then, therefore can realize not needing the transfer modling device owing to do not use lead frame, and then the production line of the such saving resource-type of the mould of each the encapsulation shape that need in this device, not use.
The 5th, since from cutting technique to measuring technology, tying up technology and can handle with the bonding sheet that is fixed on the metal frame, therefore in manufacturing during this period employed anchor clamps class only metal frame just can satisfy, can realize the shortening of production line, and can carry out continuously tying up by enough manufacturing installations from cutting to.

Claims (6)

1. the manufacture method of a semiconductor device is characterized in that:
Fixing semiconductor chip on partly each of this lift-launchs with a plurality of substrates that carry part, with common resin bed being fixed on after above-mentioned each each of above-mentioned semiconductor chip of carrying part covers, aforesaid substrate and above-mentioned resin bed overlap joint is sticked on the bonding sheet, under the state that sticks on the above-mentioned bonding sheet, cut and measure.
2. the manufacture method of the semiconductor device described in claim 1 is characterized in that:
Above-mentioned bonding sheet is fixed on periphery on the metal frame.
3. the manufacture method of the semiconductor device described in claim 2 is characterized in that:
On above-mentioned bonding sheet, paste a plurality of aforesaid substrates.
4. the manufacture method of a semiconductor device is characterized in that:
Fixing semiconductor chip on partly each of this lift-launchs with a plurality of substrates that carry part, with common resin bed being fixed on after above-mentioned each each of above-mentioned semiconductor chip of carrying part covers, aforesaid substrate and above-mentioned resin bed overlap joint is sticked on the bonding sheet, under the state that sticks on the above-mentioned bonding sheet, cut and measure, and then the semiconductor element that sticks on the above-mentioned bonding sheet directly is housed in the carrying band.
5. the manufacture method of the semiconductor device described in claim 4 is characterized in that:
Above-mentioned bonding sheet is fixed on periphery on the metal frame.
6. the manufacture method of the semiconductor device described in claim 5 is characterized in that:
On above-mentioned bonding sheet, pasting a plurality of aforesaid substrates.
CNB011228296A 2000-07-07 2001-07-09 Method for manufacture of semiconductor device Expired - Lifetime CN1183585C (en)

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US6737285B2 (en) 2004-05-18
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JP2002026182A (en) 2002-01-25
KR20020005461A (en) 2002-01-17
US20020004250A1 (en) 2002-01-10

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