CN1330135C - Detector - Google Patents
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- CN1330135C CN1330135C CNB2004100623282A CN200410062328A CN1330135C CN 1330135 C CN1330135 C CN 1330135C CN B2004100623282 A CNB2004100623282 A CN B2004100623282A CN 200410062328 A CN200410062328 A CN 200410062328A CN 1330135 C CN1330135 C CN 1330135C
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Abstract
The present invention provides a testing device for testing interconnecting mezzanine card interfaces of peripheral devices in tested devices. The testing device comprises interconnecting mezzanine cards of peripheral devices and detecting units; the interconnecting mezzanine cards of peripheral devices further comprise interface units, converting units and loop back units, wherein the interface units are connected with the interconnecting mezzanine cards of peripheral devices for transmitting testing data; the converting units are connected with the interface units for transmitting the testing data and/or for converting the transmitting format of the testing data; the loop back units are connected with the converting units for transmitting the input testing data out and have a loop back function.
Description
Technical field
The present invention relates to the measuring technology of the electronics or the communications field, refer to be applied to a kind of testing apparatus of peripheral device interconnection interlayer card interface especially.
Background technology
Peripheral device interconnection (PCI, Peripheral Component Interface) be a kind of bus specification, PCI interlayer card (PMC, PCI Mezzanine Card) is a kind of international norm, all provide the PMC interface on a lot of system boards, have the equipment of PMC interface with connection.For example on close-coupled PCI (CPCI, Compact PCI) platform, just provide the PMC interface.The CPCI platform comprises the backboard of various parts or equipment, the veneer of CPCI platform and the various parts and the equipment of grafting of pegging graft that is used for.The veneer of described CPCI platform is plugged on the front of described backboard; Various parts and equipment for described grafting, be plugged on the front or the back of described backboard as the case may be, the parts or the equipment that will be plugged on described backboard front usually are called front card, and the parts or the equipment that will be plugged on described backboard back are called back card/back board.
As shown in Figure 1, standard P MC interface on the veneer of CPCI platform comprises edge connector JN1, JN2, JN3 and the JN4 of four 64 pins, wherein, two edge connector JN1 and JN2 are low 32 pci bus interfaces, another edge connector JN3 links to each other by 64 pci buss of these three edge connector interfaces with the veneer of CPCI platform for high 32 pci bus interfaces of expansion; Last edge connector JN 4 is self defined interfaces, and this interface links to each other with the back card/back board of CPCI platform by the backboard of CPCI.
Because the PMC interface can be used for connecting the device or the equipment of the various PMC of having interfaces, so the quality of PMC interface directly has influence on the performance of the equipment that connects by the PMC interface, therefore, need test the PMC interface, the testing apparatus that is used to test the PMC interface of prior art, the PMC card 8 of Ethernet (FE) interface for example, as shown in Figure 2, this PMC card 8 comprises medium access control (MAC, Medium Access Control) chip 5, internal interface 6 and the physical chip 7 of only supporting 32.
When the PMC interface on the veneer that uses 8 pairs of CPCI platforms of described PMC card detects, two edge connector JN1 that low 32 pci bus interfaces are provided of the PMC interface on the veneer of MAC chip 5 and CPCI platform are linked to each other with JN2, and physical chip 7 links to each other with the self defined interface (edge connector JN4) of PMC interface.
Because 5 of MAC chips are supported low 32,, promptly do not cover, so can't test to high 32 pci bus interfaces so high 32 pci bus interfaces (edge connector JN3) of PMC interface are not used.
In addition, 7 of physical chips have used four pins, promptly can only test, and can't test all pins of the self defined interface (edge connector JN4) of standard P MC interface to four pins of the self defined interface (edge connector JN4) of PMC interface.
For other PMC card, the pin of the self defined interface (edge connector JN4) of the PMC interface that some can be tested than the PMC card of FE interface is more, but can't realize that also all pins of the self defined interface (edge connector JN4) to the PMC interface test.
Summary of the invention
The problem to be solved in the present invention provides a kind of testing apparatus that can test all peripheral device interconnection bus interface of peripheral device interconnection interlayer card interface.
In order to address the above problem, the invention provides following technical scheme:
A kind of testing apparatus is used for the peripheral device interconnection interlayer card interface of test setting on equipment under test, and this testing apparatus comprises peripheral device interconnection interlayer card and detecting unit,
Described peripheral device interconnection interlayer card further comprises interface unit, converting unit and loopback unit, wherein,
Described interface unit links to each other with the peripheral device interconnection interlayer card interface of described equipment under test, is used for transmitting test data;
Described converting unit links to each other with described interface unit, is used to transmit test data and/or conversion testing data transmission format;
Described loopback unit links to each other with described converting unit, and the test data that is used for receiving from described converting unit is back to this converting unit through described internal bus;
Described detecting unit, place on the described equipment under test, be used for tested pin at peripheral device interconnection interlayer card interface, send the peripheral device interconnection interlayer card interface of test data, return test data, judge whether the test data that sends equates with the test data of returning and draw test result via interface unit, converting unit and loopback unit to described equipment under test.
Described peripheral device interconnection interlayer card interface has self defined interface, and described loopback unit comprises logic control element and cooperate card, wherein,
Described cooperation card is used for the test data that loopback sends to self defined interface, has self defined interface and the self defined interface of the peripheral device interconnection interlayer card interface of the described equipment under test of directly pegging graft;
Described logic control element, one end links to each other with described converting unit, the other end links to each other with the self defined interface of described interface unit, is used for test data is passed to the self defined interface of described equipment under test and will return to described detecting unit through the test data that described cooperation snap ring returns.
Described logic control element comprises control module, input register and output register, wherein,
Described output register is used to deposit the test data that described detecting unit sends;
Described input register is used to deposit the test data of returning through described cooperation snap ring;
Described control module is used for test data that described detecting unit is sent and outputs to described interface module and read the test data of described input register and it is turned back to described detecting unit through described output register.
Described peripheral device interconnection interlayer card interface has power interface, and the testing apparatus of described peripheral device interconnection interlayer card interface comprises power supply detecting unit and power logic control unit, described power logic control unit comprises status register and energy supply control module, wherein
Described energy supply control module is used to read the power interface state of the peripheral device interconnection interlayer card interface of described equipment under test;
Described status register is used to deposit the power interface state that described energy supply control module reads;
Described power supply detecting unit places on the equipment under test, the value that is used to drive described energy supply control module and reads described status register.
Described peripheral device interconnection interlayer card also comprises voltage conversion unit, and the voltage that being used to change described peripheral device interconnection interlayer card provides makes it to be complementary with the operating voltage of the building block of described peripheral device interconnection interlayer card.
Described peripheral device interconnection interlayer card also comprises clock circuit, is used to described peripheral device interconnection interlayer card that clock signal is provided.
Described converting unit links to each other with described interface unit by external bus, and described loopback unit links to each other with described converting unit by internal bus.
Compared with prior art, the beneficial effect of a kind of testing apparatus of the present invention:
The unit of inspecting of peripheral device interconnection interlayer card interface of the present invention can be at the tested pin of peripheral device interconnection interlayer card interface, send the peripheral device interconnection interlayer card interface of test data to described equipment under test, via interface unit, converting unit and loopback unit return test data, whether the test data that judge to send equates with the test data of returning and draw test result, can test all peripheral device interconnection bus interface of described peripheral device interconnection interlayer card interface;
Further, the described loopback unit of peripheral device interconnection interlayer card interface of the present invention comprises logic control element and cooperates card, described detecting unit sends test data to described logic control element, to cooperate snap ring to return, and can test all self defined interfaces of described peripheral device interconnection interlayer card interface;
Further, peripheral device interconnection interlayer card interface of the present invention comprises power supply detecting unit and power logic control unit, the power logic control unit comprises energy supply control module and status register, described power supply detecting unit triggers described energy supply control module knows its power supply status from the power interface of the peripheral device interconnection interlayer card interface of equipment under test, and power supply status left in the status register, then, the power supply detecting unit is from status register reads power taking source state, and whether the power interface of peripheral device interconnection interlayer card interface that can detect equipment under test is normal.
Description of drawings
Fig. 1 is the front elevation of PMC interface;
Fig. 2 is the structure chart of the testing apparatus of prior art peripheral device interconnection interlayer card interface;
Fig. 3 is the structure chart of a kind of testing apparatus of the present invention;
Fig. 4 is that the special-purpose peripheral device interconnection interlayer card of a kind of testing apparatus of the present invention concerns with cooperating the position that is stuck among the embodiment;
Fig. 5 is the structure chart of the logic control unit among Fig. 3.
Embodiment
As shown in Figure 1, the PMC interface comprises two edge connector JN1 and JN2, another edge connector JN3 that high 32 bus interface are provided that low 32 pci bus interfaces are provided, the 4th the edge connector JN4 and the power interface (in JN1 and JN2) of self defined interface is provided.
As shown in Figure 3, a kind of testing apparatus of the present invention is used for the PMC interface of test setting on equipment under test 200, comprises PMC9 and detecting unit 10,
Described interface unit 120 links to each other with the PMC interface (JN1, JN2, JN3 and JN4) of described equipment under test 200, is used for transmitting test data;
Described converting unit 16 links to each other with described interface unit 120 by external bus 21, is used to transmit test data and/or conversion testing data transmission format;
Described loopback unit 17 links to each other with described converting unit 16 by internal bus 22, and the test data that is used for receiving from described converting unit is back to this converting unit through described internal bus, has loop fuction;
Described detecting unit, place on the described equipment under test 200, be used for tested pin at the PMC interface, send the PMC interface of test data, return test data, judge whether the test data that sends equates with the test data of returning and draw test result via interface unit 120, converting unit 16 and loopback unit 17 to described equipment under test 200.
Further, described PMC interface has self defined interface JN4, and described loopback unit 18 comprises logic control element 170 and cooperate card 180, wherein,
Described cooperation card 180 is used for the test data that loopback sends to self defined interface, has self defined interface and the self defined interface JN4 of the PMC interface of the described equipment under test 200 of directly pegging graft;
Described logic control element 170, one end links to each other with described converting unit 16, the other end links to each other with the self defined interface JN15 of described interface unit 120, is used for test data is passed to the self defined interface JN3 of described equipment under test 200 and will return to described detecting unit 10 through the test data that described cooperation blocks 180 loopbacks.
Described logic control element 170 comprises control module 25, input register 23 and output register 24, wherein,
Described output register 24 is used to deposit the test data that described detecting unit 10 sends;
Described input register 23 is used to deposit the test data of blocking 180 loopbacks through described cooperation;
Described control module 25 is used for test data that described detecting unit 10 is sent and outputs to the self defined interface JN15 of described interface module 120 and read the test data of described input register 23 and it is turned back to described detecting unit 10 through described output register 24.
Described PMC interface has power interface (in JN1 and JN2), and the testing apparatus of described PMC interface comprises power supply detecting unit 30 and power logic control unit 20, described power logic control unit 20 comprises status register 28 and energy supply control module 29, wherein
Described energy supply control module 29 is used to read power interface (not marking) state of the peripheral device interconnection interlayer card interface of described equipment under test 200;
Described status register 28 is used to deposit the power interface state that described energy supply control module 29 reads;
Described power supply detecting unit 30 places on the equipment under test, the value that is used to drive described energy supply control module 29 and reads described status register 28.
Described PMC9 also comprises voltage conversion unit 26, and the voltage that being used to change described PMC9 provides makes it to be complementary with the operating voltage of the building block of described PMC9.
Described PMC9 also comprises clock circuit 27, is used to described PMC9 that clock signal is provided.
PMC interface with the veneer 200 of test CPCI platform is the technical scheme that example describes a kind of testing apparatus of the present invention in detail below.
As shown in Figure 3, the external bus 21 of the PMC9 in this example adopts 64 pci buss, and internal bus 22 adopts 32 pci buss.
The interface unit 120 of special-purpose PMC9 in this example adopts four the 64 pin first edge connector JN12, the second edge connector JN13, the 3rd edge connector JN14 and the 4th edge connector JN15, wherein, the first edge connector JN12 links to each other with JN2 with the edge connector JN1 of low 32 pci bus interfaces of described PMC interface with the second edge connector JN13, the 3rd edge connector JN14 links to each other with the edge connector JN3 of high 32 pci bus interfaces of described PMC interface, and the 4th edge connector JN15 links to each other with the edge connector JN4 of the self defined interface of PMC interface.
Converting unit 16 as Fig. 3, this example adopts the transparent bridge sheet 21154 because of special (Intel) company, be transparent mode, need not address translation, make that the equipment on the internal bus 22 be connected in PMC9 is transparent for the veneer 200 of CPCI platform, converting unit 16 links to each other with the 3rd edge connector JN14 with the first edge connector JN12, the second edge connector JN13 of interface unit 120 through external buss 21,64 pci bus of the veneer 200 of CPCI platform can be converted to 32 and output on the internal bus 22 of PMC9.
As the loopback unit 17 of Fig. 3, this example adopts the net sheet GD82551ER of Intel Company, an Ethernet interface with the 10M/100M compatibility is provided, and has loop fuction.
Detecting unit 10, place on the veneer 200 of CPCI platform, send 64 bit test data at 64 pci buss to the veneer 200 of CPCI platform, this test data is through the edge connector JN1 that 64 pci bus interfaces are provided of the PMC interface of the veneer 200 of CPCI platform, the first edge connector JN12 of edge connector JN2 and edge connector JN3 and PMC9, the second edge connector JN13 and the 3rd edge connector JN14 are transferred to converting unit 16, the 64 bit test data that converting unit 16 will receive are divided into two 32 test data and send to respectively on the internal bus 22, loopback unit 17 receives two 32 test data internally on the bus 22 respectively, and the data that receive are transferred to internal bus 22 more respectively, modular converter 16 receives two 32 test data internally on the bus 22 and this test data of two 32 is combined into one 64 test data and sends on the external bus 21, again via interface unit 120 (JN12, JN13, JN14) and the PMC interface (JN1 of the veneer 200 of CPCI platform, JN2 and JN3) to detecting unit 10, detecting unit 18 judges whether its test data of sending equates with the test data of receiving, if equate, represent that the pin that this test data tests is normal, otherwise represent that this pin is wrong.
The test data that measurement unit 10 sends, can adopt walking 0 method or walking 1 method, described walking 0 method, the position corresponding to the pin that will test is set to 0 in the test data exactly, other position is set to 1, circulation in a certain order, make 0 to cover all pins that will test, for example, test 32 pins of the interface of one 32 position datawire, can send following data 0xfffffffeH successively to a fixing address, 0xfffffffdH, 0xfffffffbH, 0xfffffff7H......0xbfffffffH, 0x7fffffffH, such 0 has just covered all 32 pins; Described walking 1 method, similar with described walking 0 method, the pairing position of the pin with testing of test data is set to 1 exactly, and other position is 0, and circulation in a certain order makes 1 to cover all pins that will test.
Because the address wire and the data wire of 64 pci buss of the veneer 200 of CPCI platform are multiplexing, so sending test data to fixed address just can all cover the PMC interface of 64 pci buss of the veneer 200 of CPCI platform, to adopting walking 1 method in this example, send 0x0000000000000001H successively, 0x0000000000000002H, 0x0000000000000004H, 0x0000000000000008H, ..., 0x4000000000000000H, 0x8000000000000000H is totally 64 test datas, all pins of the PMC interface of 64 pci buss of traversal.
Further, as shown in Figure 3, the loopback unit 18 of a kind of testing apparatus of the present invention also comprises logic control element 170 and cooperates card 180.
As shown in Figure 4, PMC9 is as the front card of CPCI platform, is plugged on the PMC interface of veneer 200 of CPCI platform, cooperates card 180 back card/back boards as the CPCI platform, is plugged on the back of the backboard 11 of CPCI platform.
Link to each other with the self defined interface JN4 of the PMC interface of the veneer 200 of CPCI platform as the cooperation card 10 of Fig. 3 backboard 11 by the CPCI platform, have loop fuction, 32 bit data of 32 pins of self defined interface JN4 of PMC interface that are about to be input to the veneer 200 of CPCI platform output on the external bus 21 of PMC9 through other 32 pins of the self defined interface JN4 of the PMC interface of the veneer 200 of CPCI platform.
As shown in Figure 5, logic control element 170 adopts field programmable gate array (FPGA, Field programble gate artay) the chip EP1K50 of altera corp in this example, comprise input register 23, output register 24 and control module 25.Logic control element 170 is bus 22 acceptance test data internally, test data is sent to the self defined interface JN4 of PMC interface of the veneer 200 of the 4th edge connector JN15 and CPCI platform by output register 24 through external bus 21, and with the input register 23 that reads back of the test data on the external bus 21.
Detecting unit 10 among Fig. 3, place on the veneer 200 of CPCI platform, 64 self defined interface JN4 to the PMC interface of the veneer 200 of CPCI platform send test datas, adopt walking 1 method in this example, detecting unit 10 sends 0x00000001H successively to output register 24,0x00000002H, 0x00000004H, 0x00000008H......0x40000000H, 0x80000000H is totally 32 32 different bit test data, control module 25 sends to 32 test data 32 pins of self defined interface JN4 of PMC interface of the veneer 200 of CPCI platform, by cooperating card 180 32 test data loopback to be sent to again the input register 23 of logic control element 170 through other 32 pins of the self defined interface JN4 of the PMC interface of the veneer 200 of CPCI platform, control module 25 reads the test data of input register 23 to detecting unit 10, detecting unit 10 compares the test data of transmission and the test data of reception, equate that the pin of expression test is normal; Otherwise the pin of expression test is wrong.
Further, as shown in Figure 3, a kind of testing apparatus of the present invention comprises power supply test unit 30 and power logic control unit 20.Power logic control unit 20 in this example adopts field programmable gate array (FPGA, Field programble gate array) the chip EP1K50 of altera corp, comprises status register 28 and energy supply control module 29.Energy supply control module 29 read the CPCI platform veneer 200 the PMC interface the power interface state (this routine normal voltage is ± 12V), if voltage status is normal, with status register 28 value of writing 0x03H, power supply detecting unit 30 reads the power supply status value from status register 28, if the value of reading is 0x03H, the expression power interface is normal, otherwise the expression power interface is wrong.
Further, as shown in Figure 3, PMC9 also comprises voltage conversion unit 26, the voltage that being used to change PMC9 provides makes it to be complementary with the operating voltage of the building block of PMC9, because that logic control element 170 and power logic control unit 20 adopt in this example is the field programmable gate array (FPGA of altera corp, Field programble gate array) chip EP1K50, the operating voltage of chip EP1K50 is shown 2.5V, and the operating voltage of PMC9 is 3.3V, so voltage conversion unit 26 becomes 2.5V to output to logic control element 170 and power logic control unit 20 voltage transitions of the 3.3V of PMC9.
Further, as shown in Figure 3, PMC9 also comprises clock circuit 27, is used to described PMC9 that clock signal is provided, and prior art repeats no more.
In sum, a kind of testing apparatus of the present invention can be tested all pins of 64 pci bus interfaces of the PMC interface of equipment under test 200, its further improvement can also be tested all pins of 64 self defined interfaces of PMC interface, further can also the testing power supply interface.
The above only is a preferred implementation of a kind of testing apparatus of the present invention; should be understood that; for those skilled in the art; under the prerequisite that does not break away from a kind of testing apparatus principle of the present invention; can also make some improvements and modifications, these improvements and modifications also should be considered as the protection range of a kind of testing apparatus of the present invention.
Claims (7)
1, a kind of testing apparatus is used for the peripheral device interconnection interlayer card interface of test setting on equipment under test, it is characterized in that this testing apparatus comprises peripheral device interconnection interlayer card and detecting unit,
Described peripheral device interconnection interlayer card further comprises interface unit, converting unit and loopback unit, wherein,
Described interface unit links to each other with the peripheral device interconnection interlayer card interface of described equipment under test, is used for transmitting test data;
Described converting unit links to each other with described interface unit, is used to transmit test data and/or conversion testing data transmission format;
Described loopback unit links to each other with described converting unit, and the test data that is used for receiving from described converting unit is back to this converting unit through described internal bus;
Described detecting unit, place on the described equipment under test, be used for tested pin at peripheral device interconnection interlayer card interface, send the peripheral device interconnection interlayer card interface of test data, return test data, judge whether the test data that sends equates with the test data of returning and draw test result via interface unit, converting unit and loopback unit to described equipment under test.
2, testing apparatus as claimed in claim 1 is characterized in that, described peripheral device interconnection interlayer card interface has self defined interface, and described loopback unit comprises logic control element and cooperate card, wherein,
Described cooperation card is used for the test data that loopback sends to self defined interface, has self defined interface and the self defined interface of the peripheral device interconnection interlayer card interface of the described equipment under test of directly pegging graft;
Described logic control element, one end links to each other with described converting unit, the other end links to each other with the self defined interface of described interface unit, is used for test data is passed to the self defined interface of described equipment under test and will return to described detecting unit through the test data that described cooperation snap ring returns.
3, testing apparatus as claimed in claim 2 is characterized in that, described logic control element comprises control module, input register and output register, wherein,
Described output register is used to deposit the test data that described detecting unit sends;
Described input register is used to deposit the test data of returning through described cooperation snap ring;
Described control module is used for test data that described detecting unit is sent and outputs to described interface module and read the test data of described input register and it is turned back to described detecting unit through described output register.
4, testing apparatus as claimed in claim 3, it is characterized in that, described peripheral device interconnection interlayer card interface has power interface, and the testing apparatus of described peripheral device interconnection interlayer card interface comprises power supply detecting unit and power logic control unit, described power logic control unit comprises status register and energy supply control module, wherein
Described energy supply control module is used to read the power interface state of the peripheral device interconnection interlayer card interface of described equipment under test;
Described status register is used to deposit the power interface state that described energy supply control module reads;
Described power supply detecting unit places on the equipment under test, the value that is used to drive described energy supply control module and reads described status register.
5, testing apparatus as claimed in claim 4, it is characterized in that, described peripheral device interconnection interlayer card also comprises voltage conversion unit, and the voltage that being used to change described peripheral device interconnection interlayer card provides makes it to be complementary with the operating voltage of the building block of described peripheral device interconnection interlayer card.
6, testing apparatus as claimed in claim 5 is characterized in that, described peripheral device interconnection interlayer card also comprises clock circuit, is used to described peripheral device interconnection interlayer card that clock signal is provided.
As described any testing apparatus of claim 1 to 7, it is characterized in that 7, described converting unit links to each other with described interface unit by external bus, described loopback unit links to each other with described converting unit by internal bus.
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| CNB2004100623282A CN1330135C (en) | 2004-07-01 | 2004-07-01 | Detector |
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| CNB2004100623282A CN1330135C (en) | 2004-07-01 | 2004-07-01 | Detector |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100461717C (en) * | 2006-01-17 | 2009-02-11 | 华为技术有限公司 | Communication device and its detecting method |
| CN101166098A (en) * | 2006-10-20 | 2008-04-23 | 华为技术有限公司 | Communication system and unit with dual wide advanced interlayer card and advanced interlayer card mixed configuration |
| CN103746818B (en) * | 2013-12-27 | 2018-03-02 | 上海斐讯数据通信技术有限公司 | A kind of signal connection system between network switch support plate and sandwich plate |
| CN112241157A (en) * | 2020-09-04 | 2021-01-19 | 北京新能源汽车技术创新中心有限公司 | Loopback testing device and method for diagnosing communication link fault of vehicle central gateway |
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| CN1274115A (en) * | 1999-05-14 | 2000-11-22 | 英业达股份有限公司 | Device and method for testing communication interface card slot |
| CN1353523A (en) * | 2000-11-07 | 2002-06-12 | 华为技术有限公司 | Switch network card tester and method |
| CN1489806A (en) * | 2000-12-18 | 2004-04-14 | ������������ʽ���� | Antenna for RFID |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6145100A (en) * | 1998-03-04 | 2000-11-07 | Advanced Micro Devices, Inc. | Debug interface including timing synchronization logic |
| CN1274115A (en) * | 1999-05-14 | 2000-11-22 | 英业达股份有限公司 | Device and method for testing communication interface card slot |
| CN1353523A (en) * | 2000-11-07 | 2002-06-12 | 华为技术有限公司 | Switch network card tester and method |
| CN1489806A (en) * | 2000-12-18 | 2004-04-14 | ������������ʽ���� | Antenna for RFID |
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