CN1315049C - Diagnostic circuit module and method for detecting computer trouble - Google Patents
Diagnostic circuit module and method for detecting computer trouble Download PDFInfo
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- CN1315049C CN1315049C CNB021464820A CN02146482A CN1315049C CN 1315049 C CN1315049 C CN 1315049C CN B021464820 A CNB021464820 A CN B021464820A CN 02146482 A CN02146482 A CN 02146482A CN 1315049 C CN1315049 C CN 1315049C
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Abstract
The present invention relates to a diagnosing circuit module for detecting computer failure and a method thereof. The circuit module comprises a decoder which is respectively connected with the PCI bus lines of a computer and is used for decoding fault codes sent by the BIOS of the computer, a latch unit for latching the fault codes, a memory for storing various failure voice, a clock generating circuit, a counter connected with the output end of the clock generating circuit, a D/A change-over circuit and a power amplification circuit which are orderly connected with the voice memory and a reset circuit for carrying out energizing resetting to the latch unit and the counter, wherein the output ends of the decoder and the counter are respectively connected to the voice memory and are respectively used as the high address and the low address of the memory; the decoder is also connected with the latch unit and the counter to respectively supply a latching control signal and a counter clear signal when the change of fault codes occurs in a decode procedure. The module can realize the real-time monitoring display and the voice warning of the computer by being matched with a simple peripheral circuit, and the diagnosing circuit module can be widely used.
Description
Technical field
The present invention relates to a kind of detection computations machine Fault Diagnosis circuit arrangement and method of being used for, exactly, relate to a kind of test circuit device and method that is used for detection computations machine motherboard hardware fault, belong to error-detecting or monitoring technique field in the computer technology.
Background technology
At present, with personal computer and notebook computer is that all kinds of computing machines of representative have been penetrated into people's work day by day, study, produce, daily life, and even various aspects such as amusement and recreation, but, up to now, no matter be that computing machine is made manufacturer, or maintenance and repair department, fault for computing machine is mainly still passed through oscillograph, instruments such as logic pen, watch circuit waveform by rule of thumb by the testing staff, measuring voltage, whether whether the range estimation circuit board has the method for traditional detection digital circuit such as blackout place etc. to detect it exists fault, this traditional detection method not only needs the long period trouble-shooting, also need to dispose certain checkout equipment, more closely related with testing staff's professional skill height, efficient is low, and the cost height is demanded urgently improving.
Summary of the invention
The purpose of this invention is to provide a kind of detection computations machine Fault Diagnosis circuit arrangement that is used for, this diagnostic circuit device is aided with simple peripheral circuit, real-time monitoring, the fault that can realize computing machine automatically show and phonic warning, for realizing that in production, debugging and the maintenance process of computing machine detecting robotization provides the important techniques means.
Another object of the present invention provides a kind of detection computations machine fault Diagnosis Method that is used for.
The object of the present invention is achieved like this: a kind of detection computations machine Fault Diagnosis circuit arrangement that is used for, it is characterized in that: this circuit arrangement includes: be connected with computer PCI bus respectively, be used for demoder that the diagnostic trouble code that computer BIOS sends is decoded and the latch that latchs this diagnostic trouble code, store the storer of various failure voices, clock generation circuit and the counter that is connected this clock generation circuit output terminal, the D/A change-over circuit and the power amplification circuit that are linked in sequence with speech memory, and the reset circuit that the latch sum counter is carried out electrification reset; Described clock generation circuit is returned D/A change-over circuit output changeover control signal, and the output terminal of described demoder sum counter is connected to speech memory respectively, respectively as the high address and the low order address of this storer; Described demoder also links to each other with the latch sum counter, so as in decode procedure, to break down the sign indicating number variation the time, latch control signal sum counter reset signal is provided respectively.
Described circuit arrangement further includes: from described latch draw as the outer connector of expanding universal purpose, and from described power amplification circuit draw as connector outside the audio frequency of phonic warning.
Described outer connector as the expanding universal purpose can external fault warning light-emitting diode display.
Described outer connector as the expanding universal purpose can external single-chip microcomputer, is used for driving the fault detect of other testing apparatus or/and the extended use of treatment circuit by this interface.
Described clock generation circuit is a phase locked loop oscillator.
Described demoder is to be constituted by a plurality of general decoders, and this code translator model can be selected GAL16V8 for use.
Described diagnostic circuit device can be made application-specific integrated circuit ASIC, also can make the special test card, can also be set directly on the computer motherboard.
The application-specific integrated circuit ASIC of described diagnostic circuit device is provided with: the computer PCI interface of standard is used to read the diagnostic trouble code that detected computing machine sends; Audio interface is used to send failure voice information; Video LED interface is used to send the visual signal of fault warning; General purpose interface when being used to break down, drives the fault detect of other testing apparatuss or/and treatment circuit by this interface.
Another object of the present invention is achieved in that a kind of detection computations machine fault Diagnosis Method that is used for, it is characterized in that: when utilizing computer booting operation BIOS self-check program, 80 mouthfuls to I/O in Power-On Self-Test POST process are sent the hardware check diagnostic trouble code, and this diagnostic trouble code are handled the auto-real-time monitoring of realizing computer failure; Comprise the following steps:
(1) utilizes in the hardware power-on self-test POST process in the computer BIOS and send different diagnostic trouble code, computing machine is carried out hardware check;
(2) if self check is passed through, BIOS just continues downward self check, and corresponding diagnostic trouble code also can change thereupon; If there is fault in this detected hardware, BIOS just no longer down carries out, at this moment the diagnostic trouble code of 80 mouthfuls of its I/O current guilty culprits of output this computing machine of reflection;
(3) utilize the demoder sum counter that various diagnostic trouble code are decoded, and storage and the above-mentioned diagnostic trouble code storer of various failure voices one to one, make each diagnostic trouble code and failure voice in correspondence with each other, and automatic addressing is exported corresponding failure voice; Export this diagnostic trouble code simultaneously, be sent to display interface and general purpose interface, the latter is used to drive other checkout equipment; Finish the diagnosis and the detection of computer failure thus.
The concrete grammar that in the storer of the various failure voices of storage each diagnostic trouble code and failure voice is got up in correspondence with each other in the described step (3) is: with the failure voice deposit data in a storer, utilize its high address that the failure voice storer is divided into different sections, the respectively corresponding a kind of different failure voice data of each different section, the start address 0000H of each section is the beginning of corresponding each segment fault speech data then; When finding that in decode procedure diagnostic trouble code changes, at first determine the high address of this failure voice, send the counter O reset pulse simultaneously, it is the low order address of clear counter, and, guarantee that each failure voice data all are partly to read from the beginning in the associated storage zone of this speech memory as the trigger condition of failure voice.
The present invention is a kind of detection computations machine Fault Diagnosis circuit arrangement and method of being used for, this device is equipped with extremely simple peripheral circuit, utilize the self check diagnostic trouble code in Power-On Self-Test in the computer BIOS (POST) process, and, can realize automatically that the real-time monitoring of computing machine, fault show and phonic warning to decoding circuit, speech memory and other peripheral circuits that diagnostic trouble code is decoded.New Ying is ingenious in design concept of the present invention, makes full use of the self-characteristic in the BIOS POST process, and the hardware circuit of this device is simple, and volume is little, is easy to carry reliable operation.Both this device can be made the application-specific integrated circuit ASIC chip, also can make the special test card, can also be directly installed on the computer motherboard, and make this computing machine have the fault self-checking function.This device has the multiple standards interface mode: computer interface, audio interface, display interface and general purpose interface (being interface microcontroller), the expansion utilization is very convenient, because this device is provided with the man-machine interface good interface of voice mode, use this device carry out computer motherboard debugging, the maintenance all very convenient, improved work efficiency, also reduced requirement, the cost that reduces debugging and safeguard to technical level of operators.General purpose interface in this device can make this device apply in the at present domestic computer automation testing device that lacks very much.If device of the present invention and interface microcontroller are used, its expansion can be applied to many voice occasions of prompting automatically that need,, aircraft altitude antitheft and speed prompting, oil meter, vehicle stall warning as: motorbus, automatically-controlled door, attendance recorder, car alarm, building automatic, fire-fighting, phone affairs machine etc.In a word, the present invention provides important techniques means for how to realize a difficult problem for many years that detects robotization in computing machine production, debugging and maintenance process, has good application prospects.
Description of drawings
Fig. 1 is the circuit structure block scheme that the present invention is used for detection computations machine Fault Diagnosis circuit arrangement.
Fig. 2 is the embodiment that the present invention is used for detection computations machine Fault Diagnosis circuit arrangement: the composition block scheme of computer speech fault test card.
Embodiment
Referring to Fig. 1, the present invention is a kind of detection computations machine Fault Diagnosis circuit arrangement that is used for, be this circuit arrangement among Fig. 1 shown in the frame of broken lines, it includes: be connected with computer PCI bus respectively, be used for demoder (model is GAL16V8) that the diagnostic trouble code that computer BIOS POST process is sent by its 80H mouth is decoded and the latch (model is 74LS273) that latchs this diagnostic trouble code, store the storer of various failure voices, clock generation circuit and the counter (model is 74LS4020) that is connected this clock generation circuit output terminal, the D/A change-over circuit and the power amplification circuit that are linked in sequence with speech memory, and the reset circuit (model is MAX705) that the latch sum counter is carried out electrification reset; Wherein the output terminal of demoder sum counter is connected to speech memory respectively, respectively as the high address and the low order address of this storer; This demoder also links to each other with the latch sum counter, so as in decode procedure, to break down the sign indicating number variation the time, latch control signal sum counter reset signal is provided respectively.
This circuit arrangement also includes: from the diagnostic trouble code latch draw as the outer connector of expanding universal purpose, should as the outer connector of expanding universal purpose can external fault warning light-emitting diode display, also can external single-chip microcomputer, perhaps be connected with fault detect that drives other testing apparatuss or/and treatment circuit by cable.Lead to as connector outside the audio frequency of phonic warning from power amplification circuit.
Diagnostic trouble code demoder of the present invention is to be constituted by a plurality of general decoders (model is GAL16V8), so that the input pin of these code translators and detected computer PCI bus are coupled together one by one, receives the diagnostic trouble code signal that its 80H mouth sends.It is the phase locked loop oscillator (model is LM567) of 2KHz that clock generation circuit of the present invention adopts frequency of operation.Power on or computer motherboard when powering on detecting at every turn, this reset circuit will produce delayed reset signal at its RES pin, after the driving in this circuit, offer interlock circuit parts such as diagnostic trouble code latch sum counter respectively, guarantee the synchronous reliably working of each parts.As the demonstration zero clearing of latch and assurance counter are counted since 0 address, guarantee that promptly each phonic warning all is to send Trouble Report sound from the beginning section.
Following brief description diagnostic method of the present invention or working mechanism: each computing machine is not when breaking down, and its bios program all can be carried out hardware power-on self-test program, and sends different diagnostic trouble code in this process; Just before one section self-check program of every execution, BIOS can send the fault detect sign indicating number to 80 mouthfuls of I/O, represents that this computing machine is carrying out the self check of this hardware.If there is fault in this detected hardware, BIOS has just no longer down carried out.This moment its I/O 80 mouthfuls of fault detect sign indicating numbers that send, just reflected the current guilty culprit of this computing machine.If self check is passed through, BIOS will continue to carry out self check downwards, and corresponding fault detect sign indicating number also can change.The present invention is exactly this self-characteristic that utilizes computing machine, finds in the electric on computers self check process what hardware fault it has.For this reason, the present invention is provided with a demoder sum counter that various diagnostic trouble code are decoded, and storage and the above-mentioned diagnostic trouble code storer of various failure voices one to one, and adopt following circuit to realize in correspondence with each other with diagnostic trouble code and failure voice: with the failure voice deposit data in a FLASH storer, utilize its high address that the failure voice storer is divided into different sections, the respectively corresponding a kind of different failure voice data of each different section.The low order address 0000H that is provided by counter is the beginning of corresponding each segment fault speech data then.When the present invention adopts scrambler to find that in decode procedure diagnostic trouble code changes, send the counter O reset pulse, it is the low order address of clear counter, as the trigger condition of failure voice, guarantee that each failure voice data all are partly to read from the beginning in the associated storage zone of this speech memory.After the address of failure voice storer was determined, its speech data will appear on the data bus.By D/A change-over circuit and power amplification circuit, just can convert digital voice data to analog voice signal and inform the testing staff again by loudspeaker.Wherein the conversion and control pulse of D/A change-over circuit is also provided by oscillator.Just can finish the voice diagnosis of computer failure by foregoing circuit.
The demonstration of diagnostic trouble code then is the diagnostic trouble code that latchs 80H by the latch control signal that adopts demoder to send by latch, and the driving LED display sends demonstration again.In addition, also draw diagnostic trouble code and latch control line from latch, as the fault detect of other external testing apparatus or/and the extended use of treatment circuit.
Diagnostic circuit device of the present invention can be made application-specific integrated circuit ASIC (Application ServiceIntegrated Circuit), also can make the special test card, can also be set directly on the computer motherboard.The application-specific integrated circuit ASIC of this diagnostic circuit device is provided with: the computer PCI interface of standard is used to read the diagnostic trouble code that detected computing machine sends; Audio interface is used to send failure voice information; Video interface is used to send the visual signal of alarm failure sign indicating number; General purpose interface when being used to break down, drives the fault detect of other testing apparatuss or/and treatment circuit by this interface single-chip microcomputer.
Referring to embodiment shown in Figure 2, further introduce the computer speech fault detect card of forming with circuit arrangement of the present invention (shown in solid line block diagram among the figure), as long as increase loudspeaker and display device again, just can form a computer speech fault detect card for fault diagnosis circuit device of the present invention.This test card is connected with computer PCI bus, and read failure information is sent voice suggestion and shown diagnostic trouble code.Utilize this circuit arrangement to increase the detection of other testing apparatuss if desired or/and processing capacity also as long as the general purpose expansion interface that provides at this circuit arrangement is connected with corresponding other testing apparatuss, just can realize it easily.
Claims (10)
1, a kind of detection computations machine Fault Diagnosis circuit arrangement that is used for, it is characterized in that: this circuit arrangement includes: be connected with computer PCI bus respectively, be used for the demoder that the diagnostic trouble code that computer BIOS sends is decoded and latch the latch of this diagnostic trouble code, store the storer of various failure voices, clock generation circuit and the counter that is connected this clock generation circuit output terminal, the D/A change-over circuit and the power amplification circuit that are linked in sequence with speech memory, and the reset circuit that the latch sum counter is carried out electrification reset; Described clock generation circuit is returned D/A change-over circuit output changeover control signal, and the output terminal of described demoder sum counter is connected to speech memory respectively, respectively as the high address and the low order address of this storer; Described demoder also links to each other with the latch sum counter, so as in decode procedure, to break down the sign indicating number variation the time, latch control signal sum counter reset signal is provided respectively.
2, the detection computations machine Fault Diagnosis circuit arrangement that is used for according to claim 1, it is characterized in that: described circuit arrangement further includes: from described latch draw as the outer connector of expanding universal purpose, and from described power amplification circuit draw as connector outside the audio frequency of phonic warning.
3, the detection computations machine Fault Diagnosis circuit arrangement that is used for according to claim 2 is characterized in that: the light-emitting diode display that described outer connector as the expanding universal purpose can external fault warning.
4, the detection computations machine Fault Diagnosis circuit arrangement that is used for according to claim 2, it is characterized in that: described outer connector as the expanding universal purpose can external single-chip microcomputer, is used for driving the fault detect of other testing apparatus or/and the extended use of treatment circuit by this interface.
5, the detection computations machine Fault Diagnosis circuit arrangement that is used for according to claim 1, it is characterized in that: described clock generation circuit is a phase locked loop oscillator.
6, the detection computations machine Fault Diagnosis circuit arrangement that is used for according to claim 1, it is characterized in that: described demoder is to be constituted by a plurality of general decoders, this code translator model can be selected GAL16V8 for use.
7, the detection computations machine Fault Diagnosis circuit arrangement that is used for according to claim 1, it is characterized in that: described diagnostic circuit device can be made application-specific integrated circuit ASIC, also can make the special test card, can also be set directly on the computer motherboard.
8, the detection computations machine Fault Diagnosis circuit arrangement that is used for according to claim 1, it is characterized in that: the application-specific integrated circuit ASIC of described diagnostic circuit device is provided with: the computer PCI interface of standard is used to read the diagnostic trouble code that detected computing machine sends; Audio interface is used to send failure voice information; Video LED interface is used to send the visual signal of fault warning; General purpose interface when being used to break down, drives the fault detect of other testing apparatuss or/and treatment circuit by this interface.
9, a kind of detection computations machine fault Diagnosis Method that is used for, it is characterized in that: when utilizing computer booting operation BIOS self-check program, 80 mouthfuls to I/O in Power-On Self-Test POST process are sent the hardware check diagnostic trouble code, and this diagnostic trouble code are handled the auto-real-time monitoring of realizing computer failure; Comprise the following steps:
(1) utilizes in the hardware power-on self-test POST process in the computer BIOS and send different diagnostic trouble code, computing machine is carried out hardware check;
(2) if self check is passed through, BIOS just continues downward self check, and corresponding diagnostic trouble code also can change thereupon; If there is fault in this detected hardware, BIOS just no longer down carries out, at this moment the diagnostic trouble code of 80 mouthfuls of its I/O current guilty culprits of output this computing machine of reflection;
(3) utilize the demoder sum counter that various diagnostic trouble code are decoded, and storage and the above-mentioned diagnostic trouble code storer of various failure voices one to one, make each diagnostic trouble code and failure voice in correspondence with each other, and automatic addressing is exported corresponding failure voice; Export this diagnostic trouble code simultaneously, be sent to display interface and general purpose interface, the latter is used to drive other checkout equipment; Finish the diagnosis and the detection of computer failure thus.
10, the detection computations machine fault Diagnosis Method that is used for according to claim 9, it is characterized in that: the concrete grammar that in the storer of the various failure voices of storage each diagnostic trouble code and failure voice is got up in correspondence with each other in the described step (3) is: with the failure voice deposit data in a storer, utilize its high address that the failure voice storer is divided into different sections, the respectively corresponding a kind of different failure voice data of each different section, the start address 0000H of each section is the beginning of corresponding each segment fault speech data then; When finding that in decode procedure diagnostic trouble code changes, at first determine the high address of this failure voice, send the counter O reset pulse simultaneously, it is the low order address of clear counter, and, guarantee that each failure voice data all are partly to read from the beginning in the associated storage zone of this speech memory as the trigger condition of failure voice.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021464820A CN1315049C (en) | 2002-11-12 | 2002-11-12 | Diagnostic circuit module and method for detecting computer trouble |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021464820A CN1315049C (en) | 2002-11-12 | 2002-11-12 | Diagnostic circuit module and method for detecting computer trouble |
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| Publication Number | Publication Date |
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| CN1501249A CN1501249A (en) | 2004-06-02 |
| CN1315049C true CN1315049C (en) | 2007-05-09 |
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| CNB021464820A Expired - Fee Related CN1315049C (en) | 2002-11-12 | 2002-11-12 | Diagnostic circuit module and method for detecting computer trouble |
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Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7350626B2 (en) | 2004-10-20 | 2008-04-01 | Otis Elevator Company | Power-on-reset of elevator controllers |
| CN100461141C (en) * | 2005-03-22 | 2009-02-11 | 威盛电子股份有限公司 | Method for monitoring system bus and relative device |
| CN101227347B (en) * | 2008-01-07 | 2010-08-25 | 上海颐东网络信息有限公司 | Method and apparatus for remote monitoring mainframe network state |
| CN102253873B (en) * | 2010-05-19 | 2013-11-20 | 鸿富锦精密工业（深圳）有限公司 | Alarm system and method for BIOS (Basic Input Output System) |
| CN102411532A (en) * | 2011-12-31 | 2012-04-11 | 曙光信息产业股份有限公司 | Computer failure reminding method and device, and computer |
| CN103200023A (en) * | 2012-01-09 | 2013-07-10 | 联想(北京)有限公司 | Method and device of sending hardware information, and method and system of processing hardware information |
| CN103995758A (en) * | 2014-05-21 | 2014-08-20 | 浪潮电子信息产业股份有限公司 | Method for displaying main board fault information in delayed mode |
| CN104615515A (en) * | 2015-02-05 | 2015-05-13 | 中国人民解放军海军航空工程学院 | Computer hardware monitoring system and implement method thereof |
| CN105183602B (en) * | 2015-10-09 | 2018-10-26 | 天津市英贝特航天科技有限公司 | Computer booting fault self-diagnosis and process inquiry unit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1052384A (en) * | 1990-12-10 | 1991-06-19 | 陆为民 | Diagnostic test card for microcomputer |
| CN1077037A (en) * | 1992-03-06 | 1993-10-06 | 国际商业机器公司 | Multi-media computer diagnostic system |
| US5964845A (en) * | 1995-04-18 | 1999-10-12 | International Business Machines Corporation | Processing system having improved bi-directional serial clock communication circuitry |
-
2002
- 2002-11-12 CN CNB021464820A patent/CN1315049C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1052384A (en) * | 1990-12-10 | 1991-06-19 | 陆为民 | Diagnostic test card for microcomputer |
| CN1077037A (en) * | 1992-03-06 | 1993-10-06 | 国际商业机器公司 | Multi-media computer diagnostic system |
| US5964845A (en) * | 1995-04-18 | 1999-10-12 | International Business Machines Corporation | Processing system having improved bi-directional serial clock communication circuitry |
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