CN1314708A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN1314708A
CN1314708A CN01117392A CN01117392A CN1314708A CN 1314708 A CN1314708 A CN 1314708A CN 01117392 A CN01117392 A CN 01117392A CN 01117392 A CN01117392 A CN 01117392A CN 1314708 A CN1314708 A CN 1314708A
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China
Prior art keywords
mentioned
welding zone
electrode welding
chip
semiconductor chip
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Granted
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CN01117392A
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CN1193424C (zh
Inventor
千川保宪
北崎宏明
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III Holdings 10 LLC
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Sharp Corp
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Publication of CN1314708A publication Critical patent/CN1314708A/zh
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Abstract

IC芯片的电路形成面上避开外部引出电极来设置再布线层。再布线层就在IC芯片的电路制造时随电路形成继续形成,作为IC芯片制造的一个环节进行再布线层的形成。再布线层上设置有:在芯片周围侧的第1电极焊区、在比第1电极焊区要靠近IC芯片侧的第2电极焊区,和第1电极焊区的每个和第2电极焊区的每个一对一连接的布线。因此,可以提供一种在多个半导体芯片叠层的构成中,可以增加叠层的半导体芯片尺寸的可能组合,而又抑制封装成本的上升、封装厚度的增加和封装制造生产率的降低的半导体装置。

Description

半导体装置
本发明有关一种由多个半导体芯片叠层并封装化成一个的半导体装置。
众所周知，以往，将由多个半导体芯片叠层并封装化成一个称之为叠式封装的半导体装置。叠式封装按照保持层叠半导体芯片的叠层基台，大致分为：1)将半导体芯片叠层到广泛使用于一般半导体封装的引线架上的封装；2)将形成布线图形的聚酰亚胺系列树脂膜做为基片，其上叠层半导体芯片的封装；3)刚性印制电路板上叠层半导体芯片的封装等的三种类型。就2)的构成和3)的构成的一部分来说，具有可将封装尺寸缩小到近似芯片尺寸的特征，这种封装称之为CSP(Chip Size Package：芯片尺寸封装)。
在叠式封装内作为叠层的多个半导体芯片的组合，包括存储器IC相互的组合、IC与逻辑电路IC的组合、CMOSIC与双极IC的组合等各种构成。作为移动电话用的叠式封装，就广泛使用瞬时存储器与SRAM叠层的封装。
图4中示出现有CSP型叠式封装的构成例。该叠式封装51是；将由聚酰亚胺基片或印制电路板构成的CSP基片52为叠层基台，按此顺序叠层IC芯片53和比其尺寸要小的IC芯片54的构成。在CSP基片52与IC芯片53之间，以及IC芯片53与IC芯片54之间用小片粘合层55粘合起来。在IC芯片53、54上各自设置外部引出电极53a---、54a---，并分别与设置在CSP基片52上的封装外部引出电极52a---连线。
作为该连线的方法，如同图所示，广泛使用着金线等的金属线56的引线接合法。在叠层基台是引线架时也使用引线接合法。上述封装外部引出电极52a---，通过通孔52b---而与设置于CSP基片52背面一侧的软钎料球状电极57---连接。而且，在CSP基片52的表面一侧，如上所述，采用在IC芯片53、54的外部引出电极53a---、54a---与CSP基片52的布线导通的状态下用树脂58密封的办法，把整个叠式封装51封装化。
另外，有时叠层IC芯片的几个外部引出电极也不与封装外部引出电极连线，而与叠层的其它IC芯片的外部引出电极连线。
可是，上述现有的叠式封装的构成，在用引线接合法进行连线时，发生以下示出的这种问题。
首先，因金属线的材料特性，使金属线的长度L是以3mm左右为界限。而且，在接合开始后，将金属线向接合端到开始弯曲，需要保证垂直上方与接合表面的环形线高度在一定范围。因此，如图5的叠式封装61所示，上层的IC芯片62的大小比下层的IC芯片53要相当小，要是用金属线56超过下层的IC芯片53---来连接IC芯片62的外部引出电极62a---和封装外部引出电极52a---的话，就会随着IC芯片53的尺寸而使金属线56---的长度L超过上述界限。这时，会有金属线56---在接合时中途下垂，或与从IC芯片53来的金属线56---相接触，或有金属线56---中途断开的危险。即，在这种情况下，可能叠层的IC芯片尺寸的组合就相当限制了。
并且，例如象图4和图5的软钎料球状电极57…之类封装外部连接端子的配置要由用途定下来，并且有关IC芯片的外部引出电极配置到芯片的什么位置要由IC设计决定。因此，连接IC芯片的外部引出电极与叠层基台的封装外部引出电极的金属线长度即使比上述界限小的时候，由于上述这种外部连接端子与外部引出电极间的位置关系，决定了金属线相互交叉接触，往往不能很好连线。
以前，作为其解决对策，可应用以下两种方法，第一种方法是，以IC芯片的叠层基台为多层布线基片，从IC芯片用金属线连接到叠层基台上可能引线接合的位置，再用基片内部的布线，连接接合位置与封装规定的外部连接端子的连线方法。
第二种方法是，日本国公开特许公报“特开平11-97571号公报(公开日1999年4月9日)公布的方法。用该方法形成叫做插入式选择指的布线转换基片，从IC芯片到与插入式选择指的容易接合位置进行引线接合。而且，从插入式选择指的靠近封装外部引出电极的位置到该封装外部引出电极进行引线接合，并且插入式选择指的上述2个接合点用插入式选择指的内部布线进行连接。
但是，这两种方法有以下的这些问题。1)多层布线基片和插入式选择指等价高，涉及封装成本大幅度上升。2)采用上述公报所述的硅基片的插入式选择指则需要与IC芯片同等水平的高度微细加工技术，就是需要用于作成插入式选择指的特别制造工序和制造场所。3)使用多层布线基片和硅插入式选择指时封装的厚度增大，就不可能制成规定厚度以下的封装。并且，因此，随着封装厚度的改变，也需要改变封装组装工序、设备、夹具以及工具之类，就不可能将通用设备共用化。
另外，因为直接用金属线连接半导体芯片的外部引出电极和封装外部引出电极，金属线的长度超过上述界限时，采用在半导体芯片的叠层中间插入上述插入式选择指的办法，作为缩短金属线各自的长度，也改变不了发生上述1)～3)的不合适情况。
这样，以往想要增加叠层的半导体芯片尺寸的可能的组合时，或者，为了取得全部叠层的半导体芯片的外部引出电极与封装的外部引出电极之间导通而想要在进行的引线接合中使金属线相互不接触时，就存在导致封装成本大幅度上升、封装厚度大幅度增加、和封装制造生产率大幅度降低的问题。显然，这个问题随叠层的半导体芯片层数越增加，变得越深刻。
本发明的目的在于提供一种如叠式封装的那样，在多个半导体芯片层叠的构成中，既可抑制封装成本的上升、封装厚度的增加和封装制造生产率的降低，又能增加叠层的半导体芯片尺寸的可能组合的半导体装置。
为达成上述目的，根据本发明的半导体装置是，将设置有外部引出电极的多个半导体芯片叠层，并在上述外部引出电极与上述半导体芯片叠层基台的布线导通的状态下封装化的半导体装置，其特征是在至少一个上述半导体芯片的电路形成面上，设置：配置于芯片周围侧的第1电极焊区；配置于比上述第1电极焊区要靠近一个上层的半导体芯片侧的第2电极焊区；及具有连接上述第1电极焊区和上述第2电极焊区的布线的再布线层。
倘采用上述构成，则在一个半导体芯片的电路形成面上形成如上述的再布线层。在该再布线层上设置两种电极焊区，芯片周围侧配置第1电极焊区，并在比第1电极焊区要靠近一个上层芯片的侧面配置第2电极焊区。而且，用布线连接第1电极焊区和第2电极焊区。
第2电极焊区，例如，除可以用作用于在与最上层的半导体芯片之间进行引线接合的接合焊区外，也可以用作一个上层半导体芯片的倒装片接合用的电极。在将第2电极焊区用作接合焊区时，该电连接可以通过布线随着从第1电极焊区的引线接合使其再延长。通过如上所述配置第1和第2电极焊区，介以具备再布线层的半导体芯片，分成多次进行引线接合法的一方比从最上层的半导体芯片直接向叠层基台的布线上进行引线接合，每条金属线的长度都要缩短。因此，用一次引线接合法连接半导体芯片与叠层基台时，即使对金属线长度超过界限的那种半导体芯片尺寸的组合，也能将整个金属线的长度缩小到比界限长度小。
并且，基本上只要在电路形成面上形成金属膜等的布线层和绝缘膜就可以，因而再布线层的厚度与插入式选择指比较，有压倒性减小。
根据以上，提供一种如叠式封装的那样，在多个半导体芯片叠层的构成中，既可抑制封装成本的上升、封装厚度的增加和封装制造生产率的降低，又可增加叠层的半导体芯片尺寸的可能组合的半导体装置。
进而本发明的其它目的、特征和优点，通过以下所示的记载将得到充分了解。并且，本发明的优点，参照附图的下面说明将变得更明白。
图1(a)是表示根据本发明一个实施例的半导体装置构成的平面透视图，
图1(b)是图1(a)的A-A线的剖面图。
图2是表示图1(a)和图1(b)的半导体装置变形例的构成平面透视图。
图3是表示根据本发明的另一个实施例半导体装置的构成剖面图。
图4是表示现有半导体装置的构成例的剖面图。
图5是表示现有半导体装置的另一个构成例的剖面图。
[实施例1]
利用图1(a)、图1(b)和图2说明实现本发明半导体装置的一个实施例，则具体如下。
图1(a)和图1(b)示出作为本实施例的半导体装置的CSP型叠式封装1的构成。图1(a)为从叠层上方一侧观看叠式封装1的平面透视图，图1(b)是图1(a)的A-A线的剖面图。该叠式封装1，现在已经以聚酰亚胺基片或印制电路板等的绝缘性树脂基片构成的CSP基片2作为叠层基台，并将作为半导体芯片的IC芯片3和半导体芯片尺寸比其小的IC芯片4按该顺序叠层的构成。另外，作为叠层基台，如果假定封装为大量生产型的大小，则也可以用引线架，使用绝缘性树脂基片时就可以供给高密度装配型的封装。在CSP基片2与IC芯片3之间和IC芯片3与IC芯片4之际用小片粘合层5粘合起来。
在IC芯片3、4上，各自设置有形成于叠层上方一侧的电路和用于取得与外部导通的外部引出电极3a---、4a---。并且，在IC芯片3的电路形成面上，避开外部引出电极3a---而设置再布线层6。再布线层6是在制造IC芯片3时，与电路形成连接地形成的。即，再布线层6的形成成为制造IC芯片3的一个环节。
通常，IC芯片3就是在硅基片上形成晶体管等的电路器件的构成。而且，残留外部引出电极的电极焊区而其它电路部分的表面覆盖有表面保护膜，叫做SiN和聚酰亚胺等构成的钝化膜(表面保护膜)的绝缘膜。再布线层6就是在上述电路的制造工序中，在钝化膜上与IC芯片3的电路电隔离的情况下，形成1层或多层金属膜等的布线层及其绝缘膜。另外，如有需要，在再布线层6中，也可以形成与IC芯片3的电路直接连接的那种布线层。
上述布线层具有第1电极焊区6a---、第2电极焊区6b---和布线6c---。第1电极焊区6a---被配置在IC芯片3的周围侧。第2电极焊区6b---被配置在比第1电极焊区6a---要靠近一个上层的IC芯片4侧。布线6c---用一对一连接各个第1电极焊区6a---和各个第2电极焊区6b---。该布线6c---只要不与其它金属部分接触也可以露出，但以覆盖钝化膜为好。因此，在IC芯片3的叠层上方侧面变成露出第1电极焊区6a---、第2电极焊区6b---和IC芯片3a----的状态。
在本实施例中，利用该再布线层6进行引线接合。IC芯片4的外部引出电极4a---用金线等金属线7与IC芯片4的第2电极焊区6b---连接。并且，IC芯片3的第1电极焊区6a---用金属线7---与作为CSP基片2的布线的封装外部引出电极2a---连接。并且，IC芯片3的外部引出电极3a---，用金属线7---与除与封装外部引出电极2a---之中IC芯片3的第1电极焊区6a---连接以外进行连接。另外，在图1(b)中，示出连接到封装外部引出电极2a---的金属线7---相互不交叉的情况，为方便，图示出与图1(a)不同的引线接合的状态。
封装外部引出电极2a---，通过通孔2b---与设于CSP基片2背面的表面侧的软钎料球状电极8---连接。而且，在CSP基片2的表面侧，如上所述IC芯片3、4的外部引出电极3a---、4a---在与CSP基片2的封装外部引出电极2a---导通的状态下，通过用树脂9密封的办法，对整个叠式封装1进行封装。
如上所述，再布线层6的第2电极焊区6b---，用作与上层IC芯片4的IC芯片4a---之间进行引线接合的接合焊区。并且，再布线层6的第1电极焊区6a---，用作与CSP基片2的外部引出电极2a---之间进行引线接合的接合焊区。进而，第2电极焊区6b---与第1电极焊区6a---，分别用布线6c---进行连接。因此，外部引出电极4a---，通过第2电极焊区6b---、布线6c---、和第1电极焊区6a---，与封装外部引出电极2a---电连接起来。
这样，采用介以备有再布线层6的IC芯片3分成多次进行引线接合的话，就可以比从上层的外部引出电极4a---向CSP基片2的封装外部引出电极2a---直接进行引线接合，要缩短每一条金属线7---的长度。因此，如用一次引线接合连接IC芯片4的外部引出电极4a---与CSP基片2的封装外部引出电极2a---，即使对于金属线7---的长度超过界限的这种IC芯片3、4的尺寸组合，也由于在IC芯片3上备有再布线层6，仍然可使整个金属线7---的长度比界限长度要短些。
而且，因为容易在再布线层6的形成中使用与形成IC芯片3电路同样的工序，就可以在降低成本下以高生产率形成再布线层6。并且，如上所述，基本上只在电路形成面上形成布线层和绝缘膜也行，所以再布线层6的厚度与插入式选择指比较，有压倒性减薄。
并且，在本实施例中，如图1(a)所示，金属线7---的哪一条也没有相互交叉，就进行引线接合。这里要配置成：①将IC芯片3的第2电极焊区6b---以与和各自成对的IC芯片4的外部引出电极4a---的排列顺序相同顺序配置在IC芯片4的周围，和②IC芯片3的第1电极焊区6a---通过连接IC芯片3的外部引出电极3a---与CSP基片2的封装外部引出电极2a---的金属线7---相互之间导通，使封装外部引出电极2a---成对地配置，以便进行引线接合。并且，在该图中，第1电极焊区6a---的配置位置越靠近IC芯片3的边缘，引线接合的距离越短，而且在与IC芯片3相邻的外部引出电极3a---相互之间有余裕，就可以在该区域作成配置第1电极焊区6a---的构成的方法。
进而，通过IC芯片3的外部引出电极3a---、IC芯片4的外部引出电极4a---和CSP基片2的外部引出电极2a---的配置设计，也可以象图2中所示叠式封装11一样金属线7---没有交叉的引线接合。至于该图所示的叠式封装11，在具有外围部分的四个边12～15的IC芯片3，外部引出电极3a---只设置在芯片周围部的相互对向的两个边12、14侧。
并且，与位于边12侧的外部引出电极3a---连接的封装外部引出电极2a---设置在靠近边12的位置，与位于边14侧的外部引出电极3a---连接的封装外部引出电极2a---设置在靠近边14的位置。进而，与IC芯片3的第1电极焊区6a---连接的封装外部引出电极2a---只设置在芯片周围部的相互对向的两个边13、15侧。
并且，IC芯片4的外部引出电极4a---被设置在与图1(a)所示构成同样的位置。因此，与在边13近旁的封装外部引出电极2a---连接的第1电极焊区6a---被配置在边13侧，并且与在边15近旁的封装外部引出电极2a---连接的第1电极焊区6a---，因配置在边15侧，故能很好避免金属线7---的交叉。
这样，为了达成不交叉引线接合，通常，将再布线层6的第1电极焊区6a---和第2电极焊区6b---的配置规定如下就可以。对于第1电极焊区6a---，从半导体芯片(在这里，IC芯片3、4)的叠层上方一侧来看，把第1电极焊区6a---与其引线接合端头(在这里，CSP基片2的封装外部引出电极2a---)连接的连线部分，和将其半导体芯片(在这里为IC芯片3)的外部引出电极(在这里为外部引出电极3a---)与其引线接合端头(在这里为CSP基片2的封装外部引出电极2a---)连接的连线部分，全部要配置成互相以半导体芯片(在这里为IC芯片3、4)的面宽方向来隔开。对于第2电极焊区6b，从叠层的上方一侧来看，把第2电极焊区6b与更上层的半导体芯片(在这里为IC芯片4)的引线接合端头(在这里，为IC芯片的外部引出电极4)连接的连线部分，全部要配置成互相以半导体芯片(在这里为IC芯片3、4)的面宽方向来隔开。
通过这样的第1电极焊区6a---和第2电极焊区6b---的配置，在进行引线接合的时候，在叠层的上下方向哪一条金属线7也不会交叉，而且很容易避免金属线7---相互接触。这里，在再布线层6中，与第1电极焊区6a---和第2电极焊区6b---的配置位置相应，也可以设置成对连接第1电极焊区6a和第2电极焊区6b的布线6c。
因此，半导体芯片的外部引出电极(在这里为IC芯片3的外部引出电极3a---和IC芯片4的外部引出电极4a---)和叠层基台的封装外部引出电极(在这里为CSP基片2的封装外部引出电极2a---)，在一次引线接合中即使作为配置在金属线7---相互接触的位置，，因使用了再布线层6，也不可能使金属线7---相互接触。再布线层6与插入式选择指或多层布线基片比较，制造成本低，其厚度也有压倒性减小。进而，在半导体芯片的电路制造时，也很容易形成再布线层6。
这样，倘采用本实施例，则可以提供一种与叠式封装一样，在多个半导体芯片叠层的构成中，一面抑制封装成本上升、封装厚度增加、和封装生产率的降低，一面可以增加叠层的半导体芯片尺寸的可能组合的半导体装置。并且，可以提供一种一面抑制封装成本上升、封装厚度增加、和封装生产率的降低，一面用为了取得叠层的整个半导体芯片的外部引出电极与封装的外部连接端子的导通而进行的引线接合法，使金属线相互不接触的半导体装置。
[实施例2]
用图3说明体现本发明半导体装置的其它实施例如下。另外，对具有与实施例1所述的构成要素同意功能的构成要素给予同一的标号，并省略其说明。
图3中示出作为本实施例的半导体装置的叠式封装21的构成。该叠式封装21，是由作为半导体芯片的IC芯片22、IC芯片23、和IC芯片24按该顺序叠层的构成，并在IC芯片22和IC芯片23上，设置与实施例1中所述再布线层6同样的再布线层16和再布线层26。按IC芯片22、IC芯片23、和IC芯片24的顺序尺寸由小到大，并分别具有外部引出电极22a---、外部引出电极23a---、和外部引出电极24a---。
在再布线层16上设置有与实施例1的第1电极焊区16a---同样的第1电极焊区16a---、与第2电极焊区6b----同样的第2电极焊区16b---。并且，图未示出的，用与实施例1的布线6c---同样的布线连接第1电极焊区16a---与第2电极焊区16b---。在再布线层26上设置有与实施例1的第1电极焊区6a---同样的第1电极焊区26a---、与第2电极焊区6b---同样的第2电极焊区26b---。并且，图未示出的，用与实施例的布线6c---同样的布线连接第1电极焊区26a---和第2电极焊区26b---。
IC芯片24的外部引出电极24a---与IC芯片23的第2电极焊区26b---连接起来。IC芯片23的第1电极焊区26a---和外部引出电极23a与IC芯片22的第2电极焊区16b---连接起来。IC芯片22的第1电极焊区16a---和外部引出电极22a与CSP基片2的封装外部引出电极2a---连接起来。
这样，在3层的叠层构成中，也介以备有再布线层16、26的IC芯片22、23分成多次进行引线接合的一方，比从上层的IC芯片23、24的外部引出电极23a---、24a---向CSP基片2的封装外部引出电极2a---直接进行引线接合的另一方，每一条金属线7--的长度都能缩短。
因此，对于用一次引线接合连接IC芯片23、24的外部引出电极23a---、24a---与CSP基片2的封装外部引出电极2a---连接时象金属线7---的长度超过界限这样的IC芯片22、23、24的尺寸组合，也因为在IC芯片22、23上备有再布线层16、26，而可以使整个的金属线7---长度比界限小。
而且，在再布线层16、26的形成方面容易使用与IC芯片22、23电路的形成同样的工序，因而能以不太高成本，高生产率形成再布线层16、26。并且，如上所述，基本上只在电路形成面上形成布线层和绝缘膜也行，而且再布线层16、26的厚度与插入式选择指比较也压倒性减小。
以上所述IC芯片的叠层数即使为4层以上，当然也可以应用。
另外，在图3的例子中，除最上层的IC芯片24以外，IC芯片22、23两者上也设有再布线层，但是本发明并不限定于此。这种构成例如，也可以包括四层以上的叠层，即使跨越任何一个或几个IC芯片来进行引线接合，金属线7---的长度也不会超过长度界限，而且在一些IC芯片上也可以不设置再布线层。但是，在除最上层和最下层以外的IC芯片上，理想的是把第1电极焊区和外部引出电极借助于引线接合法连接到一个下层IC芯片的第2电极焊区上去。并且，在最下层的IC芯片上，理想的是把第1电极焊区和外部引出电极借助于引线接合法连接到叠层基台的布线上去。并且，在最上层的IC芯片上，理想的是把外部引出电极借助于引线接合法连接到一个下层的IC芯片的第2电极焊区上去。这是由于决定经由每一层进行全部从IC芯片来的引线接合，可使整个的金属线长度非常短的缘故。
并且，一般地说，增加IC芯片的叠层数，不仅金属线7---的长度，而且随着金属线7---的高低差，即IC芯片的外部引出电极与叠层基台的封装外部引出电极间的高低差的增加，引线接合的难度也成问题。可是，倘采用上述构成，由于至少在一个IC芯片上设置再布线层，把金属线7---的高低差分成多个高低差，因此该问题得以解决。
并且，IC芯片的第2电极焊区，也不一定需要使用作为引线接合用的接合焊区。例如，有时再布线层面积稍稍比一个上层IC芯片大一点，不能保证为引线接合用而设置第1电极焊区和第2电极焊区的两者可以充分露出面积。在这种情况下，仅仅使第1电极焊区露出来，通过把第2电极焊区用作一个上层IC芯片的倒装片接合用的电极，叠层就容易了。
并且，如实施例1所述的那样，为了达成金属线7---引线接合不交叉，第1电极焊区和第2电极焊区的配置也适用于IC芯片的叠层数在3以上的场合。
这样，倘采用本实施例，就可以提供一种如叠式封装的那样，在多个半导体芯片叠层的构成中，一面抑制封装成本的上升、封装厚度的增加、和封装生产率的降低，一面增加叠层半导体芯片尺寸的可能组合的半导体装置。并且，可以提供一种半导体装置，一面抑制封装成本的上升、封装厚度的增加、和封装生产率的降低，一面要使叠层的全部半导体芯片的外部引出电极与封装的外部连接端子之间导通而进行的引线接合中使金属线相互不接触。
如上所述，本发明的半导体装置，在设有外部引出电极的多个半导体芯片叠层，并在上述外部引出电极与上述半导体芯片的叠层基台布线导通的状态下封装的半导体装置中，除最上层的半导体芯片以外，在电路形成面侧就是叠层上方一侧的至少一个半导体芯片中，在上述电路形成面上有配置于芯片周围侧的第1电极焊区、在比第1电极焊区还要靠近一个上层的半导体芯片侧配置第2电极焊区、和连接上述第1电极焊区和上述第2电极焊区的布线的再布线层，在上述电路制造时随着电路形成，并成为避开上述外部引出电极形成的构成。
倘采用上述构成，在叠层的半导体芯片之中除最上层外，在电路形成面一侧就是叠层上方一侧的至少一个半导体芯片上，其电路形成面上形成上述这种再布线层。该再布线层上设置两种电极焊区，芯片周围侧配置第1电极焊区，并在比第1电极焊区还要靠近一个上层的半导体芯片侧配置第2电极焊区。而且，用布线将第1电极焊区和第2电极焊区连接起来。再布线层的形成是在半导体芯片电路制造时随电路的形成继续进行的，而且为半导体芯片制造的一个环节。并且，再布线层是避开外部引出电极形成于电路形成面上，因而在半导体芯片的叠层上方侧的表面上，第1电极焊区、第2电极焊区、和外部引出电极变成全部露出来的状态。
第2电极焊区除可以用作与最上层的半导体芯片之间进行引线接合的接合焊区以外，也可以用作一个上层的半导体芯片的倒装片接合用的电极。把第2电极焊区用作接合焊区时，其电连接可以通过布线，借助于从第1电极焊区来的焊接线进一步使其延长。通过如上所述配置第1和第2电极焊区，通过备有再布线层的半导体芯片，分成多次进行引线接合的一方比起从最上层的半导体芯片向叠层基台的布线上直接进行引线接合来，每一条金属线的长度都要缩小。因此，用一次引线接合连接半导体芯片和叠层基台时，即使对金属线的长度超过界限的半导体芯片的尺寸组合，也由于把备有再布线层的半导体芯片使用于叠层中，所以能够将所有的金属线长度缩小到比其界限长度短。
而且，在形成再布线层中容易使用与形成半导体芯片电路同样的工序，并且能以低成本高生产率形成再布线层。还有，基本上只要在电路形成面上形成金属膜等的布线层和绝缘膜就行，而再布线层的厚度与插入式选择指比较，有压倒性减小。
并且，再布线层的面积稍稍比一个上层半导体芯片大一点，不能保证为引线接合用而设置第1电极焊区和第2电极焊区的两者可以充分露出面积的情况下。在仅使第1电极焊区露出下，通过把第2电极焊区用作一个上层半导体芯片的倒装片接合用的电极，因此很容易叠层。
根据以上，提供一种如叠式封装的那样，在多个半导体芯片叠层的构成中，既能抑制封装成本的上升、封装厚度的增加、和封装生产率的降低，而又可增加叠层的半导体芯片的尺寸的可能组合的半导体装置。
进而本发明的半导体装置，也可以作成分别用引线接合法连接的构成：除最上层的半导体芯片外的全部半导体芯片上都设有上述再布线层，最上层和最下层半导体芯片的上述第1电极焊区和上述外部引出电极，用引线接合法分别与一个下层半导体芯片的上述第2电极焊区连接；并且最下层半导体芯片的上述第1电极焊区和上述外部引出电极，用引线接合法分别与上述叠层基台的布线连接；并且最上层半导体芯片的上述外部引出电极，用引线接合法分别与一个下层半导体芯片的上述第2电极焊区连接。
倘采用上述构成，则把最上层和最下层半导体芯片的第1电极焊区和外部引出电极全部用引线接合法与一个下层半导体芯片的第2电极焊区连接。至于最下层的半导体芯片，把第1电极焊区和外部引出电极用引线接合法与叠层基台的布线连接；并且，至于最上层的半导体芯片，用引线接合法使外部引出电极与一个下层半导体芯片的第2电极焊区连接。因此，变成为经过每一层进行全部的半导体芯片的引线接合，而且可使全部的金属线长度变成非常之短。
进而，本发明的半导体装置，将上述第1电极焊区和上述第2电极焊区使用于引线接合法时，从叠层上方一侧来看，上述第1电极焊区和上述第2电极焊区作成这样配置的构成：所有连接具有上述再布线层的半导体芯片的上述第1电极焊区与上述第1电极焊区的引线接合端头的连线部分和同一半导体芯片的上述外部引出电极与上述外部引出电极的引线接合端头的连线部分，都以半导体芯片的面宽方向互相隔开来；而且所有连接上述第2电极焊区与比上述第2电极焊区更上层的半导体芯片的引线接合原点的连线部分，都以半导体芯片的面宽方向互相隔开。
倘采用上述构成，在把第1电极焊区和第2电极焊区使用于引线接合法时，规定再布线层上两种电极焊区的配置。关于第1电极焊区，从叠层上方一侧来看，要这样配置，使所有连接第1电极焊区与其引线接合端头的连线部分，和连接该半导体芯片的外部引出电极与其引线接合端头的连线部分，都在半导体芯片的面宽方向互相隔开。关于第2电极焊区，从叠层上方一侧来看，要这样配置，使所有连接第2电极焊区与更上层的半导体芯片的引线接合原点的连线部分，都在半导体芯片的面宽方向互相隔开。
由于这样地配置两电极焊区，在进行引线接合时，任何一条金属线可以在叠层上下方向也隔开而不交叉，因此容易避免金属线相互接触。即使在再布线层如所述的那样配置两电极焊区，根据这些电极之间的布线配置位置，可以领着成对的第1电极焊区和第2电极焊区进行连接。因此，半导体芯片的外部引出电极和叠层基台的封装外部引出电极，即使配置在用一次引线接合法金属线相互接触的位置上，也可以使用再布线层，使其相互不会接触。再布线层与插入式选择指或多层布线基片比较，不太增加成本，厚度也压倒性地减小，并且半导体芯片电路制造时容易形成。
根据以上，可以提供一种如叠式封装的那样，在多个半导体芯片叠层的构成中，一面抑制封装成本的上升、封装厚度的增加和封装制造生产率的降低，一面为了要使叠层的全部半导体芯片的外部引出电极与封装的外部引出电极之间的导通而进行引线接合中可使金属线相互不接触的半导体装置。
进而，本发明的半导体装置，也可以制成上述叠层基台为引线架的构成。
倘采用上述构成，则叠层基台为引线架，因而可以把半导体装置制成大量生产型尺寸的封装。
进而，本发明的半导体装置，上述叠层基台也可以制作形成了布线的绝缘性树脂基片的构成。
倘采用本发明，则叠层基台是形成布线的绝缘性树脂基片，因此可以制成CSP等高密度组装型的封装。
在本发明的各项详细说明中所给出的具体实施方案或实施例，始终是使本发明的技术内容更清楚，而不是仅限定于这些具体例子并不应做狭义解释，在本发明的精神和下面所述的权利要求书范围内，可以有各式各样变更使其实施。

Claims (13)

1、一种半导体装置，设置有外部引出电极的多个半导体芯片叠层，并在上述外部引出电极与上述半导体芯片的叠层基台的布线导通的状态下进行封装，其特征是
在至少一个上述半导体芯片的电路形成面上设置：配置于芯片周围侧的第1电极焊区；配置于比上述第1电极焊区要靠近一个上层的半导体芯片侧的第2电极焊区；及具有连接上述第1电极焊区和上述第2电极焊区的布线的再布线层。
2、根据权利要求1所述的半导体装置，其特征是上述第1电极焊区、第2电极焊区和上述再布线层，设置在最上层的半导体芯片以外的至少一个半导体芯片上。
3、根据权利要求1所述的半导体装置，其特征是上述第1电极焊区、第2电极焊区和上述再布线层，设置在电路形成面成为叠层上方一侧的至少一个半导体芯片上。
4、根据权利要求1所述的半导体装置，其特征是上述第1电极焊区、第2电极焊区和上述再布线层，避开上述外部引出电极进行设置。
5、根据权利要求1所述的半导体装置，其特征是上述第1电极焊区、第2电极焊区和上述再布线层，在构成上述半导体芯片的电路制造时，随该电路的形成继续形成。
6、根据权利要求1所述的半导体装置，其特征是在最上层半导体芯片以外的全部半导体芯片上设置上述再布线层，并将最上层和最下层以外的半导体芯片的上述第1电极焊区和上述外部引出电极与一个下层半导体芯片的第2电极焊区电连接；并且，将最下层半导体芯片的上述第1电极焊区和上述外部引出电极与上述叠层基台的布线电连接；并且，最上层半导体芯片的上述外部引出电极与一个下层半导体芯片的上述第2电极焊区电连接起来。
7、根据权利要求6所述的半导体装置，其特征是上述电连接，用引线接合法进行。
8、根据权利要求1所述的半导体装置，其特征是这样配置上述第1电极焊区和上述第2电极焊区，使得连接具有上述再布线层的半导体芯片的上述第1电极焊区与上述第1电极焊区的引线接合端头的连线部分，和连接同一半导体芯片的上述外部引出电极与上述外部引出电极的引线接合端头的连线部分的全部，相互在半导体芯片的面宽方向隔开来。
9、根据权利要求1所述的半导体装置，其特征是这样配置上述第1电极焊区和上述第2电极焊区，使得连接具有上述再布线层的半导体芯片的上述第2电极焊区与上述第2电极焊区的最上层半导体芯片的引线接合端头的连线部分的全部，相互在半导体芯片的面宽方向隔开来。
10、根据权利要求1所述的半导体装置，其特征是上述叠层基台是引线架。
11、根据权利要求1所述的半导体装置，其特征是上述叠层基台是形成布线的绝缘性树脂基片。
12、根据权利要求1所述的半导体装置，其特征是在上述半导体芯片的电路形成面与上述再布线层之间设置有绝缘膜。
13、根据权利要求1所述的半导体装置，其特征是在上述再布线层上的上述布线覆盖着绝缘膜。
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7432585B2 (en) 2005-08-10 2008-10-07 Seiko Epson Corporation Semiconductor device electronic component, circuit board, and electronic device
US7646087B2 (en) 2005-04-18 2010-01-12 Mediatek Inc. Multiple-dies semiconductor device with redistributed layer pads
US7915744B2 (en) 2005-04-18 2011-03-29 Mediatek Inc. Bond pad structures and semiconductor devices using the same
CN102779803A (zh) * 2011-05-10 2012-11-14 立锜科技股份有限公司 集成电路芯片封装及其制造方法
CN101355067B (zh) * 2007-07-23 2012-11-21 三星电子株式会社 多芯片模块的改进的电连接
CN104769709A (zh) * 2012-07-23 2015-07-08 马维尔国际贸易有限公司 涉及包括多存储器裸片的半导体封装体的方法和布置

Families Citing this family (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4570809B2 (ja) * 2000-09-04 2010-10-27 富士通セミコンダクター株式会社 積層型半導体装置及びその製造方法
JP2002373969A (ja) * 2001-06-15 2002-12-26 Oki Electric Ind Co Ltd 半導体装置及び半導体装置の製造方法
JP4738675B2 (ja) * 2001-09-14 2011-08-03 ルネサスエレクトロニクス株式会社 半導体装置
KR100470387B1 (ko) * 2001-10-05 2005-02-07 주식회사 하이닉스반도체 적층 칩 패키지
US8089142B2 (en) 2002-02-13 2012-01-03 Micron Technology, Inc. Methods and apparatus for a stacked-die interposer
US7109588B2 (en) * 2002-04-04 2006-09-19 Micron Technology, Inc. Method and apparatus for attaching microelectronic substrates and support members
EP1434264A3 (en) * 2002-12-27 2017-01-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method using the transfer technique
JP4615189B2 (ja) * 2003-01-29 2011-01-19 シャープ株式会社 半導体装置およびインターポーザチップ
US7095103B1 (en) * 2003-05-01 2006-08-22 Amkor Technology, Inc. Leadframe based memory card
JP2005039161A (ja) * 2003-07-18 2005-02-10 System Fabrication Technologies Inc 半導体集積回路チップの三次元高密度実装方式
JP3880572B2 (ja) * 2003-10-31 2007-02-14 沖電気工業株式会社 半導体チップ及び半導体装置
JP4103796B2 (ja) * 2003-12-25 2008-06-18 沖電気工業株式会社 半導体チップパッケージ及びマルチチップパッケージ
JP2005236176A (ja) * 2004-02-23 2005-09-02 Torex Semiconductor Ltd 電極パッケージ及び半導体装置
CN100511672C (zh) * 2004-03-25 2009-07-08 日本电气株式会社 芯片层叠型半导体装置
KR100843137B1 (ko) 2004-12-27 2008-07-02 삼성전자주식회사 반도체 소자 패키지
EP2063596B1 (en) 2005-03-21 2018-03-07 QUALCOMM Incorporated Joint packet detection in a wireless communication system with one or more receiver
JP4508947B2 (ja) * 2005-05-30 2010-07-21 Ｏｋｉセミコンダクタ株式会社 半導体装置の自動設計方法および自動設計装置
US20060289981A1 (en) * 2005-06-28 2006-12-28 Nickerson Robert M Packaging logic and memory integrated circuits
KR100780661B1 (ko) * 2005-06-29 2007-11-29 주식회사 하이닉스반도체 비휘발성 메모리 소자의 유전체막 및 그 형성방법
JP4703300B2 (ja) * 2005-07-20 2011-06-15 富士通セミコンダクター株式会社 中継基板及び当該中継基板を備えた半導体装置
SG130055A1 (en) * 2005-08-19 2007-03-20 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
KR100690922B1 (ko) 2005-08-26 2007-03-09 삼성전자주식회사 반도체 소자 패키지
SG130066A1 (en) 2005-08-26 2007-03-20 Micron Technology Inc Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices
JP4137929B2 (ja) * 2005-09-30 2008-08-20 シャープ株式会社 半導体装置
JP4268607B2 (ja) 2005-09-30 2009-05-27 富士通マイクロエレクトロニクス株式会社 半導体装置に配設される中継部材及び半導体装置
KR100648040B1 (ko) 2005-11-25 2006-11-23 삼성전자주식회사 다수의 금속 랜드를 가지는 인터포저 기판, 및 이로부터제작되는 인터포저를 포함하는 적층 칩 패키지
US7714450B2 (en) * 2006-03-27 2010-05-11 Marvell International Technology Ltd. On-die bond wires system and method for enhancing routability of a redistribution layer
JP4910512B2 (ja) * 2006-06-30 2012-04-04 富士通セミコンダクター株式会社 半導体装置および半導体装置の製造方法
US8138591B2 (en) * 2006-09-23 2012-03-20 Stats Chippac Ltd Integrated circuit package system with stacked die
US8922028B2 (en) * 2007-02-13 2014-12-30 Advanced Semiconductor Engineering, Inc. Semiconductor package
JP2007214582A (ja) * 2007-03-29 2007-08-23 Sharp Corp 半導体装置およびインターポーザチップ
US7863090B2 (en) * 2007-06-25 2011-01-04 Epic Technologies, Inc. Packaged electronic modules and fabrication methods thereof implementing a cell phone or other electronic system
US20090051019A1 (en) * 2007-08-20 2009-02-26 Chih-Feng Huang Multi-chip module package
US7768138B2 (en) 2007-10-23 2010-08-03 Panasonic Corporation Semiconductor device
JP5548342B2 (ja) * 2007-10-23 2014-07-16 パナソニック株式会社 半導体装置
JP2009158750A (ja) * 2007-12-27 2009-07-16 Fujifilm Corp ワイヤボンディング方法及び半導体装置
JP4774075B2 (ja) * 2008-04-18 2011-09-14 富士通セミコンダクター株式会社 半導体装置に配設される中継部材及び半導体装置
JP4536808B2 (ja) * 2008-09-08 2010-09-01 シャープ株式会社 半導体装置およびインターポーザチップ
US20110012239A1 (en) * 2009-07-17 2011-01-20 Qualcomm Incorporated Barrier Layer On Polymer Passivation For Integrated Circuit Packaging
US8169065B2 (en) * 2009-12-22 2012-05-01 Epic Technologies, Inc. Stackable circuit structures and methods of fabrication thereof
US9196509B2 (en) 2010-02-16 2015-11-24 Deca Technologies Inc Semiconductor device and method of adaptive patterning for panelized packaging
US8656333B1 (en) * 2010-02-16 2014-02-18 Deca Technologies, Inc. Integrated circuit package auto-routing
US8799845B2 (en) 2010-02-16 2014-08-05 Deca Technologies Inc. Adaptive patterning for panelized packaging
JP2012212417A (ja) * 2011-03-24 2012-11-01 Toshiba Corp 半導体メモリカード
JP2012222326A (ja) * 2011-04-14 2012-11-12 Elpida Memory Inc 半導体装置
JP2014060185A (ja) 2012-09-14 2014-04-03 Toshiba Corp 半導体装置の製造方法および半導体装置
WO2015087705A1 (ja) * 2013-12-10 2015-06-18 ソニー株式会社 半導体装置、固体撮像素子、撮像装置および電子機器、並びにそれらの製造方法
JP6560496B2 (ja) * 2015-01-26 2019-08-14 株式会社ジェイデバイス 半導体装置
JP1582228S (zh) * 2016-08-02 2017-07-24
US10157803B2 (en) 2016-09-19 2018-12-18 Deca Technologies Inc. Semiconductor device and method of unit specific progressive alignment
US10573601B2 (en) 2016-09-19 2020-02-25 Deca Technologies Inc. Semiconductor device and method of unit specific progressive alignment
USD872033S1 (en) * 2018-09-14 2020-01-07 Telit Communications S.P.A. Connection module
USD872032S1 (en) * 2018-09-14 2020-01-07 Telit Communications S.P.A. Connection module
JP1664282S (zh) * 2019-07-24 2020-07-27
USD938925S1 (en) * 2019-10-24 2021-12-21 Nuvoton Technology Corporation Japan Semiconductor device
USD934820S1 (en) * 2019-10-24 2021-11-02 Nuvoton Technology Corporation Japan Semiconductor device
USD951212S1 (en) * 2019-12-11 2022-05-10 Panasonic Semiconductor Solutions Co., Ltd. Semiconductor device
USD951214S1 (en) * 2019-12-11 2022-05-10 Panasonic Semiconductor Solutions Co., Ltd. Semiconductor device
USD951213S1 (en) * 2019-12-11 2022-05-10 Panasonic Semiconductor Solutions Co., Ltd. Semiconductor device
USD951215S1 (en) * 2019-12-11 2022-05-10 Panasonic Semiconductor Solutions Co., Ltd. Semiconductor device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62165350A (ja) * 1986-01-17 1987-07-21 Nec Corp 多層配線基板
JPH04284663A (ja) 1991-03-13 1992-10-09 Toshiba Corp 半導体装置
WO1995005676A1 (en) * 1993-08-13 1995-02-23 Irvine Sensors Corporation Stack of ic chips as substitute for single ic chip
KR100231276B1 (ko) * 1996-06-21 1999-11-15 황인길 반도체패키지의 구조 및 제조방법
JP3545200B2 (ja) * 1997-04-17 2004-07-21 シャープ株式会社 半導体装置
JP3867875B2 (ja) 1997-09-17 2007-01-17 ソニー株式会社 半導体装置
JP2000208698A (ja) * 1999-01-18 2000-07-28 Toshiba Corp 半導体装置
US6351028B1 (en) * 1999-02-08 2002-02-26 Micron Technology, Inc. Multiple die stack apparatus employing T-shaped interposer elements
US6118176A (en) * 1999-04-26 2000-09-12 Advanced Semiconductor Engineering, Inc. Stacked chip assembly utilizing a lead frame
US6221682B1 (en) * 1999-05-28 2001-04-24 Lockheed Martin Corporation Method and apparatus for evaluating a known good die using both wire bond and flip-chip interconnects

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7646087B2 (en) 2005-04-18 2010-01-12 Mediatek Inc. Multiple-dies semiconductor device with redistributed layer pads
US7915744B2 (en) 2005-04-18 2011-03-29 Mediatek Inc. Bond pad structures and semiconductor devices using the same
US7432585B2 (en) 2005-08-10 2008-10-07 Seiko Epson Corporation Semiconductor device electronic component, circuit board, and electronic device
CN101355067B (zh) * 2007-07-23 2012-11-21 三星电子株式会社 多芯片模块的改进的电连接
CN102779803A (zh) * 2011-05-10 2012-11-14 立锜科技股份有限公司 集成电路芯片封装及其制造方法
CN104769709A (zh) * 2012-07-23 2015-07-08 马维尔国际贸易有限公司 涉及包括多存储器裸片的半导体封装体的方法和布置

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