CN1309035C - 减少SiGe衬底上应变Si中N+扩散的方法 - Google Patents

减少SiGe衬底上应变Si中N+扩散的方法 Download PDF

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CN1309035C
CN1309035C CNB2004100624730A CN200410062473A CN1309035C CN 1309035 C CN1309035 C CN 1309035C CN B2004100624730 A CNB2004100624730 A CN B2004100624730A CN 200410062473 A CN200410062473 A CN 200410062473A CN 1309035 C CN1309035 C CN 1309035C
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D·奇丹巴尔拉奥
O·H·多库马奇
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Abstract

本发明提供一种减少SiGe衬底上应变Si中N+扩散的方法。在SiGe衬底的上表面中形成第一源和漏区。第一源和漏区含有N型杂质。为减少第一源和漏区中含有的N型杂质的扩散，降低第一源和漏区中的空位浓度。通过第一源和漏区中的填隙元素或空位俘获元素降低空位浓度。通过离子注入提供填隙元素或空位俘获元素。

Description

减少SiGe衬底上应变Si中N+扩散的方法
技术领域
本发明涉及用于制造器件性能得到提高的半导体器件和展示出器件性能得到提高的器件结构的方法，尤其涉及用于制造展示出减少了N型杂质扩散的基于SiGe的器件的方法。
技术背景
对超大规模集成半导体器件的日益增加的需求，要求晶体管的性能和密度不断提高。随着器件尺寸的缩小达到极限，人们转为寻找能够提高器件性能的新材料和方法。优选方法之一是通过增加迁移率。
众所周知，在NFET器件中，对沟道区施加的双轴张应力增加了电子迁移率。这点可通过构建NFET器件实现，NFET器件由衬底上的一组层叠膜(如，硅-SiGe-硅)构成。从硅衬底开始，在硅衬底上生长SiGe。通常使用缓冲层来减少可以导致器件泄漏的螺旋位错缺陷密度，但是由于失配位错的形成，仍然达到了充分的弛豫。SiGe膜得到弛豫，从而具有比硅大的晶格常数。当接着在SiGe上淀积硅时，硅遵从弛豫SiGe的更大晶格，并受到双轴张力。沟道被完全容纳在应变硅中，并提高了电子迁移率。
然而，基于SiGe的衬底展示出某些缺陷，尤其当在其上形成NFET器件时。为了形成NFET器件，将N型杂质(如，As或P)离子注入到基于SiGe的衬底，以形成有源区(如，源和漏区)。这里，SiGe层中含有的大量空位不希望地增加了注入的N型杂质的扩散。这使得实现一致的频响跌落(roll-off)器件特性更加困难了。因此，需要更有效的用于制造基于SiGe的半导体器件的方法。
发明内容
本发明的一方面，提供了一种制造半导体器件的方法。该方法包括在基于SiGe的衬底的上表面形成源和漏延伸区的步骤。源和漏延伸区含有N型杂质。然后，为减少源和漏延伸区中含有的N型杂质的扩散，降低源和漏延伸区中的空位浓度。通过向源和漏延伸区提供填隙元素或空位俘获元素来降低空位浓度。
本发明的另一方面，提供了一种减少基于SiGe的衬底中N型杂质的扩散的方法。源和漏延伸区位于基于SiGe的衬底的上表面。将填隙元素或空位俘获元素离子注入到源和漏延伸区，以降低源和漏延伸区中的空位浓度。
本发明的再一方面为具有基于SiGe的衬底的半导体器件。在基于SiGe的衬底上形成栅极，在其二者之间具有栅氧化物。在SiGe衬底的上表面形成含有N型杂质的源和漏延伸区。与源和漏延伸区对应形成低空位区，低空位区含有填隙元素或空位俘获元素。
附图说明
通过参考附图对本发明的优选实施例的下述详细说明，将更好地理解前述和其它优点，其中：
图1到7按顺序描述了根据本发明的实施例的方法的诸阶段。
具体实施方式
本发明提供了一种方法，该方法显著减少了基于SiGe的衬底中N型杂质的不希望的扩散，从而提高了器件的频响跌落特性。在一实施例中，通过减少源和漏延伸区中的空位，减少了N型杂质的扩散。通过向源和漏延伸区提供填隙元素(如，Si或O)或空位俘获元素(如，F、N、Xe、Ar、He、Kr或惰性气体元素)来减少空位。
通常，填隙元素在提供的每个离子处产生一个额外的空隙，这些额外的空隙与基于SiGe的衬底中过剩的空位作用并湮灭它们。空位俘获元素俘获空位并形成基于空位的簇。因为空位或者由填隙元素湮灭，或者由空位俘获元素俘获，降低了空位浓度，从而减少了源和漏区中N型杂质的扩散。
图1示出了在硅衬底10上形成的包括SiGe层12的基于SiGe的衬底。在一实施例中，在硅衬底10上通过多次形成缓冲层的生长步骤形成总厚度通常为约200到20000的SiGe层12。然后使SiGe层12弛豫。通过在SiGe层12上生长，在SiGe层12上形成约30到400厚的Si帽盖层14。然后，在张力下使Si帽盖层14双轴应变以匹配下面的弛豫的SiGe晶格。在Si帽盖层14上形成栅氧化层16。基于SiGe的衬底被划分为NMOS区和PMOS区，其中分别形成NMOS器件和PMOS器件。
图2示出了在栅氧化层16上形成的栅极18。因为本发明针对于N型器件，有选择地在PMOS区上形成掩膜22，以在后序处理步骤中保护其中的PMOS器件。图2还示出了在栅极18的侧面上形成的可选择的侧壁20，用于在后序离子注入步骤中保护栅极18。
图3只示出了图2中的NMOS区，其中如箭头“A”所示，将N型杂质(如，As或P)离子注入到Si帽盖层14的上表面，以在基于SiGe的衬底的表层部分形成源和漏延伸区24。如其中所示，通过将栅极18用作掩膜，离子注入以自对准的方式进行，注入浓度约为1×1014原子/cm2到1×1016原子/cm2，注入能量约为0.3KeV到50KeV。注入的N型杂质的浓度峰值形成于距Si帽盖层的上表面约10到1000的深度。
如上所述，显著地和不希望地提高了在基于SiGe的衬底中N型杂质(如，As或P)的扩散，因为其中基于空位的机制更加显著。为解决该问题，如图4所示，将填隙元素(如，Si或O)或空位俘获元素(如，F、N、Xe、Ar、He、Kr或者其它惰性气体元素)离子注入到源和漏延伸区24，如箭头“B”所示，以形成与源和漏延伸区24基本重叠的低空位区26。
一旦注入，这种方式会造成损伤，一旦对损伤进行退火，空隙湮灭掉过剩的空位，从而降低了延伸区24中的空位浓度。类似地，注入的空位俘获元素俘获过剩的空位并形成基于空位的簇，从而降低源和漏延伸区24中的空位浓度。在此阶段的退火是可选的。
在一实施例中，以约1×1014原子/cm2到1×1016原子/cm2的注入浓度和约0.3KeV到100KeV的注入能量离子注入填隙元素或空位俘获元素。注入的填隙元素或空位俘获元素的浓度峰值形成于距Si帽盖层的上表面约5到2000的深度。通常，填隙元素或空位俘获元素的注入分布将完全包括N型杂质分布。注入的填隙元素或空位俘获元素的浓度峰值可接近于N型杂质峰值，以最大化扩散延迟。
无须在注入填隙元素或空位俘获元素之前形成源和漏延伸区24。可以在形成源和漏延伸区24之前形成低空位区26。然后可以进行退火，以同时激活注入的杂质和元素，从而控制通过空位中介机制的扩散。也可以在处理步骤之后(如，在源和漏形成之后)或在制作过程完成之后进行退火。
如图5所示，在形成侧壁隔板28之后，如箭头“C”所示，将N型杂质离子注入到基于SiGe的衬底，以形成源和漏区30，如图6所示。源和漏区30分别与源和漏延伸区24重叠。通过将栅极18和侧壁隔板28用作掩膜，N型杂质以自对准方式离子注入。在一实施例中，通过离子注入N型杂质形成源和漏区30，注入浓度约为1×1014原子/cm2到1×1016原子/cm2，注入能量约为0.3KeV到50KeV。
图7示出了离子注入填隙元素或空位俘获元素(如，F、N、Xe、Ar、He、Kr或者惰性气体元素)的可选步骤，如箭头“D”所示，以形成与源和漏区30对应的基于SiGe的衬底的低空位区32，以便降低基于SiGe的衬底中的空位浓度。在一实施例中，通过离子注入填隙元素或空位俘获元素形成低空位区32，注入浓度约为1×1014原子/cm2到1×1016原子/cm2，注入能量约为0.3KeV到100KeV。然而，如果通过如图4所示的前述离子注入步骤，已经充分降低了基于SiGe的衬底中的空位浓度，则该步骤可以不是必需的。此外，区30和32中N型注入与填隙元素或空位俘获元素的峰值可以在其顶部对准，或根据扩散控制移位。
进行退火以激活注入的杂质，并修复由注入填隙元素或空位俘获元素及源和漏注入引起的注入损伤。在一实施例中，退火在约700℃到1200℃的温度下进行约1秒到3分钟。这包括全部可能的退火，包括峰值退火、快速热退火、以及炉内退火。
如上所述，本发明提供了显著减少基于SiGe的衬底中N型杂质的不希望的扩散的方法。通过减少源和漏延伸区中的空位，减少N型杂质的扩散。通过向源和漏延伸区提供填隙元素或空位俘获元素减少了空位。注入的填隙元素产生额外的空隙，所述空隙与基于SiGe的衬底中的过剩的空位作用并湮灭它们。注入的空位俘获元素俘获空位并形成基于空位的簇。因为空位或者由填隙元素湮灭，或者由空位俘获元素俘获，空位浓度降低，并减少了源和漏区中N型杂质的扩散，从而提高了器件的频响跌落的特性。
尽管根据实施例说明了本发明，本领域的技术人员将认识到，可以在所附权利要求书的精神和范围内对发明进行修改。

Claims (20)

1.一种制造半导体器件的方法，包括以下步骤：
在基于SiGe的衬底的上表面形成源和漏延伸区，源和漏延伸区含有N型杂质；以及
降低源和漏延伸区中的空位浓度，以减少源和漏延伸区中含有的N型杂质的扩散。
2.根据权利要求1的方法，其中降低空位浓度的步骤包括在源和漏延伸区中提供填隙元素或空位俘获元素的步骤。
3.根据权利要求2的方法，其中填隙元素为Si或O，以及空位俘获元素为F、N、Xe、Ar、He、Kr或者惰性气体元素。
4.根据权利要求2的方法，其中提供填隙元素或空位俘获元素的步骤包括在基于SiGe的衬底上离子注入填隙元素或空位俘获元素的步骤。
5.根据权利要求4的方法，其中离子注入填隙元素或空位俘获元素的步骤包括以1×1014atoms/cm2到1×1016atoms/cm2的注入浓度和0.3KeV到100KeV的注入能离子注入填隙元素或空位俘获元素的步骤。
6.根据权利要求5的方法，其中SiGe衬底包括在硅衬底上的SiGe膜上的Si盖层。
7.根据权利要求6的方法，其中在源和漏延伸区中，填隙元素或空位俘获元素的浓度峰值与N型杂质的浓度峰值形成于距Si盖层的上表面基本相同的深度。
8.根据权利要求7的方法，其中填隙元素或空位俘获元素的浓度峰值形成于距Si盖层的上表面5到2000的深度。
9.根据权利要求4的方法，还包括在所述离子注入步骤之后的退火步骤。
10.根据权利要求9所述的方法，其中退火步骤在700℃到1200℃的温度下进行1秒到3分钟。
11.根据权利要求1的方法，还包括在基于SiGe的衬底的上表面形成栅极的步骤，在其二者之间具有栅氧化膜。
12.根据权利要求1的方法，还包括在基于SiGe的衬底的上表面形成源和漏区的步骤，源和漏区含有N型杂质，并与源和漏延伸区重叠。
13.根据权利要求12的方法，还包括在源和漏区提供填隙元素或空位俘获元素的步骤。
14.根据权利要求13的方法，其中填隙元素为Si或O，以及空位俘获元素为F、N、Xe、Ar、He、Kr或者惰性气体元素。
15.根据权利要求14的方法，其中在源和漏区提供填隙元素或空位俘获元素的步骤包括离子注入填隙元素或空位俘获元素的步骤。
16.一种减少基于SiGe的衬底中N型杂质的扩散的方法，该方法包括以下步骤：
在基于SiGe的衬底的上表面形成源和漏延伸区；以及
向源和漏延伸区离子注入填隙元素或空位俘获元素，以降低源和漏延伸区中的空位浓度。
17.根据权利要求16的方法，其中填隙元素为Si或O，以及空位俘获元素为F、N、Xe、Ar、He、Kr或者惰性气体元素。
18.根据权利要求16的方法，还包括形成源和漏区的步骤。
19.一种半导体器件，包括：
基于SiGe的衬底；
在基于SiGe的衬底上形成的栅极，在其二者之间具有栅氧化物；
在SiGe衬底的上表面形成的源和漏延伸区，其中含有N型杂质；以及
与源和漏延伸区对应形成的低空位区，其中含有填隙元素或空位俘获元素。
20.根据权利要求19的半导体器件，其中填隙元素为Si或O，以及空位俘获元素为F、N、Xe、Ar、He、Kr或者惰性气体元素。
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