CN1307560C - Data picking method and system thereof - Google Patents
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- CN1307560C CN1307560C CNB2004100315915A CN200410031591A CN1307560C CN 1307560 C CN1307560 C CN 1307560C CN B2004100315915 A CNB2004100315915 A CN B2004100315915A CN 200410031591 A CN200410031591 A CN 200410031591A CN 1307560 C CN1307560 C CN 1307560C
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Abstract
The present invention relates to a data retrieval method which is suitable for a data retrieval system. The data retrieval system comprises a processor, a north bridge chip, an end point device of PCI-Express, a direct memory access buffer area and a cache, wherein the cache is used for storing data comprising partial written-back and invalidated data; the written back data in the cache is stored in the direct memory access buffer area; the end point device which indicates the PCI-Express uses a non-snoop transaction technique to read the data stored in the direct memory access buffer area. When the north bridge chip receives a non-snoop reading requirement, the data stored in the direct memory access buffer area is directly retrieved without snooping on the processor.
Description
Technical field
The present invention relates to a kind of DAQ method, particularly relate to a kind of data transmission method of supporting non-supervising (non-snoop) treatment technology.
Background technology
In general, present computer system all has one or more processor units, and each processor all can have exclusive high-speed cache.High-speed cache is that small-sized a, speed is fast, expensive, the internal memory of zero wait state, is used for depositing the program code and the data that often use.In addition, high-speed cache is situated between and is connected between the relevant processor and system bus, is used for bridge joint processor cycle length and at a slow speed memory access time fast.
Because advanced electronic product, to the demand on speed and the frequency range, a kind of non-treatment technology (non-snoop transaction) that supervises is suggested, with so that north bridge chips, must not supervise (snoop) processor, and read or write direct memory access (direct memory access, DMA) impact damper of primary memory.The non-treatment technology that supervises has two big advantages, and processor bus (CPU bus) can allow other primary controller use, and access delay (access latency) can be expected.
For instance, when reading of data, using the non-primary controller that supervises treatment technology, all is by primary memory (DRAM) reading of data forever, so can be contemplated to the delay (read-DRAM-latency) of reading DRAM.But using the primary controller that supervises treatment technology (snoop transaction), just might be delay (read-DRAM-latency) of reading DRAM or the delay (snoop-CPU-latency) that monitors CPU.When writing data, use the non-primary controller that supervises treatment technology, all be that data are write primary memory, for example by write-back (post write) technology.But use the primary controller supervise treatment technology, if the result who monitors overrides (hit dirty) for data, so want waiting for CPU write back high-speed cache, and with the data integration of north bridge chips after, be then written to primary memory.If the result who monitors not is that data override (not hit dirty), when supervise finish after, then carry out data write-back (post write).
Several methods is arranged traditionally, use so that north bridge chips must not supervise (snoop) processor (CPU) by the non-treatment technology (non-snoop transaction) that supervises, and read or write the dma buffer of primary memory.Yet classic method is not that usefulness is not good, has the conforming problem of cached data (cache coherency issue) exactly.
Summary of the invention
In view of this, primary and foremost purpose of the present invention is the timely usefulness (realtime performance) during improving non-supervision handles, and keeps the cached data consistance simultaneously.
For realizing above-mentioned purpose of the present invention, the invention provides a kind of data picking method, be applicable to that a data acquisition system contains the end-point devices of a processor, a north bridge chips, a PCI-Express (endpoint device), direct memory access buffer zone (DMA buffer) and a high-speed cache in order to store data, comprise partly write-back and ineffective treatment (partial write back and invalidate) high-speed cache, wherein in the high-speed cache by the deposit data of write-back to the direct memory access buffer zone; The end-point devices of indication PCI express is used a non-treatment technology (non-snoop transaction) that supervises, and reads the data of direct memory access buffer zone; And receive one non-ly when supervising reading requirement when north bridge chips, do not supervise processor, and directly capture the data in the direct memory access buffer zone.
For realizing above-mentioned purpose of the present invention, the present invention also provides a kind of data acquisition system, comprises the end-point devices of a PCI-Express; One north bridge chips couples the end-point devices of PCI-Express; One primary memory couples above-mentioned north bridge chips, has at least one direct memory access buffer zone; One high-speed cache is in order to storage data; An and processor, sequencing is with the partial data in the high-speed cache, be written back in the direct memory access buffer zone, and the above-mentioned partial data in the ineffective treatment high-speed cache, and the end-point devices of indication PCI express uses a non-treatment technology that supervises, and reads the data of direct memory access buffer zone, and it is one non-when supervising reading requirement to make north bridge chips receive, must not supervise processor, directly capture the data in the direct memory access buffer zone.
For realizing above-mentioned purpose of the present invention, the present invention also provides a kind of data acquisition system, comprises a high-speed cache, in order to storage data; One processor couples high-speed cache; The end-point devices of one PCI-Express; One primary memory has at least one direct memory access buffer zone; An and north bridge chips, couple the end-point devices of PCI-Express, in order to cause processor with the partial data in the high-speed cache, be written back in the direct memory access buffer zone, and the above-mentioned partial data in the ineffective treatment high-speed cache, and the end-point devices of indication PCI-Express is used a non-treatment technology that supervises, read the data of direct memory access buffer zone, it is one non-when supervising reading requirement to make north bridge chips receive, must not supervise processor, directly capture the data in the direct memory access buffer zone.
For above and other objects of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and be described with reference to the accompanying drawings as follows.
Description of drawings
Fig. 1 is the synoptic diagram of data acquisition system of the present invention.
Fig. 2 is the process flow diagram of data picking method of the present invention.
The reference numeral explanation
10: processor; 12: high-speed cache;
13: system bus; 14: north bridge chips;
15: rambus; 16: primary memory;
18: the direct memory access buffer zone; 21:PCI-Express link;
The end-point devices of 20:PCI-Express.
Embodiment
In general, when a processor sends a reading requirement, and desired data are when being present in its high-speed cache, promptly take place one and get soon and read success (cache read hit), microprocessor can not must accessing main memory, and by obtaining data in the high-speed cache.Get soon and read failure (cache read miss) if desired data when not being present in its high-speed cache, promptly take place one, and request memory can be forwarded to system, not exist, be used as by acquisition data in the primary memory as high-speed cache.Read failure (cache read miss) when taking place getting soon, by the data that capture in the primary memory since statistics go up these data can be by the processor possibility of access again, so also can be written in the high-speed cache.Similarly, write when requiring when a processor sends one, the data that (in a write-back cache time) writes can be written in the high-speed cache, and must be on system bus accessing main memory.The use that this can increase the usefulness of processor and reduce system bus provides other processor and bus master controller more frequency range.
An efficient cache systems can have high success rate (hit rate), just in whole memory access process, gets the ratio height of success soon.When a fast taking system has high success rate, most access all can be used as the service of zero-waiting.Therefore, be away from a processor of its regional internal memory (local memory) operation, can have very low " bus use (bus utilization) ", this will reduce bus and is taken by processor, uses other bus master controller to have more effective frequency range.In addition, when processor need not control bus, it can be away from its scoped memory operation, to increase the efficient of computer system.
Typical fast taking system has two kinds, is respectively " all writing formula cache systems (write-through cache system) " and " write-back cache system (write-backcache system) ".In write-through cache system, writing data and can being written in the high-speed cache of from processor also can be written in the primary memory at once.So can guarantee the data in the high-speed cache, with the consistance of data in the primary memory.Yet the shortcoming of write-through cache system is all to need to take system bus for writing of processor each time.
In write-back cache system, the writing data and only can be written in the high-speed cache of from processor, and when these data of other matching requirements, or will be substituted because new data requires the time, just can be written back in the primary memory.When the writing data and only be written in the high-speed cache of processor, leave the data on the corresponding address in the primary memory in, with being regarded as old, lost efficacy.The data of the position of high-speed cache in order to remember to revise.In write-back cache system, when using bus, need get controller soon and supervise (snoop) at other bus master controller.
In general, get the management that controller carries out high-speed cache soon by one.The most important management policy of high-speed cache is exactly the consistance (coherency) of maintaining cached data.The consistance of high-speed cache just is meant that any bus unit can receive the data of latest edition.
In the independent bus line primary controller can the computer system of accessing main memory, possible bus master controller, for example another processor, direct access controller, network or magnetic disc adaptation card or image processing cards will be revised the content with the identical host memory location of high-speed cache.When this situation took place, high-speed cache then can be considered as having the data of inefficacy.Problem will take place if processor reads invalid data because of carelessness.Therefore,, when processor does not have control bus, get controller soon by one and come the monitoring system bus, see if there is other bus master controller accessing main memory and be necessary in order to keep the consistance of high-speed cache.The technology that this supervises bus is to be called snooping.
In write-back cache system, because writing (previousprocessor write), previous processor changed the data in the high-speed cache (not being updated in the primary memory as yet), therefore in the cycle that primary memory is read by a bus master controller, getting controller soon still must the monitoring system bus, is called " read and supervise (read snooping) ".Reading under the situation that supervises successfully (read snoophit), promptly high-speed cache contains the data that are not updated to as yet in the primary storage, and in general getting controller soon can provide relevant data to primary memory and the bus that claims.
In write cycle,, still need the monitoring system bus at internal memory, be called " write and supervise (writesnooping) " so get controller soon because bus master controller can write or revise the position that is present in internal memory in the high-speed cache.Read under the situation that supervises successfully (write snoop hit), any is denoted as the project of getting soon (cache entry) of invalid (invalid) in the controller getting soon, represent that this project is not correct, or this high-speed cache upgraded together with primary memory.
Therefore, in write-back cache system, when a bus master controller reads or writes a primary memory, or in write-through cache system, when a bus master controller writes a primary memory, whether get controller soon and must pin alliance, looking at has in the high-speed cache of being present in by the position of the primary memory of access.If come locational since then data to be present in the high-speed cache, get controller soon and then can read to supervise successfully (read snoop hit) or write and supervise successfully (write snoop hit) according to what taken place, take suitable action.This can be avoided being stored in the data of out-of-date in primary memory and the high-speed cache (stale), by the consistance of keeping high-speed cache.Though, in write-back cache system, when bus master controller reads and write primary memory, all needing the monitoring system bus, its system effectiveness is better than write-through cache system.
It shown in Fig. 1 the synoptic diagram of data acquisition system of the present invention.Data acquisition system 100 comprises the end-point devices (endpoint device) 20 of a processor 10, a high-speed cache 12, a north bridge chips 14, a direct memory access buffer zone (DMAbuffer) 18, a PCI-Express.
In the present embodiment, the end-point devices 20 of PCI-Express is in order to as a bus master controller, yet is not in order to limit the present invention.Processor 10 is coupled to north bridge chips 14 by a system bus 13, north bridge chips 14 is by a rambus 15 primary memorys 16 (containing direct memory access buffer zone 18), and north bridge chips 14 is coupled to the end-point devices 20 of PCI-Express by a PCI-Express link21.For instance, the end-point devices 20 of PCI-Express is another processor, direct access controller, network or magnetic disc adaptation card or image processing cards or the like.In addition, primary memory 16 is cut apart the DMA buffer zone 18 of a part as non-supervision processing (non-snooped), and DMA buffer zone 18 is set for and can be carried out data access in the mode that writes back (write back) by high-speed cache 12.
Fig. 2 is the process flow diagram of data picking method of the present invention.Desire to read processing (non-snoop read transaction) when DMA buffer zone 18 is read when a software or driver, then carry out step S10 earlier, partly write back and ineffective treatment high-speed cache 12 by non-supervising.
In traditional write back cache system, if will be in primary memory 16 with the Data Update that had been modified in the high-speed cache 12, then must by processor 10 go to carry out one " high-speed cache write back and ineffective treatment (cache write back and invalidate; WBINV) " instruction empties (flush) whole high-speed cache 12, and the data that are about to be modified in the high-speed cache 12 all are updated in the primary memory 16.
Yet, if this software (or driver) only will carry out access to DMA buffer zone 18, just therefore with the Data Update in the whole high-speed cache 12 to primary memory 16 (containing DMA buffer zone 18), promptly carry out " writing back and ineffective treatment (WBINV) of high-speed cache " instruction by processor 10, and empty (flush) whole high-speed cache 12, will cause timely usefulness (real time performance) not good.So the present invention only partly writes back and ineffective treatment high-speed cache 12, with the Data Update relevant with DMA buffer zone 18 to DMA buffer zone 18, so that above-mentioned software (driver) reading DMA buffer zone 18.
Providing two kinds of methods to come performing step S10 in the present invention, so is not in order to limit the present invention.Be to adopt first kind of mode to come performing step S10 in this embodiment, promptly increase by a new instruction and give processor 10 that this instruction is called that " part of high-speed cache writes back and ineffective treatment (partial cache write back andinvalidate; PWBINV) ", in order to according to first, second address information, with the partial data in the high-speed cache 12, write back in the DMA buffer zone 18 after, the above-mentioned partial data in the ineffective treatment high-speed cache 12 again.For instance, first, second address date can be divided into and opens beginning address and an end address, or is divided into and opens a beginning address and a length data.
That is to say, when a software (or driver) is desired to read processing (non-snoopread transaction) when DMA buffer zone 18 is read by non-supervising, then according to a PWBINV instruction repertorie processor 10, and only with modification Data Update relevant in the high-speed cache 12 with first, second address information to DMA buffer zone 18, and the Data Update of whole high-speed cache 12 (is not promptly emptied high-speed cache 12) to primary memory 16.So, can keep the consistance (coherency) of cached data, and avoid timely usefulness (real time performance) not good.
Then, step S20, the end-point devices 20 of this software (or driver) indication PCI express is used the non-technology that supervises, and comes the data in the reading DMA buffer zone 18.Then, step S30 when north bridge chips 14 receives " the non-reading requirement that supervises processing " that the end-point devices 20 of PCI-Express sent, directly captures the data in the DMA buffer zone 18, and must not supervise processor 10.Afterwards, again the data that captured are sent to the end-point devices 20 of PCI-Express.
Second embodiment
Adopt another kind of mode to come performing step S10 in this embodiment, the method is in north bridge chips 14, by one first buffer (not shown) deposit that the part that will be used for high-speed cache 12 writes back and ineffective treatment open the beginning address, one second buffer (not shown) deposits that the part that will be used for high-speed cache 12 writes back and the end address of ineffective treatment, and one the 3rd buffer (not shown) writes back in order to the part of setting high-speed buffer memory and the mode of operation of ineffective treatment.In the present invention, when the 3rd buffer is set as 1,14 of north bridge chips can be according to begin address and the end address of opening that stores in first, second buffer, cause processor 10 to open the data of having revised in beginning address and the end address scope in the high-speed cache, write back in the DMA buffer zone 18, again the data in this scope in the ineffective treatment high-speed cache 12.
That is to say, when a software or driver are desired to read processing when DMA buffer zone 18 is read by non-supervising, then can open beginning address and an end address and be stored in first in the north bridge chips 14 one, in second buffer, and change the mode of operation in the 3rd buffer into 1 by an activation signal, so that cause processor 10 with in the high-speed cache with first, Data Update is to DMA buffer zone 18 in the second address date scope, and not with the data of revising in the whole high-speed cache 12, update all (promptly empties high-speed cache) to primary memory 16, so, can keep the consistance (coherency) of cached data, and avoid timely usefulness (real time performance) not good.When in the high-speed cache with first, second address date scope in after data have been updated in the DMA buffer zone 18, north bridge chips 14 can be made as 0 with the mode of operation in the 3rd buffer.
Then, step S20, the end-point devices 20 of this software (or driver) indication PCI-Express is used the non-technology that supervises, and comes the data in the reading DMA buffer zone 18.Then, step S30 when north bridge chips 14 receives " the non-reading requirement that supervises processing " that the end-point devices 20 of PCI-Express sent, directly captures the data in the DMA buffer zone 18, and must not supervise processor 10.Afterwards, again the data that captured are sent to the end-point devices 20 of PCI-Express.
In data picking method of the present invention,,, keep the cached data consistance simultaneously so can avoid timely usefulness (real time performance) not good owing to only upgrade partial data in the high-speed cache 12 to DMA buffer zone 18.
The 3rd embodiment
As shown in fig. 1, data acquisition system 100 of the present invention comprises the end-point devices (endpoint device) 20 of a processor 10, a high-speed cache 12, a north bridge chips 14, one direct memory access buffer zone (DMA buffer) 18, one PCI-Express.
In the present embodiment, the end-point devices 20 of PCI express so is not in order to limit the present invention in order to as a bus master controller.In the present invention, the end-point devices 20 of PCI-Express is another processor, direct access controller, network or magnetic disc adaptation card or image processing cards or the like.In addition, primary memory 16 is cut apart the DMA buffer zone 18 of a part as non-supervision processing (non-snooped), and DMA buffer zone 18 is set for and can be carried out data access in the mode that writes back (write back) by high-speed cache 12.
Processor 10 is coupled to north bridge chips 14 by a system bus 13, and it is inner or outside that high-speed cache 12 can be arranged at processor 10.In the present embodiment, processor 10 is designed to can be by a PWBINV instruction repertorieization, with according to first, second address information, with the partial data in the high-speed cache 12, after writing back in the DMA buffer zone 18, the above-mentioned partial data in the ineffective treatment high-speed cache 12 again.For instance, first, second address date can be divided into and opens beginning position, location and an end address, or is divided into and opens a beginning address and a length data.
Therefore, when a software (or driver) is desired to read processing (non-snoop readtransaction) when DMA buffer zone 18 is read by non-supervising, can with " part of high-speed cache writes back and ineffective treatment (partial cache write back and invalidate; PWBINV) " processor 10 is delivered in instruction; so processor 10 is carried out the PWBINV instruction, according to first, second address information, with the partial data in the high-speed cache 12; after writing back in the DMA buffer zone 18, and the above-mentioned partial data in the ineffective treatment high-speed cache 12 again.That is to say, processor 10 only with Data Update relevant in the high-speed cache 12 with first, second address date to DMA buffer zone 18, and not with corrected data in the whole high-speed cache 12, update all (promptly empties high-speed cache 12) to primary memory 18.So, can keep the consistance (coherency) of cached data, and avoid timely usefulness (real timeperformance) not good.
North bridge chips 14 is to be coupled to primary memory 16 (containing direct memory access buffer zone 18) by a rambus 15, and north bridge chips is the end-point devices 20 that is coupled to PCI-Express by a PCI-Express link 21.Processor 10 in high-speed cache the Data Update relevant with first, second address date to the DMA buffer zone 18 after, this software (or driver) then can be indicated total line control machine 20, uses the non-technology of supervising to come data in the reading DMA buffer zone 18.When north bridge chips 14 receives " the non-reading requirement that supervises processing " that the end-point devices 20 of PCI-Express sent, directly capture the data in the DMA buffer zone 18, and must not supervise processor 10.Afterwards, again the data that captured are sent to the end-point devices 20 of PCI-Express.
The 4th embodiment
As shown in fig. 1, data acquisition system 100 of the present invention comprises the end-point devices (endpoint device) 20 of a processor 10, a high-speed cache 12, a north bridge chips 14, one direct memory access buffer zone (DMA buffer) 18, one PCI-Express.
In the present embodiment, the end-point devices 20 of PCI-Express so is not in order to limit the present invention in order to as a bus master controller.In the present invention, the end-point devices 20 of PCI-Express is another processor, direct access controller, adapter, magnetic disc adaptation card or image processing cards or the like.In addition, primary memory 16 is cut apart the DMA buffer zone 18 of a part as non-supervision processing (non-snooped), and DMA buffer zone 18 is set for and can be carried out data access in the mode that writes back (write back) by high-speed cache 12.
Processor 10 is coupled to north bridge chips 14 by a system bus 13, and it is inner or outside that high-speed cache 12 can be arranged at processor 10.
North bridge chips 14 is coupled to primary memory 16 (containing direct memory access buffer zone 18) by a rambus 15, and north bridge chips 14 is coupled to the end-point devices 20 of PCI-Express by a PCI-Express link 21.In the present embodiment, north bridge chips 14 is designed to and can opens beginning address, an end address and an activation signal according to one, cause processor 10 to open the data of revising in beginning address and the end address scope in the high-speed cache 12, write back in the DMA buffer zone 18, again the data in this scope in the ineffective treatment high-speed cache 12.
For instance, in north bridge chips 14, by one first buffer deposit that the part that will be used for high-speed cache 12 writes back and ineffective treatment open the beginning address, one second buffer deposits that the part that will be used for high-speed cache 12 writes back and the end address of ineffective treatment, and one the 3rd buffer writes back in order to the part of setting high-speed buffer memory 12 and the mode of operation of ineffective treatment.Be set as 1 o'clock at the 3rd buffer, 14 of north bridge chips can be according to begin address and the end address of opening that stores in first, second buffer, cause processor 10 to open the data of revising in beginning address and the end address scope in the high-speed cache 12, write back in the DMA buffer zone 18, again the data in this scope in the ineffective treatment high-speed cache 12.
Therefore, when a software or driver are desired to read processing when DMA buffer zone 18 is read by non-supervising, then can open beginning address and an end address and be stored in first in the north bridge chips 14 one, in second buffer, and change the mode of operation in the 3rd buffer into 1 by an activation signal, with cause processor 10 with in the high-speed cache 12 with first, Data Update is to DMA buffer zone 18 in the second address date scope, and not with corrected data in the whole high-speed cache 12, update all (promptly empties high-speed cache) to primary memory 16, so, can keep the consistance (coherency) of cached data, and avoid timely usefulness (real time performance) not good.When in the high-speed cache 12 with first, second address date scope in corrected data, be updated in the DMA buffer zone 18 after, north bridge chips 14 can be made as 0 with the mode of operation in the 3rd buffer.
Afterwards, software (or driver) can the indication bus draw device 20, uses the non-technology of supervising to come data in the reading DMA buffer zone 18.When north bridge chips 14 receives " the non-reading requirement that supervises processing " that the end-point devices 20 of PCI-Express sent, directly capture the data in the DMA buffer zone 18, and must not supervise processor 10.Afterwards, again the data that captured are sent to the end-point devices 20 of PCI-Express.
In data acquisition system of the present invention,,, keep the cached data consistance simultaneously so can avoid timely usefulness (real time performance) not good owing to only upgrade partial data in the high-speed cache 12 to DMA buffer zone 18.
Be noted that, data acquisition system of the present invention during with normal mode accessing main memory 16, still can be carried out the WBINV instruction with in the whole high-speed cache 12 by processor 10 at software (or driver), corrected Data Update is to primary memory, to keep the cached data consistance.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; those skilled in the art can do some changes and retouching under the premise without departing from the spirit and scope of the present invention, so the claim that protection scope of the present invention is looked the application is as the criterion.
Claims (10)
1. data acquisition system comprises:
One high-speed cache is in order to storage data;
One processor couples high-speed cache;
The end-point devices of one PCI-Express;
One primary memory has at least one direct memory access buffer zone; And
One north bridge chips, couple the end-point devices of above-mentioned PCI-Express, in order to cause above-mentioned processor with the partial data in the aforementioned cache, be written back in the above-mentioned direct memory access buffer zone, and the above-mentioned partial data in the ineffective treatment aforementioned cache, and the end-point devices of indicating above-mentioned PCI-Express is used a non-treatment technology that supervises, read the data of above-mentioned direct memory access buffer zone, it is one non-when supervising reading requirement to make above-mentioned north bridge chips receive, must not supervise above-mentioned processor, directly capture the data in the above-mentioned direct memory access buffer zone.
2. data acquisition system as claimed in claim 1, wherein above-mentioned north bridge chips is according to an instruction that contains one first address and one second address, above-mentioned partial data in the aforementioned cache is written back in the above-mentioned direct memory access buffer zone, and the above-mentioned partial data in the ineffective treatment aforementioned cache.
3. data acquisition system as claimed in claim 1, wherein the end-point devices of above-mentioned PCI-Express is a direct access controller, an image processing cards, a magnetic disc adaptation card or an adapter.
4. data acquisition system comprises:
The end-point devices of one PCI-Express;
One north bridge chips couples the end-point devices of above-mentioned PCI-Express;
One primary memory couples above-mentioned north bridge chips, has at least one direct memory access buffer zone;
One high-speed cache is in order to storage data; And
One processor, sequencing is with the partial data in the aforementioned cache, be written back in the above-mentioned direct memory access buffer zone, and the above-mentioned partial data in the ineffective treatment aforementioned cache, and the end-point devices of indicating above-mentioned PCI-Express uses a non-treatment technology that supervises, and reads the data of above-mentioned direct memory access buffer zone, and it is one non-when supervising reading requirement to make above-mentioned north bridge chips receive, must not supervise above-mentioned processor, directly capture the data in the above-mentioned direct memory access buffer zone.
5. data acquisition system as claimed in claim 4, wherein above-mentioned processor is according to an instruction that contains one first address and one second address, above-mentioned partial data in the aforementioned cache is written back in the above-mentioned direct memory access buffer zone, and the above-mentioned partial data in the ineffective treatment aforementioned cache.
6. data acquisition system as claimed in claim 4, wherein the end-point devices of above-mentioned PCI-Express couples by a PCI-Express link and above-mentioned north bridge chips.
7. data picking method, be applicable to a non-disposal system that supervises, this is non-to supervise end-point devices, direct memory access buffer zone and a high-speed cache that disposal system includes a processor, a north bridge chips, a PCI-Express in order to store data, and this method comprises:
With the partial data in the aforementioned cache, be written back in the direct memory access buffer zone;
Above-mentioned partial data in the ineffective treatment aforementioned cache; And
Indicate the end-point devices of above-mentioned PCI-Express to use a non-treatment technology that supervises, read the data of above-mentioned direct memory access buffer zone, it is one non-when supervising reading requirement to make above-mentioned north bridge chips receive, do not supervise above-mentioned processor, directly capture the data in the above-mentioned direct memory access buffer zone.
8. data picking method as claimed in claim 7, wherein above-mentioned processor is according to an instruction that contains one first address and one second address, above-mentioned partial data in the aforementioned cache is written back in the above-mentioned direct memory access buffer zone, and the above-mentioned partial data in the ineffective treatment aforementioned cache.
9. data picking method as claimed in claim 7, wherein above-mentioned north bridge chips is according to one first address, one second address and an activation signal, cause above-mentioned processor that the above-mentioned partial data in the aforementioned cache is written back in the above-mentioned direct memory access buffer zone, and the above-mentioned partial data in the ineffective treatment aforementioned cache.
10. data picking method, be applicable to a data acquisition system, this data acquisition system includes end-point devices, direct memory access buffer zone and the high-speed cache of a processor, a north bridge chips, a PCI-Express in order to store data, and this method comprises:
Partly write-back and ineffective treatment aforementioned cache, wherein in the aforementioned cache by the deposit data of write-back to above-mentioned direct memory access buffer zone;
Indicate the end-point devices of above-mentioned PCI-Express to use a non-treatment technology that supervises, read the data of above-mentioned direct memory access buffer zone; And
When above-mentioned north bridge chips receives one non-ly when supervising reading requirement, do not supervise above-mentioned processor, and directly capture the data in the above-mentioned direct memory access buffer zone.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100315915A CN1307560C (en) | 2004-03-25 | 2004-03-25 | Data picking method and system thereof |
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| CNB2004100315915A CN1307560C (en) | 2004-03-25 | 2004-03-25 | Data picking method and system thereof |
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| CN1564139A CN1564139A (en) | 2005-01-12 |
| CN1307560C true CN1307560C (en) | 2007-03-28 |
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| CN1326048C (en) * | 2005-05-31 | 2007-07-11 | 威盛电子股份有限公司 | Memory access device and method |
| US8205053B2 (en) | 2005-08-16 | 2012-06-19 | Nxp B.V. | Method and system for accessing memory using an auxiliary memory |
| CN101277196B (en) * | 2007-03-30 | 2011-09-28 | 杭州华三通信技术有限公司 | Communication system, communication method and cable fastener plate based on PCIE switching network |
| CN103186492B (en) * | 2011-12-28 | 2016-03-30 | 联芯科技有限公司 | Based on data consistency protective method and the system thereof of AXI bus |
| CN109101439B (en) * | 2017-06-21 | 2024-01-09 | 深圳市中兴微电子技术有限公司 | Message processing method and device |
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| US5524233A (en) * | 1993-03-31 | 1996-06-04 | Intel Corporation | Method and apparatus for controlling an external cache memory wherein the cache controller is responsive to an interagent communication for performing cache control operations |
| US5524234A (en) * | 1992-11-13 | 1996-06-04 | Cyrix Corporation | Coherency for write-back cache in a system designed for write-through cache including write-back latency control |
| US5555398A (en) * | 1994-04-15 | 1996-09-10 | Intel Corporation | Write back cache coherency module for systems with a write through cache supporting bus |
| US5623633A (en) * | 1993-07-27 | 1997-04-22 | Dell Usa, L.P. | Cache-based computer system employing a snoop control circuit with write-back suppression |
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| US5524234A (en) * | 1992-11-13 | 1996-06-04 | Cyrix Corporation | Coherency for write-back cache in a system designed for write-through cache including write-back latency control |
| US5860111A (en) * | 1992-11-13 | 1999-01-12 | National Semiconductor Corporation | Coherency for write-back cache in a system designed for write-through cache including export-on-hold |
| US5524233A (en) * | 1993-03-31 | 1996-06-04 | Intel Corporation | Method and apparatus for controlling an external cache memory wherein the cache controller is responsive to an interagent communication for performing cache control operations |
| US5623633A (en) * | 1993-07-27 | 1997-04-22 | Dell Usa, L.P. | Cache-based computer system employing a snoop control circuit with write-back suppression |
| US5555398A (en) * | 1994-04-15 | 1996-09-10 | Intel Corporation | Write back cache coherency module for systems with a write through cache supporting bus |
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