CN1303685C - Ball grid array (BGA) semiconductor package - Google Patents
Ball grid array (BGA) semiconductor package Download PDFInfo
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- CN1303685C CN1303685C CNB021231923A CN02123192A CN1303685C CN 1303685 C CN1303685 C CN 1303685C CN B021231923 A CNB021231923 A CN B021231923A CN 02123192 A CN02123192 A CN 02123192A CN 1303685 C CN1303685 C CN 1303685C
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- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
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Abstract
The present invention relates to a ball grid array semiconductor package piece. The present invention is characterized in that at leat one chip is connected to a basal plate; multiple welding wires are formed for electrically connecting a signal solder ingot of the chip to a signal welding wire pad of the chip; both ends of a power strip and both ends of a grounding strip are respectively stuck to the preset positions of the chip and the basal plate through conductive adhesive, and the power strip and the grounding strip do not influence the layout mode of the welding wires. The basal plate does not need to be provided with a power ring or a grounding ring, so the layout limitation of the basal plate is reduced. Only the welding wires which connect the signal solder ingot to the signal welding wire pad are arranged on the basal plate; therefore, the probability of generating short circuits among the welding wires is reduced, and the qualification rate of products is increased. Besides, the power strip and the grounding strip can also provide a shielding function so that the chip is free from external electromagnetic interference, which is helpful to enhance the performance of the ball grid array semiconductor package piece; the top surfaces of the power strip and the grounding strip are exposed, and thus, the radiation efficiency of the ball grid array semiconductor package piece is effectively improved.
Description
Technical field
The invention relates to a kind of semiconductor package part, particularly be increased electrically and ball grid array (Ball Grid Array, the BGA) semiconductor package part of radiating efficiency about a kind of.
Background technology
One of encapsulating products main flow, spherical grid array type (Ball Grid Array, BGA) semiconductor package part, it is characterized in that many soldered balls of arranging in the array mode of planting on the substrate bottom surface, make and be provided with more input/go out link (I/O Connection) in the same units area, the semiconductor chip that can adapt to high density electronic building brick (Electronic Component) and electronic circuit (Electronic Circuit) is required, to meet the demand of electronic product for electrical functionality and processing speed.Plant the soldered ball that is connected on the substrate in order to connect packaging part to external device such as printed circuit board (PCB) (PrintedCircuit Board, PCB) etc., electrically connect for chip and external device, therefore the functions such as ground connection (Ground), power supply (Power) and signal (Signal) conduction of packaging part need be provided.Therefore, on structural design, substrate be provided with corresponding mechanism respectively with this soldered ball electrical communication of same-action not, go up the effect of expection in the hope of reaching the running of packaging part intraware.
In view of this, United States Patent (USP) the 5th, 581,122,5,545,923 and 5,726, invent the design that is provided with ground loop (Ground Ring), power ring (Power Ring) and signal bond wires pad (Signal Finger) in substrate No. 860.In the semiconductor structure shown in accompanying drawing 5 and accompanying drawing 6, the zone beyond the chip connecting area 101 of a substrate 10 upper surfaces 100 is laid with a ground loop 11, a power ring 12 and many barss wire bond pad 13.Connect and put a chip 14 behind this chip connecting area 101, carry out routing (Wire Bonding) operation then, to form many earth connections (GroundWire) 15, power line (Power Wire) 16 and holding wire (Signal Wire) 17; Earth connection 15 is to connect this weld pad 140 on this chip 14 to ground loop 11, and power line 16 connects these weld pads 140 to power ring 12, and 17 of holding wires connect this weld pad 140 to signal bond wires pad 13.Afterwards, in subsequent manufacturing processes, plant and connect a plurality of soldered balls 18 on the lower surface 102 of substrate 10, and make soldered ball 18 and this ground loop 11, power ring 12 and signal bond wires pad 13 electrical communication via conductive trace 19, so just can electrically communicate and chip 14 is operated with external device (not icon).Notice, icon only is the usefulness of explanation, so be all the structure of simplification, actual structure is then accurate complicated many.
Yet the design of above-mentioned semiconductor structure but has many shortcomings.At first, the setting of ground loop and power ring occupies the restriction that substrate area causes layout on the substrate (Routability), be unfavorable for high density input/the go out setting and the integrated development of chip height of link, and substrate size can't further reduce, so do not meet the compact requirement of semiconductor structure.Moreover; for reducing the noise of signal; existing semiconductor structure usually also on substrate design isolator (Decoupling Pad) (not icon) arranged, for settling capacitor (Capacitor) (not icon) in order to reducing noise, the like this then layout on the restricting substrate more.In addition, need to form numerous earth connections, power line and holding wire, further increase the complexity of manufacture process, as shown in Figure 6, this bonding wire is laid with multilayer, so need the accurately height of bonding wire bank (Loop) between the control different layers, the difficulty of manufacture process is improved, and the bonding wire of multilayer can cause the difficulty of mold pressing (Molding) operation, when the mold pressing injecting glue, mould stream (Mold Flow) impulsive force (Impact) causes touching each other between bonding wire and (Short) phenomenon that is short-circuited most probably, and this can have a strong impact on the acceptance rate of product.
Therefore, how effectively addressing the aforementioned drawbacks, develop a kind of electrically highly and do not increase layout restrictions on the substrate and guarantee the semiconductor device of manufactured goods acceptance rate, is the problem that needs are inquired in fact.
Summary of the invention
A purpose of the present invention is to provide a kind of ball grid array (BGA) semiconductor package that power ring and ground loop need not be set.
Another object of the present invention is to provide a kind of ball grid array (BGA) semiconductor package that need not lay power line and earth connection.
A further object of the present invention is to provide a kind of ball grid array (BGA) semiconductor package that can not increase layout restrictions on the substrate.
Another purpose of the present invention is to provide a kind of ball grid array (BGA) semiconductor package of be increased radiating efficiency and tool function of shielding.
For reaching above-mentioned and other purpose, invented a kind of ball grid array (BGA) semiconductor package.This semiconductor package part is to comprise: a substrate, have a first surface and an opposing second surface, on the first surface of this substrate, define a chip connecting area, be laid with many barss wire bond pad (Signal Finger) around this chip connecting area, and the zone outside this signal bond wires pad is formed with the both sides that a power supply sheet connecting area and a ground strip connecting area lay respectively at this substrate; At least one chip, have an action face (Active Surface) the non-action face (Non-active Surface) relative with one, location about place on this chip action face is laid with many barss weld pad (Signal Pad), power supply weld pad (Power Pad) and ground connection weld pad (Ground Pad), and the zone of not laying weld pad on this action face is formed with a bus plane (Power Plane) and a ground plane (Ground Plane), this power supply weld pad is to integrate (Consolidate) and electrical communication to this bus plane, and this ground connection weld pad be integrate and electrical communication to this ground plane, simultaneously, the non-action face of this chip is to be adhered on the chip connecting area of this substrate, makes bus plane on this chip and ground plane respectively towards the power supply sheet connecting area and the ground strip connecting area of this substrate; Many bonding wires are in order to the signal weld pad that electrically connects this chip signal bond wires pad to this substrate first surface; One power supply sheet (Power Plate), the one end is adhered to the bus plane of this chip, and the other end is bonded to the power supply sheet connecting area of this substrate, and this power supply sheet is provided with in the mode that does not influence this bonding wire laying; One ground strip (Ground Plate), the one end is adhered to the ground plane of this chip, and the other end is bonded to the ground strip connecting area of this substrate, and this ground strip is provided with in the mode that does not influence this bonding wire laying; One packing colloid is formed on the first surface of this substrate, in order to coat this chip, this bonding wire, this power supply sheet and this ground strip; And a plurality of soldered balls, plant and be connected on this substrate second surface.
Wherein, the pre-position is formed with many barss solder ball pad (Signal Ball Pad), power supply solder ball pad (Power Ball Pad) and ground connection solder ball pad (GroundBall Pad) on the second surface of this substrate, and this substrate is formed with many through holes (Via) that run through this substrate, this through hole is with so that the signal bond wires pad electrical communication on this signal solder balls pad and this substrate first surface, and make this power supply solder ball pad and ground connection solder ball pad respectively with this substrate first surface on power supply sheet connecting area and ground strip connecting area electrical communication; This soldered ball is then planted on this signal solder balls pad, power supply solder ball pad and the ground connection solder ball pad that is connected to this substrate second surface.Moreover power supply weld pad on this chip action face and ground connection weld pad are formed with a plurality of leads in reprovision (Re-distribution) mode, and this lead-in wire usefulness is so that this power supply weld pad and ground connection weld pad are distinguished electrical communication to this bus plane and ground plane.
The power supply sheet made from metal material, be formed with a protuberance (Protruding Portion), a par (Flat Portion) and a support portion (Supporting Portion), this protuberance is the bus plane that is adhered to this chip with conductivity viscose such as elargol, this support portion also is adhered to the power supply sheet connecting area of this substrate with the conductivity viscose, make this par be supported in the laying that this chip top does not influence this bonding wire for this protuberance and support portion.In like manner, this ground strip also is able to metal material and makes, and be adhered on this chip and the substrate with the conductivity viscose, wherein, this ground strip also is formed with a protuberance, a par and a support portion, this protuberance is adhered to the ground plane of this chip, and this support portion is adhered to the ground strip connecting area of this substrate, makes this par be supported in the laying that this chip top does not influence this bonding wire for this protuberance and support portion.
In above-mentioned structure, the mode that adopts power supply sheet and ground strip has plurality of advantages to replace power line and the earth connection that existing packaging part is laid.At first, need not to be provided with power ring and ground loop in order to connect power line and earth connection respectively on the substrate, the shortcoming that occupies layout on the substrate restricting substrate (Routability) because of power ring and ground loop is overcome.Moreover, need not to lay power line and earth connection, connect the bonding wire of signal weld pad and only be formed with to the signal bond wires pad, so the probability of be short-circuited between bonding wire when mold pressing (Short) is minimized, and manufacture process is simplified, the acceptance rate of raising product.In addition, power supply sheet and ground strip also can provide shielding (Shielding) function, and (Electric Magnetic Interference EMI), helps to promote the performance of semiconductor package part to make chip avoid extraneous electromagnetic interference.
On the other hand, the end face of this power supply sheet par must be the copline mode with the end face of this ground strip par and be provided with, and makes the end face of this power supply sheet and the end face of this ground strip expose outside this packing colloid.This kind design then helps to get rid of the heat energy that chip produced by power supply sheet that exposes and ground strip surface, so effectively promoted the radiating efficiency of packaging part.
Description of drawings
For above and other objects of the present invention, feature and advantage can be become apparent, will with preferred embodiment, and conjunction with figs. describes embodiments of the invention in detail, the content Description of accompanying drawing is as follows:
Accompanying drawing 1 is the cutaway view of first embodiment of semiconductor package part of the present invention;
Accompanying drawing 2A is the top view of the chip of semiconductor package part of the present invention;
Accompanying drawing 2B is the partial sectional view that accompanying drawing 2A cuts along the 2B-2B line;
Accompanying drawing 3A is the manufacture process generalized section that shows first embodiment of semiconductor package part of the present invention to accompanying drawing 3F;
Accompanying drawing 4 is cutaway views of second embodiment of semiconductor package part of the present invention;
Accompanying drawing 5 is cutaway views of an existing semiconductor structure; And
Accompanying drawing 6 is local top views of accompanying drawing 5 semiconductor structures.
Symbol description
1 semiconductor structure, 10 substrates
100 upper surfaces, 101 chip connecting areas
102 lower surfaces, 11 ground loops
12 power rings, 13 signal bond wires pads
14 chips, 140 weld pads
15 earth connections, 16 power lines
17 holding wires, 18 soldered balls
19 conductive traces
2 semiconductor package parts, 20 substrates
200 first surfaces, 201 second surfaces
202 chip connecting areas, 203 signal bond wires pads
204 power supply sheet connecting areas, 205 ground strip connecting areas
206 signal solder balls pads, 207 power supply solder ball pads
208 ground connection solder ball pads 209 are refused welding flux layer
21 chips, 210 action face
211 non-action face 212 signal weld pads
213 power supply weld pads, 214 ground connection weld pads
215 bus planes, 216 ground planes
217 lead-in wires, 218 interlayers
219 interlayers, 22 bonding wires
23 power supply sheets, 230 protuberances
232 support portions, 231 pars
24 ground strips, 240 protuberances
242 support portions, 241 pars
25 packing colloid 26S signal solder balls
26P power supply soldered ball 26G ground connection soldered ball
27 through holes, 28 conductivity viscoses
3 semiconductor package parts, 30 power supply sheets
300 pars, 301 end faces
31 ground strips, 310 pars
311 end faces, 32 packing colloids, 33 chips
Embodiment
Embodiment 1
Be ball grid array (BGA) semiconductor package 2 of the present invention as shown in Figure 1; Accompanying drawing 2A is depicted as semiconductor package part 2 employed chips 21 of the present invention.As shown in the figure, this semiconductor package part 2 is to comprise: a substrate 20, have a first surface 200 and an opposing second surface 201, on the first surface 200 of this substrate 20, define a chip connecting area 202, around this chip connecting area 202, be laid with many barss wire bond pad (Signal Finger) 203, and the zone outside this signal bond wires pad 203 is formed with the both sides that a power supply sheet connecting area 204 and a ground strip connecting area 205 lay respectively at this substrate 20; At least one chip 21, have an action face (ActiveSurface) the 210 non-action face (Non-active Surface) 211 relative with one, location about place on these chip 21 action face 210, be laid with many barss weld pad (Signal Pad) 212, power supply weld pad (Power Pad) 213 and ground connection weld pad (Ground Pad) 214, and the zone of not laying weld pad on this action face 210 is formed with a bus plane (Power Plane) 215 and one ground plane (Ground Plane) 216, this power supply weld pad 213 is to integrate (Consolidate) and electrical communication to this bus plane 215, and this ground connection weld pad 214 be integrate and electrical communication to this ground plane 216, simultaneously, the non-action face 211 of this chip 21 is to be adhered on the chip connecting area 202 of this substrate 20, makes bus plane 215 on this chip 21 and ground plane 216 respectively towards the power supply sheet connecting area 204 and the ground strip connecting area 205 of this substrate 20; Many bonding wires 22 are in order to the signal weld pad 212 that electrically connects this chip 21 signal bond wires pad 203 to these substrate 20 first surfaces 200; One power supply sheet (Power Plate) 23, the one end is adhered to the bus plane 215 of this chip 21, and the other end is bonded to the power supply sheet connecting area 204 of this substrate 20, and this power supply sheet 23 is provided with in the mode that does not influence these bonding wire 22 layings; One ground strip (Ground Plate) 24, the one end is adhered to the ground plane 216 of this chip 21, and the other end is bonded to the ground strip connecting area 205 of this substrate 20, and this ground strip 24 is provided with in the mode that does not influence these bonding wire 22 layings; One packing colloid 25 is formed on the first surface 200 of this substrate 20, in order to coat this chip 21, this bonding wire 22, this power supply sheet 23 and this ground strip 24; And many barss soldered ball 26S, power supply soldered ball 26P and ground connection soldered ball 26G, plant on the second surface 201 that is connected to this substrate 20.
Above-mentioned ball grid array (BGA) semiconductor package 2 is to make to the step shown in the accompanying drawing 3F as accompanying drawing 3A.At first, shown in accompanying drawing 3A, preparation one chip 21 with an action face 210 non-action face 211 relative with one.Shown in accompanying drawing 2A, the location about place on these chip 21 action face 210 is laid with many barss weld pad 212, power supply weld pad 213 and ground connection weld pad 214.Because the method for making of this weld pad all adopts prior art, so do not given unnecessary details in this.Notice, the number of icon weld pad is only established for simplified illustration, and the weld pad number should be looked actual needs and be provided with.
Shown in accompanying drawing 3B and accompanying drawing 2A, power supply weld pad 213 on these chip 21 action face 210 is formed with a plurality of leads 217 in reprovision (Re-distribution) mode, with so that this power supply weld pad 213 integrate and electrical communication to bus planes 215 via this lead-in wire 217, simultaneously, the lead-in wire 217 that also forms in the reprovision mode of this ground connection weld pad 214 and integrating and electrical communication to a ground plane 216.The reprovision technology that this states, shown in accompanying drawing 2B, on the power supply weld pad 213 that exposes outside interlayer (PassivatingFilm) 218, form lead-in wire 217 with conductivity material such as aluminium (Aluminum) or copper (Copper), also on lead-in wire 217, be coated with an insulating properties material such as silica (SiliconOxide) or silicon nitride (Silicon Nitride) to form another interlayer 219, and removal part interlayer 219, the exposed portions serve lead-in wire 217 in addition, and lead-in wire 217 exposed parts of all power supply weld pads 213 are then integrated and formed bus plane 215.In like manner, ground plane 216 also forms in the mode shown in accompanying drawing 2B, so do not given unnecessary details in this.
Shown in accompanying drawing 3C, preparation one substrate 20 with a first surface 200 and an opposing second surface 201, on the first surface 200 of this substrate 20, define a chip connecting area 202, around this chip connecting area 202, be laid with many barss wire bond pad 203, and the zone outside this signal bond wires pad 203 is formed with the both sides that a power supply sheet connecting area 204 and a ground strip connecting area 205 lay respectively at this substrate 20.The pre-position is formed with many barss solder ball pad (Signal Ball Pad) 206, power supply solder ball pad (Power BallPad) 207 and ground connection solder ball pad (Ground Ball Pad) 208 on the second surface 201 of this substrate 20; wherein; also be coated with one on the second surface 201 of this substrate 20 and refuse solder flux (Solder Mask) layer 209; in order to the second surface 201 of protecting this substrate 20, and make this solder ball pad expose outside this to refuse welding flux layer 209 for follow-up usefulness of planting ball.Again, this substrate 20 is formed with a plurality of through holes (Via) 27 that run through this substrate, 27 effects of this through hole are signal bond wires pad 203 electrical communication that make on this signal solder balls pad 206 and these substrate 20 first surfaces 200, and make this power supply solder ball pad 207 and ground connection solder ball pad 208 respectively with these substrate 20 first surfaces 200 on power supply sheet connecting area 204 and ground strip connecting area 205 electrical communication.
Shown in accompanying drawing 3D, the non-action face 211 of bonding this chip 21 makes bus plane 215 on this chip 21 and ground plane 216 respectively towards the power supply sheet connecting area 204 and the ground strip connecting area 205 of this substrate 20 to the chip connecting area 202 of this substrate 20.Carry out bonding wire (Wire Bonding) operation again,,, make the signal weld pad 212 of this chip 21 be electrically connected to signal bond wires pad 203 on these substrate 20 first surfaces 200 as gold thread in order to form many bonding wires 22.
Shown in accompanying drawing 3E, the two ends of the power supply sheet of making as the bonding metal material of elargol with conductivity viscose 28 23 are respectively on this chip 21 and the substrate 20.This power supply sheet 23 is formed with 231 and one support portion, a protuberance (Protruding Portion) 230, one par (Flat Portion) (Supporting Portion) 232, this protuberance 230 is the bus planes 215 that are adhered to this chip 21, and this support portion 232 is adhered to the power supply sheet connecting area 204 of this substrate 20, makes this par 231 be this protuberance 230 and support portion 232 laying that these chip 21 tops do not influence this bonding wire 22 that is supported in.Simultaneously, the ground strip 24 that one metal material is made also uses these conductivity viscose 28 bonding its two ends respectively on this chip 21 and the substrate 20, wherein, this ground strip 24 also is formed with a protuberance 240, a par 241 and a support portion 242, this protuberance 240 is adhered to the ground plane 216 of this chip 21, this support portion 242 is adhered to the ground strip connecting area 205 of this substrate 20, makes this par 241 be this protuberance 240 and support portion 242 laying that these chip 21 tops do not influence this bonding wire 22 that is supported in.Yet the shape that this power supply sheet 23 and ground strip 24 present is not limited to the described shape of this embodiment, notice, and any other can reach the shape of identical function, is all category of the present invention and contains.
Shown in accompanying drawing 3F, carry out mold pressing (Molding) operation, use a resin compound such as epoxy resin (Epoxy Resin) on the first surface 200 of this substrate 20, to form a packing colloid 25, so that this chip 21, this bonding wire 22, this power supply sheet 23 and this ground strip 24 coated by this packing colloid 25, thereby avoid extraneous aqueous vapor or polluter is encroached on.Then, plant ball (Ball Implantation) operation, plant respectively and meet many barss soldered ball 26S, power supply soldered ball 26P and ground connection soldered ball 26G on this signal solder balls pad 206, power supply solder ball pad 207 and the ground connection solder ball pad 208 of these substrate 20 second surfaces 201, the effect of this type of soldered ball 26 is to make this chip 21 be able to electrically connect with external device (not icon).So then finish semiconductor package part 2 of the present invention.Since mold pressing with plant the ball process and be prior art, so do not given unnecessary details in this.
Compare with existing semiconductor package part, the invention is characterized in and adopt power supply sheet and ground strip to replace power line and the earth connection that existing packaging part is laid, its advantage is as follows: at first, need not to be provided with power ring and ground loop on the substrate in order to connect power line and earth connection respectively, thus power ring and ground loop occupy substrate and on the restricting substrate shortcoming of layout (Routability) got rid of.Moreover, be compared to power line and earth connection that prior art is laid, being arranged in the whole manufacturing process of power supply sheet and ground strip comparatively simplified, and only be formed with in the packaging part of the present invention and connect the bonding wire of signal weld pad to the signal bond wires pad, the probability of (Short) is minimized so be short-circuited between bonding wire when mold pressing, and the acceptance rate of product is improved.In addition, power supply sheet and ground strip also can provide shielding (Shielding) function, and (ElectricMagnetic Interference EMI), helps to promote the performance of semiconductor package part to make chip avoid being subjected to extraneous electromagnetic interference.
Embodiment 2
Accompanying drawing 4 is depicted as second embodiment of semiconductor package part of the present invention.As shown in the figure, the semiconductor package part 3 of second embodiment of the invention is that the semiconductor package part 2 with first embodiment is identical haply, and difference only is that the end face 301 of power supply sheet 30 pars 300 must be the copline mode with the end face 311 of the par 310 of ground strip 31 and be provided with.When carrying out molding operation, the roof of encapsulating mould (not icon) gets on the end face 311 of the end face 301 that directly is pressed on this power supply sheet 30 and ground strip 31, make this end face 301,311 are not coated by packing colloid 32, so after packing colloid 32 formed, the end face 301 of this power supply sheet 30 and the end face 311 of ground strip 31 were exposed outside this packing colloid 32.Because this power supply sheet 30 and ground strip 31 are to make with metal material, the design that this kind end face exposes, help to make heat that chip 33 produced via this power supply sheet 30 and ground strip 31, with and the end face 301 that exposes, 311 and dissipate to outside the packaging part 3, so effectively promote the radiating efficiency of this packaging part 3.
The above; only be in order to the explanation specific embodiments of the invention; but be not in order to limiting practical range of the present invention, change or modify not breaking away from all equivalences of finishing under spirit defined in claims of the present invention and the principle, all belong within the protection range of this patent.
Claims (20)
1. a ball grid array (BGA) semiconductor package is characterized in that, this semiconductor package part comprises:
One substrate, have a first surface and an opposing second surface, on the first surface of this substrate, define a chip connecting area, be laid with many barss wire bond pad around this chip connecting area, and the zone outside this signal bond wires pad is formed with the both sides that a power supply sheet connecting area and a ground strip connecting area lay respectively at this substrate;
At least one chip, have an action face non-action face relative with one, location about place on this chip action face, be laid with many barss weld pad, power supply weld pad and ground connection weld pad, and the zone of not laying weld pad on this action face is formed with a bus plane and a ground plane, this power supply weld pad be integrate and electrical communication to this bus plane, and this ground connection weld pad be integrate and electrical communication to this ground plane, simultaneously, the non-action face of this chip is to be adhered on the chip connecting area of this substrate, the power supply sheet connecting area and the ground strip connecting area that make bus plane on this chip and ground plane are electrically connected at this substrate respectively;
Many bonding wires are in order to the signal weld pad that electrically connects this chip signal bond wires pad to this substrate first surface;
One power supply sheet, the one end is adhered to the bus plane of this chip, and the other end is bonded to the power supply sheet connecting area of this substrate, and this power supply sheet is to keep mode at interval to be arranged on this chip and the substrate with this bonding wire;
One ground strip, the one end is adhered to the ground plane of this chip, and the other end is bonded to the ground strip connecting area of this substrate, and this ground strip is to keep mode at interval to be arranged on this chip and the substrate with this bonding wire;
One packing colloid is formed on the first surface of this substrate, in order to coat this chip, this bonding wire, this power supply sheet and this ground strip; And
A plurality of soldered balls are planted on the second surface that is connected to this substrate.
2. semiconductor package part as claimed in claim 1, it is characterized in that, the pre-position is formed with many barss solder ball pad, power supply solder ball pad and ground connection solder ball pad on the second surface of this substrate, make the signal bond wires pad electrical communication on this signal solder balls pad and this substrate first surface, and this power supply solder ball pad and ground connection solder ball pad respectively with this substrate first surface on power supply sheet connecting area and ground strip connecting area electrical communication.
3. semiconductor package part as claimed in claim 2, it is characterized in that, this substrate is formed with many through holes that run through substrate, with so that this signal solder balls pad, power supply solder ball pad and ground connection solder ball pad respectively with this signal bond wires pad, this power supply sheet connecting area and ground strip connecting area electrical communication.
4. semiconductor package part as claimed in claim 2 is characterized in that, this soldered ball is planted on this signal solder balls pad, power supply solder ball pad and the ground connection solder ball pad that is connected to this substrate second surface.
5. semiconductor package part as claimed in claim 1, it is characterized in that, power supply weld pad and ground connection weld pad on this chip action face are formed with a plurality of leads in the reprovision mode, this lead-in wire with so that this power supply weld pad and ground connection weld pad integrate respectively and electrical communication to this bus plane and ground plane.
6. semiconductor package part as claimed in claim 1, it is characterized in that, this power supply sheet is to have a protuberance, a par and a support portion, this protuberance is adhered to the bus plane of this chip, this support portion is adhered to the power supply sheet connecting area of this substrate, makes this par be supported in the laying that this chip top does not influence this bonding wire for this protuberance and support portion.
7. semiconductor package part as claimed in claim 1 is characterized in that, this power supply sheet is to make with metal material.
8. semiconductor package part as claimed in claim 1 is characterized in that, this power supply sheet is to be adhered on this chip and the substrate with the conductivity viscose.
9. semiconductor package part as claimed in claim 1, it is characterized in that, this ground strip is to have a protuberance, a par and a support portion, this protuberance is adhered to the ground plane of this chip, this support portion is adhered to the ground strip connecting area of this substrate, makes this par be supported in the laying that this chip top does not influence this bonding wire for this protuberance and support portion.
10. semiconductor package part as claimed in claim 1 is characterized in that this ground strip is to make with metal material.
11. semiconductor package part as claimed in claim 1 is characterized in that, this ground strip is to be adhered on this chip and the substrate with the conductivity viscose.
12. a ball grid array (BGA) semiconductor package is characterized in that, this semiconductor package part comprises:
One substrate, have a first surface and an opposing second surface, on the first surface of this substrate, define a chip connecting area, be laid with many barss wire bond pad around this chip connecting area, and the zone outside this signal bond wires pad is formed with the both sides that a power supply sheet connecting area and a ground strip connecting area lay respectively at this substrate;
At least one chip, have an action face non-action face relative with one, location about place on this chip action face, be laid with many barss weld pad, power supply weld pad and ground connection weld pad, and the zone of not laying weld pad on this action face is formed with a bus plane and a ground plane, this power supply weld pad be integrate and electrical communication to this bus plane, and this ground connection weld pad be integrate and electrical communication to this ground plane, simultaneously, the non-action face of this chip is to be adhered on the chip connecting area of this substrate, the power supply sheet connecting area and the ground strip connecting area that make bus plane on this chip and ground plane are electrically connected at this substrate respectively;
Many bonding wires are in order to the signal weld pad that electrically connects this chip signal bond wires pad to this substrate first surface;
One power supply sheet, have a protuberance, a par and a support portion, this protuberance is adhered to the bus plane of this chip, and this support portion is adhered to the power supply sheet connecting area of this substrate, make this par be supported in this chip top, and keep at interval with this bonding wire by this protuberance and support portion;
One ground strip, have a protuberance, a par and a support portion, this protuberance is adhered to the ground plane of this chip, this support portion is adhered to the ground strip connecting area of this substrate, make this par be supported in this chip top by this protuberance and support portion, and keep at interval with this bonding wire, and to make the end face of this ground strip par be that end face with this power supply sheet par is the copline mode and is provided with;
One packing colloid is formed on the first surface of this substrate, in order to coat this chip, this bonding wire, this power supply sheet and this ground strip, makes the end face of this ground strip par and the end face of this power supply sheet par expose outside this packing colloid; And
A plurality of soldered balls are planted on the second surface that is connected to this substrate.
13. semiconductor package part as claimed in claim 12, it is characterized in that, the pre-position is formed with many barss solder ball pad, power supply solder ball pad and ground connection solder ball pad on the second surface of this substrate, make the signal bond wires pad electrical communication on this signal solder balls pad and this substrate first surface, and this power supply solder ball pad and ground connection solder ball pad respectively with this substrate first surface on power supply sheet connecting area and ground strip connecting area electrical communication.
14. semiconductor package part as claimed in claim 13, it is characterized in that, this substrate is formed with many through holes that run through substrate, with so that this signal solder balls pad, power supply solder ball pad and ground connection solder ball pad respectively with this signal bond wires pad, this power supply sheet connecting area and ground strip connecting area electrical communication.
15. semiconductor package part as claimed in claim 13 is characterized in that, this soldered ball is planted on this signal solder balls pad, power supply solder ball pad and the ground connection solder ball pad that is connected to this substrate second surface.
16. semiconductor package part as claimed in claim 12, it is characterized in that, power supply weld pad and ground connection weld pad on this chip action face are formed with a plurality of leads in the reprovision mode, this lead-in wire with so that this power supply weld pad and ground connection weld pad integrate respectively and electrical communication to this bus plane and ground plane.
17. semiconductor package part as claimed in claim 12 is characterized in that, this power supply sheet is to make with metal material.
18. semiconductor package part as claimed in claim 12 is characterized in that, this power supply sheet is to be adhered on this chip and the substrate with the conductivity viscose.
19. semiconductor package part as claimed in claim 12 is characterized in that, this ground strip is to make with metal material.
20. semiconductor package part as claimed in claim 12 is characterized in that, this ground strip is to be adhered on this chip and the substrate with the conductivity viscose.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021231923A CN1303685C (en) | 2002-06-28 | 2002-06-28 | Ball grid array (BGA) semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021231923A CN1303685C (en) | 2002-06-28 | 2002-06-28 | Ball grid array (BGA) semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1466206A CN1466206A (en) | 2004-01-07 |
| CN1303685C true CN1303685C (en) | 2007-03-07 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB021231923A Expired - Fee Related CN1303685C (en) | 2002-06-28 | 2002-06-28 | Ball grid array (BGA) semiconductor package |
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| CN (1) | CN1303685C (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100373596C (en) * | 2004-09-07 | 2008-03-05 | 日月光半导体制造股份有限公司 | Ball-grid array packed substrate plate and its structure thereof |
| CN101378023B (en) * | 2007-08-27 | 2010-12-01 | 矽品精密工业股份有限公司 | Semiconductor package and manufacturing method thereof |
| US7800208B2 (en) * | 2007-10-26 | 2010-09-21 | Infineon Technologies Ag | Device with a plurality of semiconductor chips |
| JP2013222829A (en) * | 2012-04-17 | 2013-10-28 | Taiyo Yuden Co Ltd | Circuit module and manufacturing method thereof |
| CN103400826B (en) * | 2013-06-21 | 2016-08-17 | 三星半导体(中国)研究开发有限公司 | Semiconductor packages and manufacture method thereof |
| CN103400816B (en) * | 2013-06-26 | 2016-08-10 | 三星半导体(中国)研究开发有限公司 | Packaging part and manufacture method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09148478A (en) * | 1995-11-21 | 1997-06-06 | Hitachi Ltd | Semiconductor integrated circuit device |
| US6034423A (en) * | 1998-04-02 | 2000-03-07 | National Semiconductor Corporation | Lead frame design for increased chip pinout |
| US6201298B1 (en) * | 1998-04-28 | 2001-03-13 | Nec Corporation | Semiconductor device using wiring tape |
-
2002
- 2002-06-28 CN CNB021231923A patent/CN1303685C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09148478A (en) * | 1995-11-21 | 1997-06-06 | Hitachi Ltd | Semiconductor integrated circuit device |
| US6034423A (en) * | 1998-04-02 | 2000-03-07 | National Semiconductor Corporation | Lead frame design for increased chip pinout |
| US6201298B1 (en) * | 1998-04-28 | 2001-03-13 | Nec Corporation | Semiconductor device using wiring tape |
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| CN1466206A (en) | 2004-01-07 |
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