CN1303676C - Semiconductor device for shortening length of wire bonding - Google Patents
Semiconductor device for shortening length of wire bonding Download PDFInfo
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- CN1303676C CN1303676C CNB021228728A CN02122872A CN1303676C CN 1303676 C CN1303676 C CN 1303676C CN B021228728 A CNB021228728 A CN B021228728A CN 02122872 A CN02122872 A CN 02122872A CN 1303676 C CN1303676 C CN 1303676C
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Abstract
The present invention relates to a semiconductor packaging piece for shortening the wiring length, which comprises a base plate, wherein a chip sticking region for connecting a semiconductor chip is arranged on the base plate; a plurality of welding wire pads are laid on the periphery of the chip sticking region; the surface of the base plate arranged between the chip sticking region and the welding wire pads is connected with a plurality of bridge components which are unevenly arrayed so that a first gold wire group connected with the chip and the bridge components in an electricity conduction mode, and a second gold wire group connected to the bridge components and the welding wire pads in an electrical property coupling mode are mutually communicated in an electrical property communication mode so as to be as midway connecting points for multiple times of wiring. A multi-times wiring mode replaces the single gold wire welding so as to obviously shorten the distance of each time of wiring. The present invention reduces the wire arc span and the wire arc height of single time of wiring. Meanwhile, the wire arc span is reduced to increase the supporting capability of gold wires from the connecting ends so as bear the impact of the module flow, and furthermore, the present invention prevents the gold wires from sweeping or sagging.
Description
Technical field
The invention relates to a kind of semiconductor package part, particularly relate to a kind of wire bonds type ball grid array (Wire Bond Ball Grid Array, WBBGA) semiconductor package part that shortens length of wire bonding.
Background technology
(Ball Grid Array, BGA) the encapsulation technology I/O link (I/O Connections) that possesses quantity sufficient connects requiredly to satisfy high density electronic building brick and electronic circuit ball grid array, has now become the encapsulation main flow of high-performance electronic product.Along with this method and technology is constantly progressive, the quantity of I/O link and density all significantly improve on the BGA semiconductor package part, thereby must on substrate, lay wire bond pad (Fingers) that a plurality of and this I/O link electrically lead to external electric connection point thick and fast as semiconductor chip, this semiconductor chip can carry out wire bonds (Wire Bonding), and to this wire bond pad, electrically connect is to external circuit again.
The wire bond pad layout type that generally provides the BGA semiconductor package part to use.As shown in Figure 1, be to be equipped with a substrate 10 earlier, connect on it and be equipped with semiconductor chip 12, and be to be formed with several weld pads (Bond Pads) 122 on these chip 12 surfaces; Most wire bond pads 103 that arc arranges are that ring places this semiconductor chip 12 peripheries; And some gold threads 13, weldering connects each weld pad 122 on this chip 12 with this wire bond pad 103 and as the external circuits of semiconductor chip 12 respectively.(this figure is graphic for the signal of simplifying, and only shows the part relevant with the present invention; The layout kenel of its actual enforcement encapsulation unit is the shape complexity more).
Right restriction because of traditional etching technique, in the most wire bond pads 103 that form on the substrate 10, each wire bond pad 103 minimum widith is about 3 mil (mil, be equivalent to the one thousandth inch), add that 103 beelines of adjacent wire bond pad are about 3 mils, therefore whenever setting up a wire bond pad 103 promptly need occupy the wide distance (shown in P among the figure) of about 6 mils.As shown in Figure 1, if these wire bond pad 103 circular rings are listed in this semiconductor chip 12 peripheries, and with the geometric center of semiconductor chip 12 as the center of circle, then each wire bond pad is 6n/2 π (wherein n is the quantity that is provided with of expression wire bond pad 103, and 6n then is the circumference that n wire bond pad constitutes) apart from the beeline R at chip 12 centers; In like manner, on the chip 12 weld pad 122 apart from the beeline at chip 12 centers as representing with d, the routing beeline of 122 of wire bond pad 103 and chip 12 weld pads then, that is bank span (Wire Span) (shown in s among the figure) should be R-d in theory; Thereby when I/O link on the substrate 10 (not icon) flood tide increase caused this equal solder line spot 103 that quantity n showed increased is set, the circumference 6n that this equal solder line spot 103 forms can expand thereupon.Relatively the bank span s of 122 of this equal solder line spot 103 and chip 12 weld pads also can significantly increase.
Bank span s increase can make bank length (Wire Length) elongation, and (general bank length is influenced by radian, be about 1.2 times of bank span), thereby cause the routing operation to carry out difficulty, and when carrying out the colloid encapsulation, very easily be subjected to mould stream to impact the initiation bonding wire and topple over (Wire Sweeping) or sagging (Wire Sagging), (dotted portion is script gold thread position among the figure, now is subjected to mould stream to impact (as shown by arrows) and causes skew) and then formation short circuit as shown in Figure 2.United States Patent (USP) the 6th, 031, No. 281 cases were once invented and are a kind ofly set up many pseudo-bonding wires (Dummy Wire) in the strongest die sites of mould stream impulsive force and keep out mould stream to increase the gold thread resistance, reduced bonding wire and toppled over phenomenon and take place; Yet the complexity that can increase manufacture process that is provided with of pseudo-bonding wire makes the bonding wire cost promote significantly again.
For improving the problems of above-mentioned routing operation, United States Patent (USP) the 5th, 898, No. 213 case proposes a kind of wire bond pad layout type that shortens the routing distance in addition.As shown in Figure 3, be compared to traditional wire bond pad layout type, bank length can increase and to elongate because of wire bond pad is provided with quantity, this technology be with adjacent wire bond pad 110 ', 111 ' be interlace mode about in the of (Staggered) circular row in chip 12 ' periphery to constitute a circumference; Wherein, the wire bond pad far away apart from chip 12 ' center be defined as the first wire bond pad group 110 ', apart from the nearer person in chip 12 ' center be defined as the second wire bond pad group 111 '.Because of this first wire bond pad 110 ' all arrange on same cambered surface but the row that intermesh are put with second wire bond pad 111 ' be not, therefore in fact two adjacent wire bond pads 110 ', 111 ' minimum spacing P2 be 3 mils because of cross effect reduces by half, so wire bond pad is 3n/2 π (that is 1/2R) apart from the beeline (not icon) of chip center, obviously shortens bank routing distance.
Though can obviously shorten bank routing distance on this technical know-how, yet during practice because this first wire bond pad group 110 ' with the second wire bond pad group 111 ' be to be staggered arrangement mutually, the gold thread welding position also must cooperate the wire bond pad position and adjust, usually can't identification wire bond pad position when wire bonder (Bonder) is carried out routing, cause gold thread fail correct weldering link wire bond pad on the contrary routing to the conductive trace that connects wire bond pad, cause weldering knot inferior quality.
Summary of the invention
Main purpose of the present invention provides to connect on a kind of substrate surface between chip adhered zone and wire bond pad establishes several bridge assemblies, the usefulness that links bank during for routing repeatedly, so as to shortening each routing bank length, the BGA semiconductor packages of lifting member routing operability.
Another object of the present invention provides to connect on a kind of substrate surface between chip adhered zone and wire bond pad establishes several bridge assemblies, the usefulness that links bank during for routing repeatedly, so as to shortening each routing bank length, increase link and impact to bear mould stream, make gold thread avoid the BGA semiconductor package part of toppling over or sinking for the bank enabling capabilities.
A further object of the present invention provides the existing method and technology of a kind of utilization, and several bridge assemblies of irregular configuration on the substrate surface between chip adhered zone and wire bond pad cause packaging cost to meet the BGA semiconductor package part of economic benefit.
In view of above-mentioned and other purpose, the present invention is to comprise in order to the semiconductor package part that shortens length of wire bonding: a substrate, its surface are provided with a chip adhered zone and this chip adhered zone is peripheral and numerous wire bond pads that have been periphery; Several bridge assemblies are that irregular row place on the substrate surface between this chip adhered zone and the wire bond pad, connect the usefulness of bank during for routing repeatedly; At least one chip semiconductor chip, this die bonding is formed with most weld pads on this chip adhered zone and its action face; One first gold thread group and one second gold thread group are that this chip pad and this bridge assembly are provided respectively, and are electrically conducted between this bridge assembly and this equal solder line spot; And one in order to coat this semiconductor chip, the packing colloid of most gold threads and these bridge assemblies.
Set up the purpose of bridge assembly in the packaging part, the master links this first gold thread group and the second gold thread group in order to conduction, successfully to implement repeatedly routing operation; And even make the electric signal of semiconductor chip output to be passed to the wire bond pad external circuit via chip pad, the first gold thread group, bridge assembly, the second gold thread group.
Encapsulating structure compared to the single gold thread welding of tradition, semiconductor package part of the present invention shortens the routing distance of each routing significantly by routing mode repeatedly, reduce the bank span and the bank height of single routing, so as to promoting the routing operability, while bank span reduces to impact to bear mould stream increasing the enabling capabilities of link for gold thread, can avoid gold thread to topple over (WireSweeping) or sagging (Wire Sagging) generation then.
Description of drawings
Below describe characteristics of the present invention and effect in detail with the preferred embodiment conjunction with figs.:
Accompanying drawing 1 is for looking simplified schematic diagram on existing its part plan of BGA semiconductor package part;
Accompanying drawing 2 is the schematic perspective views that are subjected to the influence of potting resin mould stream for the encapsulating structure of accompanying drawing 1;
Accompanying drawing 3 is to be United States Patent (USP) the 5th, 898, and the semiconductor package part of No. 213 cases invention is looked schematic diagram on it;
Accompanying drawing 4 is the generalized sections that shorten the semiconductor package part of length of wire bonding for the present invention;
Accompanying drawing 5A is in the semiconductor package part of the present invention, looks schematic diagram on the substrate;
Accompanying drawing 5B imposes repeatedly part sectioned view behind the routing for semiconductor package part of the present invention;
Accompanying drawing 5C imposes repeatedly plane top view behind the routing for semiconductor package part of the present invention;
Accompanying drawing 6 is the section comparison diagrams for semiconductor package part of the present invention and existing encapsulating structure; And,
Accompanying drawing 7 is the mould stream perspective views that carry out mold pressing for the semiconductor package part of second embodiment of the invention.
Embodiment
Below to be conjunction with figs. 4 describe the present invention in detail to accompanying drawing 6, and (following each accompanying drawing all be that the signal of simplification is graphic in order to the semiconductor package part specific embodiment that shortens length of wire bonding, and only show the assembly relevant with the present invention, this class component is not to draw with actual quantity or dimension scale; Actual encapsulating structure layout may be complicated more), only the bridge assembly in the encapsulating structure of the present invention is that irregular row place on the substrate surface for the usefulness of routing repeatedly, then (Wire Bond Ball Grid Array, WBBGA) semiconductor package part is as the illustration of the embodiment of the invention with wire bonds type ball grid array.
Embodiment 1
As shown in Figure 4, semiconductor package part 2 of the present invention is to comprise a substrate 20, which is provided with a chip adhered zone 202, and these chip adhered zone 202 peripheral and numerous wire bond pads 203 that have been periphery; Several bridge assemblies 21 are that irregular row place on substrate 20 surfaces between this chip adhered zone 202 and the wire bond pad 203, connect the usefulness of bank during for routing repeatedly; At least one chip semiconductor chip 22 is to bond on this chip adhered zone 202; Some gold threads 23, in order to this chip 22 and this bridge assembly 21 to be provided, and the electrical lotus root of 203 of this bridge assembly 21 and this equal solder line spots connects; And one in order to coat this semiconductor chip 22, the packing colloid 24 of most gold threads 23 and these bridge assemblies 21.
Accompanying drawing 5A is the substrate top view for BGA semiconductor package part of the present invention.As shown in the figure, this substrate 20 has positive 200 and one opposing backside surface 201, have a chip adhered zone 202 bonding on it in planning in advance on these substrate 20 fronts 200, and these chip adhered zone 202 peripheries are to be equipped with several to connect conductive traces (not icon) and the slightly curved wire bond pad that arranges 203 for semiconductor chip (not icon); On 20 fronts 200 of the substrate between this chip adhered zone 202 and each wire bond pad 203, be formed with most irregular arranged bridge assemblies 21, link the usefulness of bank during for each routing.These bridge assemblies 21 are the metal structure of a similar weld pad, having one first weld part 210 and another second weld part 211 on it respectively connects for different gold thread groups (not icon) weldering, right have preferable weldering knot property for making between these bridge assemblies 21 and bonding wire (not icon), generally can be in these bridge assembly 21 surperficial plated with nickel and gold (Ni/Au).
The irregular row mode of putting of these bridge assembly 21 employings is disseminated to and must makes 21 of adjacent bridge connected components have bigger accommodation space on the substrate 20, so can overcome the restriction of etching technique for spacing width, make semiconductor package part of the present invention not improve under the packaging cost, the existing method of utilization is implemented.
See also accompanying drawing 5B (phantom) and accompanying drawing 5C (plane top view), use at least one chip semiconductor chip 22, this chip 22 has an action face 220 (promptly being equipped with the surface of most electronic circuits and electronic building brick) and a non-action face 221, and is to be equipped with several solder pad 222 on this action face 220; Borrow an adhesive layer 223 that this semiconductor chip 22 is bonded on these substrate 20 chip adhered zones 202, carry out twice routing operation again: at first according to now being connected on these bridge assembly 21 first weld parts 210 to form one first gold thread group 230 from routing on these chip 22 weld pads 222 with the routing mode, afterwards, carry out second time routing from these bridge assembly 21 second weld parts 211 again and be attached on this wire bond pad 203, this for the second time the bank of routing promptly be called the second gold thread group 231.(embodiment of the invention explains to have only real operation situation must look the practical layout kenel of this bridge assembly on substrate and carry out three times even repeatedly routing operation in twice routing mode as example.) last, see accompanying drawing 4 again, coat this semiconductor chip 22, numerous bridge assembly 21, the first gold thread group 230 and the second gold thread group 231 with a packing colloid 24, promptly finish BGA semiconductor package part 2 of the present invention.
The characteristics of semiconductor package part 2 of the present invention are to have additional most irregular arranged bridge assemblies 21 on substrate 20 fronts 200, this bridge assembly 21 has one first weld part 210 and one second weld part 211 simultaneously, so as to as first gold thread group 230 on this first weld part 210 and 231 relays that are electrically connected of the second gold thread group (RelayContacts) on second weld part 211, cause the electric signal of semiconductor chip 22 I/O can pass through weld pad 222, the first gold thread group 230, bridge assembly 21, the second gold thread group 231 is passed on the wire bond pad 203 again and forms one and provide chip to be communicated with outside conductive path.
Consult shown in the accompanying drawing 6, compared to only through the existing encapsulating structure (shown in accompanying drawing 6 left sides) of a routing, the routing technology that adopts semiconductor package part of the present invention (shown in accompanying drawing 6 right-hand parts) repeatedly can shorten the bank span (L is kept to L1 and L2) and the bank height (Loop Height) (H reduces to H1 and H2) of each routing significantly, the routing degree of difficulty is reduced and promotes its routing operability (Operability); Simultaneously, reduce the bank arc length link is improved for the supportive of bank, make that gold thread is unlikely impacted by mould stream and be offset, further safeguard the quality of bonding wire operation.
Embodiment 2
Shown in the accompanying drawing 7 second embodiment for semiconductor package part of the present invention, the structure of present embodiment and aforementioned first embodiment is roughly the same, its difference is that this bridge assembly 21 is not on substrate 20 surfaces that extensively are arranged between semiconductor chip 22 and all wire bond pads 203, but settle the strongest position of mould stream impulsive force when selecting the colloid encapsulation procedure.As shown in the figure, after forming the resin mold stream 240 inflow die cavitys 26 of packing colloid (not icon), bearing mould with vertical each other end 224 positions, angle, chip 22 diagonal angle of mould flow path direction (shown in arrow among the figure), to flow 240 impulsive forces the strongest, cause 230 rounds moulds of gold thread stream 240 to impact and topple over or sink, satisfy and to strengthen gold thread 230 enabling capabilities in several bridge assemblies 21 of this place addition and keep out mould and flow 240 and attack.Present embodiment only is provided with bridge assembly 21 in segment chip 22 positions, and this measure can not only reduce the routing complexity, also can more effectively save packaging cost.
Above-mentioned specific embodiment only is in order to explain characteristics of the present invention and effect; but not in order to limit enforcement category of the present invention; in claims of the present invention institute restricted portion, any utilization institute of the present invention content and the equivalence finished changes and modify all should be within this patent protection range.
Claims (9)
1. a semiconductor package part is characterized in that, this semiconductor package part comprises:
One substrate which is provided with a chip adhered zone, and a plurality of be periphery outside this chip adhered zone and with the conductive part that the external world electrically conducts, wherein, be equipped with a plurality of irregular arranged bridge assemblies on the substrate between this chip adhered zone and this conductive part in addition;
At least one chip semiconductor chip is to be bonded on this chip adhered zone;
A plurality of first gold threads are electrically conducted to this bridge assembly for this semiconductor chip;
A plurality of second gold threads provide and carry out electrical lotus root between this bridge assembly and this conductive part and connect; And
One packing colloid is in order to coat this semiconductor chip, bridge assembly, first gold thread and second gold thread.
2. semiconductor package part as claimed in claim 1 is characterized in that, this semiconductor package part is to be wire bonds type ball grid array (BGA) semiconductor package.
3. semiconductor package part as claimed in claim 1 is characterized in that, this conductive part is to be a wire bond pad.
4. semiconductor package part as claimed in claim 1 is characterized in that, this bridge assembly is the end position place, angle, diagonal angle that is arranged in this semiconductor chip.
5. semiconductor package part as claimed in claim 1 is characterized in that, this bridge assembly is to be a metal structure, and has one first weld part and another second weld part simultaneously.
6. semiconductor package part as claimed in claim 1 is characterized in that, this bridge assembly surface is coated with gold and nickel.
7. semiconductor package part as claimed in claim 1 is characterized in that, this semiconductor chip has an action face and a relative non-action face, and is to be equipped with several solder pad on this action face.
8. as claim 1 or 4 or 6 described semiconductor package parts, it is characterized in that this first gold thread is to electrically connect this solder pad to this first weld part.
9. as claim 1 or 4 or 6 described semiconductor package parts, it is characterized in that this second gold thread is to electrically connect this second weld part to this conductive part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021228728A CN1303676C (en) | 2002-06-18 | 2002-06-18 | Semiconductor device for shortening length of wire bonding |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021228728A CN1303676C (en) | 2002-06-18 | 2002-06-18 | Semiconductor device for shortening length of wire bonding |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1466198A CN1466198A (en) | 2004-01-07 |
| CN1303676C true CN1303676C (en) | 2007-03-07 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021228728A Expired - Lifetime CN1303676C (en) | 2002-06-18 | 2002-06-18 | Semiconductor device for shortening length of wire bonding |
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| Country | Link |
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| CN (1) | CN1303676C (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1328771C (en) * | 2004-05-09 | 2007-07-25 | 江苏长电科技股份有限公司 | Technique for forming low radian bonding wire of mini semiconductor device packaging |
| CN102222655B (en) * | 2010-04-13 | 2013-10-09 | 鸿富锦精密工业（深圳）有限公司 | Chip adapter plate |
| CN101944512A (en) * | 2010-09-30 | 2011-01-12 | 无锡中微高科电子有限公司 | Switching base plate packaged by integrated circuit |
| CN102800765A (en) * | 2012-03-21 | 2012-11-28 | 深圳雷曼光电科技股份有限公司 | Light emitting diode (LED) packaging structure and packaging process for same |
| CN102623618A (en) * | 2012-04-12 | 2012-08-01 | 深圳雷曼光电科技股份有限公司 | Double-bending reverse bank type light-emitting diode (LED) packaging structure and packaging technology thereof |
| CN104821307B (en) * | 2015-04-27 | 2017-12-19 | 上海伊诺尔信息技术有限公司 | Belt for smart card and method for packing |
| CN117438400A (en) * | 2023-12-18 | 2024-01-23 | 泉州市三安集成电路有限公司 | Semiconductor packaging structure and packaging method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5365409A (en) * | 1993-02-20 | 1994-11-15 | Vlsi Technology, Inc. | Integrated circuit package design having an intermediate die-attach substrate bonded to a leadframe |
| JPH08139225A (en) * | 1994-11-11 | 1996-05-31 | Hitachi Chem Co Ltd | Semiconductor package and its manufacture |
| US5761048A (en) * | 1996-04-16 | 1998-06-02 | Lsi Logic Corp. | Conductive polymer ball attachment for grid array semiconductor packages |
| US6160313A (en) * | 1998-03-31 | 2000-12-12 | Fujitsu Limited | Semiconductor device having an insulating substrate |
-
2002
- 2002-06-18 CN CNB021228728A patent/CN1303676C/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5365409A (en) * | 1993-02-20 | 1994-11-15 | Vlsi Technology, Inc. | Integrated circuit package design having an intermediate die-attach substrate bonded to a leadframe |
| JPH08139225A (en) * | 1994-11-11 | 1996-05-31 | Hitachi Chem Co Ltd | Semiconductor package and its manufacture |
| US5761048A (en) * | 1996-04-16 | 1998-06-02 | Lsi Logic Corp. | Conductive polymer ball attachment for grid array semiconductor packages |
| US6160313A (en) * | 1998-03-31 | 2000-12-12 | Fujitsu Limited | Semiconductor device having an insulating substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1466198A (en) | 2004-01-07 |
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