CN1302403C - Optimization verification method for processor bus - Google Patents
Optimization verification method for processor bus Download PDFInfo
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- CN1302403C CN1302403C CNB2004100028893A CN200410002889A CN1302403C CN 1302403 C CN1302403 C CN 1302403C CN B2004100028893 A CNB2004100028893 A CN B2004100028893A CN 200410002889 A CN200410002889 A CN 200410002889A CN 1302403 C CN1302403 C CN 1302403C
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- 238000005457 optimization Methods 0.000 title claims abstract description 57
- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000012795 verification Methods 0.000 title claims abstract description 21
- 238000010200 validation analysis Methods 0.000 claims description 9
- 238000009825 accumulation Methods 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 238000004804 winding Methods 0.000 claims 1
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Abstract
The present invention relates to an optimization verification method for a processor bus. Firstly, the bus starting frequency bandwidth, the bus starting frequency, the bus operation frequency bandwidth and the bus operation frequency of a bus between a processor and a northern bridge chip set are set; then, commands for reading a southern bridge chip set are sent; next, the southern bridge chip set outputs a bus interrupt signal to interrupt the online of the bus between the processor and the northern bridge chip set, starts the count value of a counter and outputs an optimization verification signal with first electric levels; when the count value of the counter is accumulated to reach a set value, the southern bridge chip set outputs a bus connection signal and converts the electric levels of the optimization verification signal into second electric levels; finally, according to the bus connection signal, and the optimization verification signal of the second electric levels, the bus connects the processor and the northern bridge chip set again, and works in the frequency bandwidth and the bus operation frequency of another bus.
Description
Technical field
The present invention relates to a kind of processor bus optimization verification method, particularly relate to the processor bus optimization verification method of a kind of AMD of being applied to K8 operating platform (plat form).
Background technology
Therefore characteristics such as the easy enforcement of standard software that Legacy I/O bus structure are low-cost because of it and utilization has been set up and hardware standard are widely used in the embedded system (embedded system).Right its highest operating frequency only is about 66MHz, and therefore, operating frequency reaches the above processor of 500MHz now, must use to have the bus of higher frequency range and operating frequency.
Lightning data transmission I/O bus (Lightning Data Transport, LDT, I/O Bus), also claim high-transmission I/O bus (Hyper Transport, HT, I/O Bus), satisfied the required high frequency range demand of present computer network, communication system and other embedded system, had dirigibility, extendibility and an easy-to-use bus architecture for a kind of.LDT I/O bus can provide processor of future generation and the required frequency range (width) of communication system, moreover LDT I/O bus also has functions such as adjustable bus bandwidth and operating speed, to meet the demand of power supply, space and cost.
The frequency range of tradition LDT I/O bus and the optimization of operating frequency must by carry out LDT bus interruption (disconnection) and reconnect (reconnection) program so that the LDT bus operation in the frequency range and the operating frequency of expecting.
Fig. 1 shows traditional computer system architecture figure with LDT bus.As shown in the figure, has a LDT bus 12 between processor 10 and the north bridge 14.At this, processor is an example with the K8CPU of AMD manufacturing.And has another bus 16 between north bridge 14 and the south bridge 18.In the time will carrying out processor power management program and bus optimization procedure, LDT bus 12 between processor 10 and north bridge 14 must be carried out and interrupt and online again operations, the level that aforesaid operations need be subjected to the signal LDTSTOP# that exported by south bridge 18 change control.The level of signal LDTSTOP# is first level (is example with the high level) in normal conditions, when south bridge drags down (is example with the low level) when being second level with the level of signal LDTSTOP#, this is called setting (assert) signal LDTSTOP#, and when processor 10 and north bridge 14 all received the signal LDTSTOP# of setting (assert), then LDT bus 12 was interrupted online.At this moment, the counter 19 of south bridge 18 inside begins counting, wait to reach a set value after, then south bridge reverts to first level (high level) originally again with the level of signal LDTSTOP#, this is called releasing (deassert) signal LDTSTOP#.When processor 10 and north bridge 14 all received the signal LDTSTOP# of releasing (deassert), then LDT bus 12 was online again, applying mechanically new LDT bus operation frequency and frequency range, or the operating voltage of processor and frequency.
Fig. 2 shows the frequency range and the optimized operational flowchart of operating frequency of traditional LDT I/O bus.At first, after system power supply starts, by basic input/output (Basic Input/OutputSystem, BIOS) beginning of opening of initial (initialize) LDT bus is set, and comprises that the bus of setting the LDT bus between processor and the north bridge opens beginning frequency range and bus and opens bus operation bandwidth and operating frequency (S1) when beginning frequency and optimization.For instance, behind computer system starting, bus opens the beginning frequency range and can be 8, but can be adjusted to 16 during optimization.Moreover bus opens the beginning frequency and can be 200MHz, but can the best turn to 400MHz, 600MHz or 800MHz equifrequent.Bus operation bandwidth and operating frequency during above-mentioned optimization are set among the BIOS.Next, BIOS is initial treatment device and comprise north bridge and the power management buffer of the chipset of south bridge in regular turn, and bus operation bandwidth and operating frequency (S2) when setting optimization.Next, BIOS recovers the counter (S3) of (Auto Resume) automatically in south bridge startup one, next, BIOS and send reading command (PowerMana gement I/O, PMIO) skew 15th is to set (asserting) signal LDTSTOP# (S4) to the input/output port of south bridge.At this, it is to be converted to low level signal for the signal LDTSTOP# of high level originally that signal LDTSTOP# is carried out the operation of setting.When south bridge was set at low level with signal LDTSTOP#, then the LDT bus between processor and north bridge promptly interrupted connecting (S5).
Next, when the count value of the counter that is started in step S3 reached a set value, then south bridge was high level (S6) with signal LDTSTOP# releasing (deassert), also soon before has been set at low level signal LDTSTOP# and has reverted to high level.After signal LDTSTOP# reverts to high level again, then the LDT bus between processor and north bridge promptly recovers to connect (S7), and be pursuant to optimized bus operation bandwidth that previous BIOS sets and operating frequency operation frequency range and frequency as the LDT bus after online again, finished the frequency range of LDT I/O bus and the optimization of operating frequency.
Above-mentioned bus optimization procedure must just can be finished the frequency range of adjustment bus and the operation of operating frequency by the interruption of carrying out the LDT bus and online again operation.Yet if the interruption of LDT bus and online again operation are not carried out fully, the state of bus can't change, and can't reach the optimized effect of bus, therefore causes system effectiveness effectively to promote.
Yet conventional art is judging that whether bus has been finished on the optimization procedure, has met with many difficulties.With software, the software engineer can't determine almost whether bus has finished optimization procedure.With hardware, the level that the system engineer must utilize oscillographic probe directly to detect the pin of output signal LDTSTOP# changes judges whether bus has finished optimization procedure, the trouble that this detecting operation is suitable.Moreover, even if having detected the level of the pin of output signal LDTSTOP# is set (assert) and removes (deassert), if south bridge 18 and processor 10 or north bridge 14 be the online situation that opens circuit of circuit of any one wherein, then processor 10 can't receive the signal LDTSTOP# that is set (assert) and removes (deassert) simultaneously with north bridge 14, so the frequency range of bus and operating frequency still can optimizations.
Summary of the invention
In view of this, in order to address the above problem, fundamental purpose of the present invention provides a kind of bus optimization verification method, the program that is set (assert) and removes (deassert) with confirmation signal LDTSTOP# is performed fully and finishes, and causes the not good situation of total system usefulness because bus is not optimized to avoid computer system.
For realizing above-mentioned purpose, the present invention proposes a kind of processor bus optimization verification method.At first, the bus of setting bus between processor and the north bridge opens the beginning frequency range and opens beginning frequency and bus operation bandwidth and bus operation frequency with bus, sets the optimization of this bus and operates frequency range and optimization operating frequency; Next, send the instruction of reading south bridge, next, the line of the bus between south bridge output bus interrupt handler and the north bridge chipset, and open the count value of beginning counter and the optimization validation signal that output has first level.When the accumulation of the count value of counter reaches a set value, then the south bridge output bus connects signal, and is second level with the level conversion of above-mentioned optimization validation signal.At last, bus reconnects processor and north bridge according to the optimization validation signal that bus connects the signal and second level, and works in optimization bus operation bandwidth and optimization bus operation frequency.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and be described with reference to the accompanying drawings as follows.
Description of drawings
Fig. 1 shows the computer system architecture figure that tradition has the LDT bus.
Fig. 2 shows the frequency range and the optimized operational flowchart of operating frequency of traditional LDT I/O bus.
Fig. 3 shows the computer system architecture figure according to the described LDT of the having bus of the embodiment of the invention.
Fig. 4 shows the circuit diagram according to the described level sensitive circuit of the embodiment of the invention.
Fig. 5 shows the operational flowchart according to the described processor bus optimization of embodiment of the invention verification method.
Symbol description
10～processor
12～LDT bus
14～north bridge
16～bus
18～south bridge
21～level sensitive circuit
LDTSTOP#～signal
Embodiment
Consult Fig. 3, Fig. 3 shows the computer system architecture figure according to the described LDT of the having bus of the embodiment of the invention.As shown in the figure, have a LDT bus 22 between processor 20 and the north bridge 24, or claim the HT bus.At this, processor 20 is that the K8CPU with the AMD manufacturing is an example.And has another bus 26 between north bridge 24 and the south bridge 28.In the time will carrying out the bus optimization procedure, LDT bus between processor 20 and north bridge 24 22 must be carried out and interrupt and online again operations, the level that aforesaid operations is subjected to the signal LDTSTOP# that south bridge 28 exports change control.The level of signal LDTSTOP# is first level (is example with the high level) in normal conditions, when south bridge 29 drags down (is example with the low level) when being second level with the level of signal LDTSTOP#, this is called setting (assert) signal LDTSTOP#, and then LDT bus 22 is interrupted online.At this moment, the counter 29 of south bridge 28 inside begins counting, after waiting to reach a set value, then south bridge reverts to first level (high level) originally again with the level of signal LDTSTOP#, this is called releasing (deassert) signal LDTSTOP#, then LDT bus 22 is online again, to apply mechanically new LDT bus operation frequency and frequency range.
Moreover, according to the described bus optimization of embodiment of the invention verification method, set up a signal level detection circuit 21 and judge the signal LDTSTOP# program whether executed is set (assert) and removed (deassert).
Fig. 4 shows the circuit diagram according to the described level sensitive circuit 21 of the embodiment of the invention.Comprise a trigger 40 according to the described level sensitive circuit 21 of the embodiment of the invention, and be coupled to trigger 40 the D terminal or logic gate 42.In this level sensitive circuit 21, system or the signal of the input end 42A input logic level " 1 " of logic gate 42, this moment is in the signal LSTSTOP_STATUS of the Q of trigger 40 terminal output logic level " 1 ".When the signal LDTSTOP# that is received when the RST of trigger 40 terminal rose to high level by low level, then the logic level of the signal LSTSTOP_STATUS of the Q terminal of trigger 40 output was removed and is " 0 ".Because the level of signal LDTSTOP# is to remain in high level under normal condition, when being set (assert), signal LDTSTOP# is low level, when being disengaged (deassert) for high level again, the logic level of the signal LSTSTOP_STATUS that the Q terminal of trigger 40 is exported just can be " 0 ".Therefore, exported, can be judged that signal LDTSTOP# finishes the program of setting (assert) and removing (deassert) of carrying out by the Q terminal of detection triggers 40.
Moreover, can place the output terminal of south bridge 20 about level sensitive circuit 21 set positions, and the input end of processor 20 and north bridge 24 received signal LDTSTOP#, as shown in Figure 3.In addition, circuit structure according to the level sensitive circuit shown in embodiment of the invention Fig. 4 only is a preferred embodiment, yet the operation of detection signal LSTSTOP_STATUS logic level equally also can utilize other circuit to realize, is not limited to the level sensitive circuit structure shown in Fig. 4.
Fig. 5 shows the operational flowchart according to the described processor bus optimization of embodiment of the invention verification method.According to the embodiment of the invention, at first, after system power supply starts, by basic input/output (Basic Input/Output System, BIOS) beginning of opening of initial (initialize) LDT bus is set, and comprises that the bus of setting the LDT bus between processor and the north bridge opens beginning frequency range and bus and opens bus operation bandwidth and operating frequency (S21) when beginning frequency and optimization.For instance, bus opens the beginning frequency range and can be 8, but can be adjusted to 16 during optimization.Moreover bus opens the beginning frequency and can be 200MHz, but can the best turn to 400MHz, 600MHz or 800MHz equifrequent.Bus operation bandwidth during above-mentioned optimization and operating frequency system are set among the BIOS.Next, by BIOS initial treatment device and comprise north bridge and the power management buffer of the chipset of south bridge in regular turn, to handle relevant power settings (S22).Next, BIOS is set in (S23) in the buffer with optimized operation frequency range of the bus of the LDT bus between processor and the north bridge and operating frequency, for example, bus optimization operation frequency range is set at 16, bus optimization operating frequency is set at 800MHz.Next, BIOS recovers the counter (S24) of (Auto Resume) automatically in south bridge startup one.When the count value of the counter of automatic recovery (Auto Resume) is accumulated to a set value, then remove (deassert) signal LDTSTOP#.
Next, at the signal of the input end 42A input logic level " 1 " of the logic gate 42 of as shown in Figure 4 level sensitive circuit 21, make the signal LSTSTOP_STATUS (S25) of Q terminal output logic level " 1 " of trigger 40.Next, BIOS sends reading command (Power Management I/O, PMIO) skew 15th is to set (asserting) signal LDTSTOP# (S26) to the input/output port of south bridge.At this, it is to be converted to low level signal for the signal LDTSTOP# of high level originally that signal LDTSTOP# is carried out the operation of setting.When south bridge was set at low level with signal LDTSTOP#, then the LDT bus between processor and north bridge promptly interrupted connecting (S27).
Next, when the count value of the counter that is started at step S24 reached a set value, then south bridge was high level (S28) with signal LDTSTOP# releasing (deassert), also soon before has been set at low level signal LDTSTOP# and has reverted to high level.After signal LDTSTOP# releasing (deassert) is high level, since signal LDTSTOP# be coupled to level sensitive circuit 21 the RST terminal, so the logic level of the signal LSTSTOP_STATUS of the Q terminal of trigger 40 output remove for " 0 " (S29).Next, the logic level (S30) of the signal LSTSTOP_STATUS of the Q terminal of detection triggers 40 output is with the complete routine of judging whether signal LDTSTOP# has finished setting (assert) and removed (deassert).Next, processor judge the logic level of signal LSTSTOP_STATUS of the Q terminal output of trigger 40 whether be " 0 " (S31), if be not " 0 ", then get back to step S30, the logic level of the signal LSTSTOP_STATUS of the Q terminal output of continuation detection triggers 40.If the logic level of judging LSTSTOP_STATUS in step S31 is " 0 ", then the LDT bus between processor and north bridge is promptly recovered to connect, and be pursuant to optimized bus operation bandwidth that previous BIOS sets and operating frequency operation frequency range and frequency (S32) as the LDT bus after online again, finished the frequency range of LDT I/O bus and the optimization of operating frequency.
According to the described processor bus optimization of embodiment of the invention verification method, the logic level that is arranged at the LSTSTOP_STATUS that the level sensitive circuit 21 of south bridge exported by detection can be judged the complete routine whether signal LDTSTOP# has finished setting (assert) and removed (deassert).Moreover, if in the input end of received signal LDTSTOP# level sensitive circuit is set at north bridge or processor, the signal LDTSTOP# that also can guarantee to finish setting (assert) and remove (deassert) complete routine normally is connected to north bridge or processor, confirms that bus between north bridge and processor can follow the variation of signal LDTSTOP# level and finish really and interrupt online and recover online operation.
Though the present invention discloses as above with preferred embodiment; so it is not in order to limit scope of the present invention; those skilled in the art can do some changes and retouching under the premise without departing from the spirit and scope of the present invention, so protection scope of the present invention is as the criterion with claim of the present invention.
Claims (7)
1. processor bus optimization verification method, the South Bridge chip group that is applicable to a processor, a north bridge chipset, is coupled to the bus between this processor and the north bridge chipset and is coupled to this north bridge chipset comprises the following steps:
The bus of setting bus between this processor and the north bridge chipset opens the beginning frequency range and opens begin frequency and bus operation bandwidth and bus operation frequency with bus;
Set the optimization operation frequency range and the optimization operating frequency of this bus;
Send the instruction of reading this South Bridge chip group;
After this instruction is received in this South Bridge chip winding, export a bus look-at-me interrupting the line of the bus between this processor and the north bridge chipset, and open the count value of beginning one counter, and output has an optimization validation signal of one first level;
When the accumulation of the count value of this counter reaches a set value, then this South Bridge chip group is exported a bus and is connected signal, and is one second level with the level conversion of this optimization validation signal; And
The optimization validation signal that this bus connects signal according to this bus and has second level reconnects this processor and north bridge chipset, and works in optimization bus operation bandwidth and optimization bus operation frequency.
2. processor bus optimization verification method as claimed in claim 1, wherein this bus look-at-me and bus connect signal and are used to set and remove the signal of being exported by an output terminal of this South Bridge chip group.
3. processor bus optimization verification method as claimed in claim 1, wherein this bus look-at-me and bus connection signal is exported by same output terminal.
4. processor bus optimization verification method as claimed in claim 1, wherein this optimization validation signal is exported by a level sensitive circuit.
5. processor bus optimization verification method as claimed in claim 4, this level sensitive circuit one or logic gate of comprising a trigger and being coupled to this trigger wherein, when this South Bridge chip group is exported this bus look-at-me, then this trigger output has the optimization validation signal of first level, when this South Bridge chip group was exported this bus connection signal, then this trigger output had the optimization validation signal of second level.
6. processor bus optimization verification method as claimed in claim 4, wherein this level sensitive circuit is arranged at the output terminal of this South Bridge chip group.
7. processor bus optimization verification method as claimed in claim 4, wherein this level sensitive circuit is arranged at the input end of this north bridge chipset or processor.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100028893A CN1302403C (en) | 2004-01-20 | 2004-01-20 | Optimization verification method for processor bus |
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| CNB2004100028893A CN1302403C (en) | 2004-01-20 | 2004-01-20 | Optimization verification method for processor bus |
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| CN1558335A CN1558335A (en) | 2004-12-29 |
| CN1302403C true CN1302403C (en) | 2007-02-28 |
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| CNB2004100028893A Expired - Lifetime CN1302403C (en) | 2004-01-20 | 2004-01-20 | Optimization verification method for processor bus |
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| CN100395714C (en) * | 2005-05-28 | 2008-06-18 | 鸿富锦精密工业（深圳）有限公司 | Circuit for identificating front-end bus of central processor |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6038383A (en) * | 1997-10-13 | 2000-03-14 | Texas Instruments Incorporated | Method and apparatus for determining signal line interconnect widths to ensure electromigration reliability |
| US6070233A (en) * | 1996-01-26 | 2000-05-30 | Unisys Corporation | Processor bus traffic optimization system for multi-level cache utilizing reflection status bit to indicate data inclusion in higher level cache |
| US6366967B1 (en) * | 1995-06-22 | 2002-04-02 | Datascape, Inc. | Open network system for i/o operation including a common gateway interface and an extended open network protocol with non-standard i/o devices utilizing device and identifier for operation to be performed with device |
| US6446209B2 (en) * | 1998-06-12 | 2002-09-03 | International Business Machines Corporation | Storage controller conditioning host access to stored data according to security key stored in host-inaccessible metadata |
| US20030005235A1 (en) * | 2001-07-02 | 2003-01-02 | Sun Microsystems, Inc. | Computer storage systems |
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2004
- 2004-01-20 CN CNB2004100028893A patent/CN1302403C/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6366967B1 (en) * | 1995-06-22 | 2002-04-02 | Datascape, Inc. | Open network system for i/o operation including a common gateway interface and an extended open network protocol with non-standard i/o devices utilizing device and identifier for operation to be performed with device |
| US6070233A (en) * | 1996-01-26 | 2000-05-30 | Unisys Corporation | Processor bus traffic optimization system for multi-level cache utilizing reflection status bit to indicate data inclusion in higher level cache |
| US6038383A (en) * | 1997-10-13 | 2000-03-14 | Texas Instruments Incorporated | Method and apparatus for determining signal line interconnect widths to ensure electromigration reliability |
| US6446209B2 (en) * | 1998-06-12 | 2002-09-03 | International Business Machines Corporation | Storage controller conditioning host access to stored data according to security key stored in host-inaccessible metadata |
| US20030005235A1 (en) * | 2001-07-02 | 2003-01-02 | Sun Microsystems, Inc. | Computer storage systems |
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