CN1294641C - Two-step deposition method for interlayer film on metal wiring - Google Patents
Two-step deposition method for interlayer film on metal wiring Download PDFInfo
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- CN1294641C CN1294641C CNB2003101095316A CN200310109531A CN1294641C CN 1294641 C CN1294641 C CN 1294641C CN B2003101095316 A CNB2003101095316 A CN B2003101095316A CN 200310109531 A CN200310109531 A CN 200310109531A CN 1294641 C CN1294641 C CN 1294641C
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Abstract
The present invention relates to a method for depositing interlayer films on metal wiring, which uses two steps to deposit interlayer films and solves the problem of poor imbedibility of interlayer films. The present invention has the specific steps that firstly, interlayer films are deposited on the surface of a chip; secondly, the interlayer films are etched selectively; thirdly, metal films and titanium nitride / titanium films are deposited, and metal deposited layers and titanium nitride / titanium thin film layers are formed on the surface of the chip and the interlayer films; fourthly, metal wires are etched, and the deposited titanium nitride / titanium thin film layers and the metal layers are etched selectively; finally, a second interlayer film deposition is carried out by using a general plasma film forming mode. With the method, the interlayer films have favorable imbedibility, and the problem of metal hollow cavities can be solved. Meantime, the general plasma film forming mode is used in the second film forming step, so that plasma damage and heat conducting process are reduced.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, especially relate to a kind of on the metal line of chip between illuvium two of film the step deposition process.
Background technology
In present integrated circuit, electric component develops towards the direction of Highgrade integration, therefore require various electric components volume and relevant between distance more and more littler.Along with reducing of size, it is big that depth-width ratio between wiring becomes, and in order to satisfy the imbedibility of interlayer film, must adopt the strong equipment of imbedibility, as high-density plasma etc.
See also shown in Figure 1ly, in manufacture process, the steps include: at first, carry out aluminium film deposition at chip surface, then, carry out the aluminum steel etching, selective etch falls part aluminium illuvium; Adopt the mode of high-density plasma to carry out the deposit of interlayer film at last.Adopt aforesaid way, can complete layer between the deposit of film, satisfy the imbedibility of interlayer film.
Adopt this new equipment also to produce new problem.Temperature is higher and should not control during film forming, temperature is too high causes following aluminium wiring alloy and thermophoresis etc. take place and cause produce in the middle of the aluminum steel empty.And because the temperature of high-density plasma mode is wayward, plasma damage is big, causes the problems such as inefficacy of device easily.
Therefore, for the cavity of not only satisfying the imbedibility of interlayer film but also can not cause aluminium, must consider that other better method solve existing these problems and contradiction.
Summary of the invention
The technical problem to be solved in the present invention provide a kind of on the metal line of chip between illuvium two of film the step deposition process, reduce the depth-width ratio between metal wire, thereby improve the imbedibility of interlayer film.
For solving the problems of the technologies described above, the present invention on the metal line of chip between illuvium the performing steps of two of film step deposition process be:
The first step is carried out the deposit of interlayer film on chip surface;
Second step, selective etch interlayer film;
The 3rd step, carry out metal film deposition, on the surperficial and above-mentioned interlayer film of chip, form the metal illuvium, comprise titanium nitride/titanium/aluminium;
In the 4th step, carry out the metal wire etching, selective etch metals deposited layer;
The 5th step: carry out the deposit of secondary interlayer film.
Because adopt said method, interlayer film of the present invention has imbedibility preferably, and be difficult for producing metal cavity problem.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is the deposition process of interlayer film of the metal line of prior art;
Fig. 2 is two step deposition process of the interlayer film of metal line of the present invention.
Wherein:
Titanium nitride/titanium/aluminium refers to the metal illuvium, and IMD1 refers to the interlayer film of first step deposit, and IMD2 refers to the interlayer film of the second step deposit.
Embodiment
Metal line among the present invention adopts the aluminium wiring.See also shown in Figure 2ly, long in the chip have a tungsten.
In carrying out interlayer film deposition process, at first, carry out the deposit of interlayer film on the said chip surface, make its surface form certain thickness interlayer film IMD1.Then carry out the etching of interlayer film, carve the interlayer film IMD1 that goes on the above-mentioned tungsten correspondence position, form the groove of corresponding above-mentioned tungsten position.Carry out aluminium film deposition, at the certain thickness aluminium illuvium of the surperficial accumulation of said chip and IMD1, its thickness is greater than the thickness of above-mentioned interlayer rete IMD1 because form groove in the abovementioned steps, so in the groove thickness of corresponding aluminium greater than the thickness of the aluminium of the position of film between retaining layer.Carry out the aluminum steel etching, keep the aluminium and the titanium nitride/titanium thin layer of corresponding above-mentioned tungsten position.At last, carry out the deposit of secondary interlayer film, adopt common plasma film forming technology, at the interlayer film IMD2 of the above-mentioned entire chip surface deposition second layer.
Because said method adopts two step method to carry out the deposit of interlayer film, the interlayer film of the first step carried out before the aluminium deposit, controlled its effect easily.After carrying out the aluminium deposit, owing to originally had the interlayer film of one deck, therefore, during the deposit of second layer interlayer film, the width between the wiring is constant, and because the less thick of second layer interlayer film, thereby the depth-width ratio between line diminishes, thus improve the imbedibility of interlayer film.And, do not need the high-density plasma film technique because only adopt general plasma film forming, therefore also can reduce isoionic damage and hot resume process.
In like manner, method of the present invention also is suitable for other metal line.
In sum, two step sedimentations of metal line of the present invention can effectively be finished inventor's goal of the invention, improve the imbedibility of interlayer film between metal line, metal cavity problem can not occur, and in manufacture process, can avoid ion dam age, guarantee reliability of products.
Claims (3)
1, a kind of on the metal line of chip between illuvium two of film the step sedimentations, implementation step is:
The first step is carried out the deposit of interlayer film on chip surface;
Second step, selective etch interlayer film;
The 3rd step, carry out metal film deposition, on the surperficial and above-mentioned interlayer film of chip, form the metal illuvium, comprise titanium nitride/titanium/aluminium;
In the 4th step, carry out the metal wire etching, selective etch metals deposited layer;
The 5th step: carry out the deposit of secondary interlayer film.
2, as claimed in claim 1 at two of film step sedimentations between illuvium on the metal line of chip, it is characterized in that: above-mentioned metal line can be aluminium wiring.
3, as claimed in claim 1 between the metal line illuvium of chip two step sedimentations of film, it is characterized in that: adopt general plasma film forming mode during interlayer film deposit for the second time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101095316A CN1294641C (en) | 2003-12-18 | 2003-12-18 | Two-step deposition method for interlayer film on metal wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101095316A CN1294641C (en) | 2003-12-18 | 2003-12-18 | Two-step deposition method for interlayer film on metal wiring |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1630059A CN1630059A (en) | 2005-06-22 |
| CN1294641C true CN1294641C (en) | 2007-01-10 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2003101095316A Expired - Fee Related CN1294641C (en) | 2003-12-18 | 2003-12-18 | Two-step deposition method for interlayer film on metal wiring |
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| CN (1) | CN1294641C (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020096775A1 (en) * | 2001-01-24 | 2002-07-25 | Ning Xian J. | A method of manufacturing a metal cap layer for preventing damascene conductive lines from oxidation |
| US6436808B1 (en) * | 2000-12-07 | 2002-08-20 | Advanced Micro Devices, Inc. | NH3/N2-plasma treatment to prevent organic ILD degradation |
| CN1399314A (en) * | 2001-07-23 | 2003-02-26 | 矽统科技股份有限公司 | Prepn of pore-free intermetallic dielectrical layer |
| CN1430261A (en) * | 2002-01-04 | 2003-07-16 | 矽统科技股份有限公司 | Manufacturing method of internal metal dielectric layer |
-
2003
- 2003-12-18 CN CNB2003101095316A patent/CN1294641C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6436808B1 (en) * | 2000-12-07 | 2002-08-20 | Advanced Micro Devices, Inc. | NH3/N2-plasma treatment to prevent organic ILD degradation |
| US20020096775A1 (en) * | 2001-01-24 | 2002-07-25 | Ning Xian J. | A method of manufacturing a metal cap layer for preventing damascene conductive lines from oxidation |
| CN1399314A (en) * | 2001-07-23 | 2003-02-26 | 矽统科技股份有限公司 | Prepn of pore-free intermetallic dielectrical layer |
| CN1430261A (en) * | 2002-01-04 | 2003-07-16 | 矽统科技股份有限公司 | Manufacturing method of internal metal dielectric layer |
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| CN1630059A (en) | 2005-06-22 |
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Effective date of registration: 20171214 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corp. Address before: No. 1188, Chuan Qiao Road, Pudong, Shanghai Patentee before: Shanghai Hua Hong NEC Electronics Co.,Ltd. |
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Granted publication date: 20070110 Termination date: 20211218 |
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