CN1293637C - 具有应变沟道的互补式金属氧化物半导体及其制作方法 - Google Patents
具有应变沟道的互补式金属氧化物半导体及其制作方法 Download PDFInfo
- Publication number
- CN1293637C CN1293637C CNB2003101019562A CN200310101956A CN1293637C CN 1293637 C CN1293637 C CN 1293637C CN B2003101019562 A CNB2003101019562 A CN B2003101019562A CN 200310101956 A CN200310101956 A CN 200310101956A CN 1293637 C CN1293637 C CN 1293637C
- Authority
- CN
- China
- Prior art keywords
- mentioned
- channel
- strained
- cmos
- metal oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000002360 preparation method Methods 0.000 title description 5
- 239000004065 semiconductor Substances 0.000 claims abstract description 168
- 150000004767 nitrides Chemical class 0.000 claims abstract description 77
- 230000000295 complement effect Effects 0.000 claims abstract description 71
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 108091006146 Channels Proteins 0.000 claims description 118
- 238000000034 method Methods 0.000 claims description 76
- 229910044991 metal oxide Inorganic materials 0.000 claims description 72
- 150000004706 metal oxides Chemical class 0.000 claims description 72
- 229910052710 silicon Inorganic materials 0.000 claims description 49
- 239000010703 silicon Substances 0.000 claims description 49
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 47
- 108090000699 N-Type Calcium Channels Proteins 0.000 claims description 42
- 102000004129 N-Type Calcium Channels Human genes 0.000 claims description 42
- 108010075750 P-Type Calcium Channels Proteins 0.000 claims description 42
- 238000005229 chemical vapour deposition Methods 0.000 claims description 41
- 150000002500 ions Chemical class 0.000 claims description 41
- 238000004519 manufacturing process Methods 0.000 claims description 36
- 230000015572 biosynthetic process Effects 0.000 claims description 35
- 238000002955 isolation Methods 0.000 claims description 31
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 29
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 29
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 12
- -1 silicon ion Chemical class 0.000 claims description 10
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 8
- 238000002347 injection Methods 0.000 claims description 7
- 239000007924 injection Substances 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 229910052786 argon Inorganic materials 0.000 claims description 4
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- 239000001307 helium Substances 0.000 claims description 4
- 229910052734 helium Inorganic materials 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 229910052724 xenon Inorganic materials 0.000 claims description 4
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 claims description 4
- 239000002184 metal Substances 0.000 abstract 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 57
- 239000000463 material Substances 0.000 description 29
- 239000000377 silicon dioxide Substances 0.000 description 27
- 230000006835 compression Effects 0.000 description 22
- 238000007906 compression Methods 0.000 description 22
- 230000003647 oxidation Effects 0.000 description 12
- 238000007254 oxidation reaction Methods 0.000 description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 239000000243 solution Substances 0.000 description 11
- 125000006850 spacer group Chemical group 0.000 description 10
- 229920005591 polysilicon Polymers 0.000 description 9
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 8
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 8
- 238000005530 etching Methods 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 230000005669 field effect Effects 0.000 description 6
- 239000012212 insulator Substances 0.000 description 6
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 238000002444 silanisation Methods 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- 230000005611 electricity Effects 0.000 description 5
- 239000002002 slurry Substances 0.000 description 5
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 229910004143 HfON Inorganic materials 0.000 description 3
- 229910004129 HfSiO Inorganic materials 0.000 description 3
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- BRGOCSWOKBOIOJ-UHFFFAOYSA-N N.[O-2].[Hf+4] Chemical compound N.[O-2].[Hf+4] BRGOCSWOKBOIOJ-UHFFFAOYSA-N 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 3
- 229910006501 ZrSiO Inorganic materials 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 150000001335 aliphatic alkanes Chemical class 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- XKMRRTOUMJRJIA-UHFFFAOYSA-N ammonia nh3 Chemical compound N.N XKMRRTOUMJRJIA-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 229910052735 hafnium Inorganic materials 0.000 description 3
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 3
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 3
- 230000008676 import Effects 0.000 description 3
- 229910000765 intermetallic Inorganic materials 0.000 description 3
- 238000003701 mechanical milling Methods 0.000 description 3
- 238000002156 mixing Methods 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- 238000005121 nitriding Methods 0.000 description 3
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 239000000376 reactant Substances 0.000 description 3
- 229910000077 silane Inorganic materials 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229910052726 zirconium Inorganic materials 0.000 description 3
- 230000000712 assembly Effects 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 229910052754 neon Inorganic materials 0.000 description 2
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 230000002879 macerating effect Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
Abstract
本发明揭示一种具有应变沟道的互补式金属氧化物半导体,主要是包括:一半导体基底、设置于上述半导体基底内的多个沟槽隔离区、氮化物衬垫层、一离子注入氮化物衬垫层、一N型沟道晶体管以及一P型沟道晶体管。其中,相邻两沟槽隔离区之间各定义出一有源区,有源区包括一N型有源区与一P型有源区。另外,氮化物衬垫层,保行性设置于上述N型有源区两侧的上述沟槽隔离区与上述半导体基底之间。再者,离子注入氮化物衬垫层,保行性设置于上述P型有源区两侧的沟槽隔离区与半导体基底之间。并且,N型沟道晶体管,设置于N型有源区上方。以及,P型沟道晶体管,设置于P型有源区上方。
Description
技术领域
本发明是有关于一种场效晶体管,且特别是有关于一种包括具有拉伸应变的N型沟道晶体管(NMOS)与具有压缩应力的P型沟道晶体管(PMOS)的互补式金氧半场效晶体管(CMOS)组件及其制作方法。
背景技术
随着栅极组件尺寸的缩小化,要使金氧半场效晶体管(MOSFET)组件能在低操作电压下,具有高趋动电流和高速的效能是相当困难的。因此,许多人在努力寻求改善金氧半场效晶体管组件的效能的方法。
利用应变引发的能带结构变型来增加载子的迁移率,以增加场效晶体管的趋动电流,可改善场效晶体管组件的效能,且此种方法已被应用于各种组件中。这些组件的硅沟道是处于双轴拉伸应变的情况。
已有研究指出利用硅沟道处于双轴拉伸应变的情况中来增加电子的迁移率(K.Ismail et al.,“Electron transport properties in Si/SiGeheterostructures:Measurements and device applications”,Appl.Phys.Lett.63,pp.660,1993.),及利用硅锗沟道处于双轴压缩应变的情况中来增加空穴的迁移率(D.K.Nayak et al.,“Enhancement-modequantum-well GeSi PMOS”,IEEE Elect.Dev.Lett.12,pp.154,1991.)。然而,结合具有双轴拉伸应变的硅沟道的NMOSFETs(N型金氧半场效晶体管)及具有双轴压缩应变的硅锗沟道的PMOSFETs(P型金氧半场效晶体管)的CMOS工艺技术是难以达成的。在晶体管的制造上有利用厚的缓冲层或复杂多层结构等许多应变层制造方法(K.Ismail et al.,IBM,Jul.1996,Complementary metal-oxide semiconductor transistorlogic using strained Si/SiGe heterostructure layers,U.S.PatentNo.5534713.),此些方法并不易于整合到传统的CMOS工艺中。
再者,更有研究提出以覆盖一层应力膜于整个晶体管上方的方式,以提供适当的应力予晶体管的沟道区(A.Shimizu et al.,“Localmechanical stress control(LMC):A new technique for CMOSperformance enhancement”,pp.433-436 of the Digest of TechnicalPapers of the 2001 International Electron Device Meeting.)
然而,于沟道区导入压缩应力有利于改善电动的迁移速率,却会对电子迁移率造成退化。因此,对N型沟道晶体管(NMOS)而言,需要导入拉伸应力以提升电子迁移率,而对P型沟道晶体管(PMOS)而言,需要导入压缩应力以提升空穴迁移率。但是在同一芯片上欲制作出同时具有拉伸应力沟道区的N型沟道晶体管(NMOS)与压缩应力沟道区的P型沟道晶体管(PMOS)的互补式金属氧化物半导体(CMOS),却有相当的困难。
有鉴于此,本发明提出一种可同时具拉伸应力沟道区与压缩应力沟道区的半导体基底及其制作方法,可适用于制作互补式金属氧化物半导体。
发明内容
本发明的目的在于一种具应变沟道的互补式金属氧化物半导体及其制作方法,使N型沟道晶体管的沟道区具有拉伸应力,而P型沟道晶体管的沟道区具有压缩应力,整合两者于同一芯片,以提升组件的操作速度。
本发明的主要特征之一是在于N型沟道晶体管两侧的浅沟槽隔离区内保行性形成一氮化物衬垫层,用以阻挡后续填充于浅沟槽隔离区的氧化物扩散,以避免隔离氧化物体积膨胀,并且氮化物衬垫层本身可提供N型晶体管的半导体基底沟道区形成一拉伸应力。另外,将P型沟道晶体管两侧的浅沟槽隔离区内的氮化物衬垫层施以离子注入,以造成氮化物衬垫层内的缺陷形成,有利于后续填充于浅沟槽隔离区的氧化物扩散,以于P型晶体管的半导体基底沟道区形成一压缩应力。
为获致上述的目的,本发明提出一种具应变沟道的互补式金属氧化物半导体,主要是包括:一半导体基底、设置于上述半导体基底内的多个沟槽隔离区、一氮化物衬垫层、一离子注入氮化物衬垫层、一N型沟道晶体管以及一P型沟道晶体管。其中,相邻两上述沟槽隔离区之间各定义出一有源区,上述有源区包括一N型有源区与一P型有源区。另外,上述氮化物衬垫层,保行性设置于上述N型有源区两侧的上述沟槽隔离区与上述半导体基底之间。再者,上述离子注入氮化物衬垫层,保行性设置于上述P型有源区两侧的上述沟槽隔离区与上述半导体基底之间。并且,上述N型沟道晶体管,设置于上述N型有源区上方。以及,上述P型沟道晶体管,设置于上述P型有源区上方。
如前所述,上述半导体基底包括:一硅基底、堆叠的一硅层与一硅锗层或堆叠的一第一硅基底、一埋入绝缘层与一第二硅基底。
如前所述,上述沟槽隔离区的厚度大体为2000-6000。
如前所述,上述沟槽隔离区是由一氧化物所构成。
如前所述,本发明的结构更包括:一氧化物衬垫层,保行性设置于上述氮化物衬垫层与上述半导体基底之间。
如前所述,本发明的结构更包括:一氧化物衬垫层,保行性设置于上述离子注入氮化物衬垫层与上述半导体基底之间。
如前所述,上述氮化物衬垫层是由氮化硅所构成,而上述离子注入氮化物衬垫层是由被施以离子注入的氮化硅所构成。
如前所述,上述离子注入氮化物衬垫层所被施加的离子包括:硅(Si)离子、氮(N)离子、氦(He)离子、氖(Ne)离子、氩(Ar)、氙(Xe)或锗离子。
根据本发明,上述N型有源区的上述半导体基底表层具有一拉伸应变沟道区。上述拉伸应变沟道区的拉伸应变量大体为0.1%-2%。
根据本发明,上述P型有源区的上述半导体基底表层具有一压缩应变沟道区。上述压缩应变沟道区的拉伸应变量大体为0.1%-2%。
根据前述的具应变沟道的互补式金属氧化物半导体,本发明又提出。一种具应变沟道的互补式金属氧化物半导体的制作方法,包括:
首先,供一半导体基底。接着,形成多个沟槽于上述基底内,使得相邻两上述沟槽之间各定义出一有源区,其中上述有源区包括一N型有源区与一P型有源区。接着,保行性形成一氮化物衬垫层,于各上述沟槽的侧壁与底部。接着,实施一离子注入于上述P型有源区两侧的上述氮化物衬垫层内。然后,形成多个沟槽隔离物,以填满各上述沟槽。接着,形成一N型沟道晶体管于上述N型有源区上方。最后,形成一P型沟道晶体管于上述P型有源区上方。
如前所述,形成上述N型沟道晶体管与上述P型沟道晶体管之后更包括:分别形成一应力膜,覆盖于上述N型沟道晶体管与上述P型沟道晶体管表面。上述应力膜是由化学气相沉积法(chemical vapordeposition;CVD)所形成。
本发明的主要特征之二是在于N型沟道晶体管两侧的浅沟槽隔离区内保行性形成氮化物衬垫层,用以阻挡后续填充于浅沟槽隔离区的氧化物扩散,以避免隔离氧化物体积膨胀,并且氮化物衬垫层本身可提供N型晶体管的半导体基底沟道区形成一拉伸应力。另外,P型沟道晶体管两侧的浅沟槽隔离区内并无氮化物衬垫层,后续填充于浅沟槽隔离区的氧化物会体积膨胀,导致于P型晶体管的半导体基底沟道区形成一压缩应力。
为获致上述的目的,本发明提出一种具应变沟道的互补式金属氧化物半导体,主要是包括:一半导体基底、多个沟槽隔离区、一氮化物衬垫层、一N型沟道晶体管、一P型沟道晶体管。其中,上述沟槽隔离区,设置于上述半导体基底内,使得相邻两上述沟槽隔离区之间各定义出一有源区,上述有源区包括一N型有源区与一P型有源区。并且,上述氮化物衬垫层,保行性设置于上述N型有源区两侧的上述沟槽隔离区与上述半导体基底之间,但未覆盖氮化物衬垫层于上述P型有源区两侧的上述沟槽隔离区与上述半导体基底之间。再者,上述N型沟道晶体管,设置于上述N型有源区上方。以及,上述P型沟道晶体管,设置于上述P型有源区上方。
如前所述,上述半导体基底包括:一硅基底、堆叠的一硅层与一硅锗层或堆叠的一第一硅基底、一埋入绝缘层与一第二硅基底。
如前所述,上述沟槽隔离区的厚度大体为2000-6000。
如前所述,上述沟槽隔离区是由一氧化物所构成。
如前所述,本发明的结构更包括:一氧化物衬垫层,保行性设置于上述氮化物衬垫层与上述半导体基底之间。
如前所述,上述氮化物衬垫层是由氮化硅所构成。
根据本发明,上述N型有源区的上述半导体基底表层具有一拉伸应变沟道区,上述拉伸应变沟道区的拉伸应变量大体为0.1%-2%。
根据本发明,上述P型有源区的上述半导体基底表层具有一压缩应变沟道区,上述拉伸应变沟道区的拉伸应变量大体为0.1%-2%。
根据前述的具应变沟道的互补式金属氧化物半导体,本发明更提出一种具应变沟道的互补式金属氧化物半导体的制作方法,包括:
首先,提供一半导体基底。接着,形成多个沟槽于上述基底内,使得相邻两上述沟槽之间各定义出一有源区,其中上述有源区包括一N型有源区与一P型有源区。接着,保行性形成一氮化物衬垫层,于上述N型有源区两侧的各上述沟槽的侧壁与底部,但未覆盖氮化物衬垫层于上述P型有源区两侧的各上述沟槽的侧壁与底部。接着,形成多个沟槽隔离物,以填满各上述沟槽。形成一N型沟道晶体管于上述N型有源区上方。最后,形成一P型沟道晶体管于上述P型有源区上方。
附图说明
图1A至图1H显示根据本发明的具应变沟道的互补式金属氧化物半导体的一较佳实施例的工艺剖面图;
图2A至图2H显示根据本发明的具应变沟道的互补式金属氧化物半导体的另一较佳实施例的工艺剖面图;
图3A至图3H显示根据本发明的具应变沟道的互补式金属氧化物半导体的又一较佳实施例的工艺剖面图。
符号说明:
100、200、300-半导体基底
102、202、302-图案化掩膜层
104a、104b、204a、204b、304a、304b-沟槽隔离区
106、206、306-氧化物衬垫层
108、208、308-氮化物衬垫层
108a-离子注入氮化物衬垫层
112、212、312-隔离氧化物
117、217、317-N型沟道晶体管
116、216、316-P型沟道晶体管
S100-离子注入程序
114、214、314-栅极介电层
115、215、315-栅极层
118、218、318-间隙壁
122、120、220、222、320、322-应力膜
210、311-掩膜层
S100-形成氮化物衬垫层程序
具体实施方式
实施例1:
以下请参照图1G,说明根据本发明的具应变沟道的互补式金属氧化物半导体的一较佳实施例。
其主要是包括:一半导体基底100、多个沟槽隔离区104a、104b、一氮化物衬垫层108、一离子注入氮化物衬垫层108a、一N型沟道晶体管117以及一P型沟道晶体管116。
其中,沟槽隔离区104a、104b设置于半导体基底100内,且相邻两沟槽隔离区104a、104b之间各定义出一有源区,而有源区包括一N型有源区(n-井)与一P型有源区(p-井)。沟槽隔离区104a、104b内填满隔离氧化物112。
另外,氮化物衬垫层108保行性设置于N型有源区(n-井)两侧的沟槽隔离区104b与半导体基底100之间。氮化物衬垫层108的设置为本发明的特征之一。氮化物衬垫层108可用以阻挡后续填充于浅沟槽隔离区的氧化物112扩散,进而避免隔离氧化物112体积膨胀,并且氮化物衬垫层本身具有拉伸应力(intrinsic tensile stress),导致对沟槽104b的侧壁施加一垂直压缩应力(vertical compressive stress)以及可提供N型晶体管117的半导体基底100沟道区形成一拉伸应力。
再者,离子注入氮化物衬垫层108a保行性设置于P型有源区(p-井)两侧的沟槽隔离区104a与半导体基底100之间。离子注入氮化物衬垫层108a内具有缺陷,有利于后续填充于浅沟槽隔离区的氧化物扩散,造成体积膨胀,以于P型晶体管116的半导体基底100沟道区形成一压缩应力。
并且,N型沟道晶体管117设置于N型有源区(n-井)上方。以及,P型沟道晶体管116,设置于P型有源区(p-井)上方。如此一来,N型沟道晶体管117下方的沟道区具有一拉伸应力,可提升电子迁移率。P型沟道晶体管116下方的沟道区具有一压缩应力,可提升空穴迁移率。
实施例2:
以下请配合参考图1A至图1H的工艺剖面图,说明根据本发明的实施例1的具应变沟道的互补式金属氧化物半导体的制作方法。
首先,请参照图1A,提供一半导体基底100,其包括:一硅基底、堆叠的一硅层与一硅锗层或是堆叠的一第一硅基底、一埋入绝缘层与一第二硅基底,即所谓的绝缘层上覆硅(silicon-on-insulator;SOI),甚至可以是包含砷化镓或磷化铟的化合物。
接着,请参照图1B,形成多个沟槽104a、104b于半导体基底100内。例如先形成一图案化掩膜层102于半导体基底100表面,然后利用适当蚀刻法,例如:非等向性电浆蚀刻法(anisotropi cplasma etching),该电浆可以为含氟化学物质,较佳为CF4,透过图案化掩膜层102以形成多个沟槽104a、104b,使得相邻两沟槽104a、104b之间各定义出一有源区。本发明是强调应用于CMOS组件,所以图式中有源区包括一N型有源区(n-井)与一P型有源区(p-井)。N型有源区(n-井)与P型有源区(p-井)是分别以掺杂不同导电型态的掺杂物于半导体基底100内所形成。沟槽隔离区104a、104b的厚度大体为2000-6000。图案化掩膜层102的材质可包括:氧化硅、氮化硅或是堆叠的氧化硅与氮化硅,其中以堆叠的氧化硅与氮化硅为较佳。
接着,请参照图1C,先例如以热氧化法(thermal oxidation)于温度约600-1000℃下通入水气与氧气,或是直接以化学气相沉积法(CVD),保行性形成一氧化物衬垫层106于沟槽104a、104b的侧壁与底部表面。接着,在例如以适当的化学气相沉积法(chemical vapor deposition;CVD)保行性形成一氮化物衬垫层108于氧化物衬垫层106表面,使得氧化物衬垫层106在沟槽104a、104b内夹设于氮化物衬垫层108与半导体基底100之间。氧化物衬垫层106不仅可以增加氮化物衬垫层108的附着力,更可以缓冲以化学气相沉积(CVD)形成氮化物衬垫层108时对半导体基底100所造成的损伤。其中,形成氮化物衬垫层108的反应性气体可包括氨(ammonia)与烷类(silane)。
接着,请再参照图1D,形成一离子注入掩膜110于整个N型有源区(n-井)上方,其材质例如为光阻(photoresist)。然后,以离子注入掩膜110为遮蔽,实施一离子注入程序S100于P型有源区(p-井)两侧的氮化物衬垫层108内,也就是沟槽104b中的氮化物衬垫层108内。离子注入程序S100可以为传统的束线离子注入程序(beam-line ion implantationprocess),也可以是电浆入浸离子注入(plasma immersion ionimplantation;PIII),或是任何其它习知的离子注入程序,离子注入S100可包括:硅(Si)离子、氮(N)离子、氦(He)离子、氖(Ne)离子、氩(Ar)、氙(Xe)或锗离子,其剂量约为每平方公分下1E13-1E16个离子量,施加能量约为10eV-100keV。氮化物衬垫层108被施加离子注入之后会增加其内部的缺陷,使得不仅其本身的应力会降低,更可使后续填充于沟槽的隔离物容易扩散,进而造成体积膨胀,以至于对P型有源区(p-井)的半导体基底100表层(即沟道区)形成一压缩应力。
接着,请再参照图1E,先以适当腐蚀溶液将离子注入掩膜110移除,再形成隔离物112以填满沟槽104a、104b。隔离物112的材质可以包括氧化物,例如氧化硅,或是由氧化硅与多晶硅的组合所构成。然后再以化学机械研磨法(chemical mechanical polishing;CMP)使隔离物112表面平坦化,以完成浅沟槽隔离区(shallow trench isolation;STI)的制作。
接着,请参照图1F,再以适当腐蚀溶液移除图案化掩膜层102,当图案化掩膜层102的材质包括氧化硅与氮化硅时,较佳实施例为先以热磷酸溶液去除氮化硅,再以稀释氢氟酸去除氧化硅。
接着,请参照图1G,分别形成一N型沟道晶体管117于N型有源区(n-井)上方以及形成一P型沟道晶体管116于P型有源区(p-井)上方。先于N型有源区(n-井)与P型有源区(p-井)的半导体基底100表面形成栅极介电层114,栅极介电层114例如为氧化硅层,其形成方法例如是利用化学气相沉积法(CVD)、热氧化法(thermal oxidation)、氮化法(nitridation)、溅镀法(sputtering)或是任何习知形成栅极介电层的方法,其材质可包括氧化硅、氮化硅、氮氧化硅,其厚度约为3-100,或是其它高介电常数(high permittivity;high-k)材质,包括:氧化铝(Al2O3)、氧化铪(HfO2)、氮氧化铪(HfON)、硅烷化铪(HfSiO4)、硅烷化锆(ZrSiO4)、氧化镧(La2O3)等,其等效氧化物厚度(equivalent oxidethickness;EOT)约为3-100,其中栅极介电层114的材质以氮氧化硅为较佳。然后,再于栅极介电层114表面形成一栅极层115,栅极层115知材质包括:多晶硅、多晶硅锗、金属化合物包含:钼(Mo)、钨(W)或氮化钛(TiN),抑或者是其它导电材质,以多晶硅为较佳。栅极介电层114与栅极层115共同构成一栅极结构116、117。然后再利用一掩膜采用选择性蚀刻,图案化栅极介电层114与栅极层115,以定义出栅极结构116、117的图案。并分别于栅极结构116、117两侧的N型有源区(n-井)与P型有源区(p-井)进行n型和p型离子掺杂,以及于栅极结构116、117的侧壁形成间隙壁118,间隙壁118的材质例如为氮化硅或氧化硅。然后再例如利用离子注入法于间隙壁118外侧的半导体基底100内形成漏极/源极。这些晶体管的制成可以根据任何习知半导体晶体管制造技术加以被制,在此并不加限制与赘述。
如此,在半导体基底100上,便形成N型沟道晶体管117于具有拉伸应力的沟道区上方,拉伸应变沟道区的拉伸应变量大体为0.1%-2%,且形成P型沟道晶体管116于具有压缩应力的沟道区上方,压缩应变沟道区的拉伸应变量大体为0.1%-2%。如此一来,N型沟道晶体管117下方的沟道区具有一拉伸应力,可提升电子迁移率。P型沟道晶体管116下方的沟道区具有一压缩应力,可提升空穴迁移率。
请参照图1H,N型沟道晶体管117与P型沟道晶体管116表面更可以分别以化学气相沉积法(chemical vapor deposition;CVD)覆盖一应力膜122、120,加以提供适当的应力。
实施例3:
以下请参照图2G,说明根据本发明的具应变沟道的互补式金属氧化物半导体的一较佳实施例。
其主要是包括:一半导体基底200、多个沟槽隔离区204a、204b、一氮化物衬垫层208、一N型沟道晶体管217以及一P型沟道晶体管216。
其中,沟槽隔离区204a、204b设置于半导体基底200内,且相邻两沟槽隔离区204a、204b之间各定义出一有源区,而有源区包括一N型有源区(n-井)与一P型有源区(p-井)。沟槽隔离区204a、204b内填满隔离氧化物212。
另外,氮化物衬垫层208保行性设置于N型有源区(n-井)两侧的沟槽隔离区204b与半导体基底200之间。氮化物衬垫层208的设置为本发明的特征之一。氮化物衬垫层208可用以阻挡后续填充于浅沟槽隔离区的氧化物212扩散,进而避免隔离氧化物212体积膨胀,并且氮化物衬垫层208本身具有拉伸应力(intrinsic tensile stress),导致对沟槽204b的侧壁施加一垂直压缩应力(vertical compressive stress)以及可提供N型晶体管217的半导体基底200沟道区形成一拉伸应力。
然而,沟槽204a内并无氮化物衬垫层,后续填充于浅沟槽隔离区的氧化物会发生扩散,造成体积膨胀,以于P型晶体管216的半导体基底200沟道区形成一压缩应力。
并且,N型沟道晶体管217设置于N型有源区(n-井)上方。以及,P型沟道晶体管216,设置于P型有源区(p-井)上方。如此一来,N型沟道晶体管217下方的沟道区具有一拉伸应力,可提升电子迁移率。P型沟道晶体管216下方的沟道区具有一压缩应力,可提升空穴迁移率。
实施例4:
以下请配合参考图2A至图2H的工艺剖面图,说明根据本发明的实施例3的具应变沟道的互补式金属氧化物半导体的制作方法之一。
首先,请参照图2A,提供一半导体基底200,其包括:一硅基底、堆叠的一硅层与一硅锗层或是堆叠的一第一硅基底、一埋入绝缘层与一第二硅基底,即所谓的绝缘层上覆硅(silicon-on-insulator;SOI),甚至可以是包含砷化镓或磷化铟的化合物。
接着,请参照图2B,形成多个沟槽204a、204b于半导体基底200内。例如先形成一图案化掩膜层202于半导体基底200表面,然后利用适当蚀刻法,例如:非等向性电浆蚀刻法(anisotropic plasma etching),该电浆可以为含氟化学物质,较佳为CF4,透过图案化掩膜层202以形成多个沟槽204a、204b,使得相邻两沟槽204a、204b之间各定义出一有源区。本发明是强调应用于CMOS组件,所以图式中有源区包括一N型有源区(n-井)与一P型有源区(p-井)。N型有源区(n-井)与P型有源区(p-井)是分别以掺杂不同导电型态的掺杂物于半导体基底200内所形成。沟槽隔离区204a、204b的厚度大体为2000-6000。图案化掩膜层202的材质可包括:氧化硅、氮化硅或是堆叠的氧化硅与氮化硅,其中以堆叠的氧化硅与氮化硅为较佳。
接着,请参照图2C,先例如以热氧化法(thermal oxidation)于温度约600-1000℃下通入水气与氧气,或是直接以化学气相沉积法(CVD),保行性形成一氧化物衬垫层206于沟槽204a、204b的侧壁与底部表面。接着,在例如以适当的化学气相沉积法(chemical vapor deposition;CVD)保行性形成一氮化物衬垫层208于氧化物衬垫层206表面,使得氧化物衬垫层206在沟槽204a、204b内夹设于氮化物衬垫层208与半导体基底200之间。氧化物衬垫层206不仅可以增加氮化物衬垫层208的附着力,更可以缓冲以化学气相沉积(CVD)形成氮化物衬垫层208时对半导体基底200所造成的损伤。其中,形成氮化物衬垫层208的反应性气体可包括氨(ammonia)与烷类(silane)。
接着,请再参照图2D,形成一材质例如为光阻的掩膜层210于整个N型有源区(n-井),然后以适当溶液,例如:热磷酸溶液,去除位于P型有源区(p-井)两侧沟槽204a内的氮化物衬垫层208。
接着,请再参照图2E,先以适当腐蚀溶液将掩膜层210移除,再形成隔离物212以填满沟槽204a、204b。隔离物212的材质可以包括氧化物,例如氧化硅,或是由氧化硅与多晶硅的组合所构成。然后再以化学机械研磨法(chemical mechanical polishing;CMP)使隔离物212表面平坦化,以完成浅沟槽隔离区(shallow trench isolation;STI)的制作。
接着,请参照图2F,再以适当腐蚀溶液移除图案化掩膜层202,当图案化掩膜层202的材质包括氧化硅与氮化硅时,较佳实施例为先以热磷酸溶液去除氮化硅,再以稀释氢氟酸去除氧化硅。
接着,请参照图2G,分别形成一N型沟道晶体管217于N型有源区(n-井)上方以及形成一P型沟道晶体管216于P型有源区(p-井)上方。先于N型有源区(n-井)与P型有源区(p-井)的半导体基底200表面形成栅极介电层214,栅极介电层214例如为氧化硅层,其形成方法例如是利用化学气相沉积法(CVD)、热氧化法(thermal oxidation)、氮化法(nitridation)、溅镀法(sputtering)或是任何习知形成栅极介电层的方法,其材质可包括氧化硅、氮化硅、氮氧化硅,其厚度约为3-100,或是其它高介电常数(high permittivity;high-k)材质,包括:氧化铝(Al2O3)、氧化铪(HfO2)、氮氧化铪(HfON)、硅烷化铪(HfSiO4)、硅烷化锆(ZrSiO4)、氧化镧(La2O3)等,其等效氧化物厚度(equivalent oxidethickness;EOT)约为3-100,其中栅极介电层214的材质以氮氧化硅为较佳。然后,再于栅极介电层214表面形成一栅极层215,栅极层215知材质包括:多晶硅、多晶硅锗、金属化合物包含:钼(Mo)、钨(W)或氮化钛(TiN),抑或者是其它导电材质,以多晶硅为较佳。栅极介电层214与栅极层215共同构成一栅极结构216、217。然后再利用一掩膜采用选择性蚀刻,图案化栅极介电层214与栅极层215,以定义出栅极结构216、217的图案。并分别于栅极结构216、217两侧的N型有源区(n-井)与P型有源区(p-井)进行n型和p型离子掺杂,以及于栅极结构216、217的侧壁形成间隙壁218,间隙壁218的材质例如为氮化硅或氧化硅。然后再例如利用离子注入法于间隙壁218外侧的半导体基底200内形成漏极/源极。这些晶体管的制成可以根据任何习知半导体晶体管制造技术加以被制,在此并不加限制与赘述。
如此,在半导体基底200上,便形成N型沟道晶体管217于具有拉伸应力的沟道区上方,拉伸应变沟道区的拉伸应变量大体为0.1%-2%,且形成P型沟道晶体管216于具有压缩应力的沟道区上方,压缩应变沟道区的拉伸应变量大体为0.1%-2%。如此一来,N型沟道晶体管217下方的沟道区具有一拉伸应力,可提升电子迁移率。P型沟道晶体管216下方的沟道区具有一压缩应力,可提升空穴迁移率。
请参照图2H,N型沟道晶体管217与P型沟道晶体管216表面更可以分别以化学气相沉积法(chemical vapor deposition;CVD)覆盖一应力膜222、220,加以提供适当的应力。
实施例5:
以下请配合参考图3A至图3H的工艺剖面图,说明根据本发明的实施例3的具应变沟道的互补式金属氧化物半导体的制作方法之二。
首先,请参照图3A,提供一半导体基底300,其包括:一硅基底、堆叠的一硅层与一硅锗层或是堆叠的一第一硅基底、一埋入绝缘层与一第二硅基底,即所谓的绝缘层上覆硅(silicon-on-insulator;SOI),甚至可以是包含砷化镓或磷化铟的化合物。
接着,请参照图3B,形成多个沟槽304a、304b于半导体基底300内。例如先形成一图案化掩膜层302于半导体基底300表面,然后利用适当蚀刻法,例如:非等向性电浆蚀刻法(anisotropic plasma etching),该电浆可以为含氟化学物质,较佳为CF4,透过图案化掩膜层302以形成多个沟槽304a、304b,使得相邻两沟槽304a、304b之间各定义出一有源区。本发明是强调应用于CMOS组件,所以图式中有源区包括一N型有源区(n-井)与一P型有源区(p-井)。N型有源区(n-井)与P型有源区(p-井)是分别以掺杂不同导电型态的掺杂物于半导体基底300内所形成。沟槽隔离区304a、304b的厚度大体为2000-6000。图案化掩膜层302的材质可包括:氧化硅、氮化硅或是堆叠的氧化硅与氮化硅,其中以堆叠的氧化硅与氮化硅为较佳。
接着,请参照图3C,先例如以热氧化法(thermal oxidation)于温度约600-1000℃下通入水气与氧气,或是直接以化学气相沉积法(CVD),保行性形成一氧化物衬垫层306于沟槽304a、304b的侧壁与底部表面。
接着,请再参照图3D,进行形成氮化物衬垫层308步骤S300。此步骤是本发明的实施例3的结构的制作方法中与前述实施例4主要差异的步骤。先形成一掩膜311于整个P型有源区(p-井)上方,例如以适当的化学气相沉积法(chemical vapor deposition;CVD)、含氮离子注入法或是在含氮气氛下进行退火,抑或是施以含氮电浆处理,保行性形成一氮化物衬垫层308于N型有源区(n-井)的两侧沟槽304b的氧化物衬垫层306表面,使得氧化物衬垫层306在沟槽304a内夹设于氮化物衬垫层308与半导体基底300之间。氧化物衬垫层306不仅可以增加氮化物衬垫层308的附着力,更可以缓冲以化学气相沉积(CVD)形成氮化物衬垫层308时对半导体基底300所造成的损伤。其中,形成氮化物衬垫层308的反应性气体可包括氨(ammonia)与烷类(silane)。
接着,请再参照图3E,先以适当腐蚀溶液将掩膜层311移除,再形成隔离物312以填满沟槽304a、304b。隔离物312的材质可以包括氧化物,例如氧化硅,或是由氧化硅与多晶硅的组合所构成。然后再以化学机械研磨法(chemical mechanical polishing;CMP)使隔离物312表面平坦化,以完成浅沟槽隔离区(shallow trench isolation;STI)的制作。
接着,请参照图3F,再以适当腐蚀溶液移除图案化掩膜层302,当图案化掩膜层302的材质包括氧化硅与氮化硅时,较佳实施例为先以热磷酸溶液去除氮化硅,再以稀释氢氟酸去除氧化硅。
接着,请参照图3G,分别形成一N型沟道晶体管317于N型有源区(n-井)上方以及形成一P型沟道晶体管216于P型有源区(p-井)上方。先于N型有源区(n-井)与P型有源区(p-井)的半导体基底300表面形成栅极介电层314,栅极介电层314例如为氧化硅层,其形成方法例如是利用化学气相沉积法(CVD)、热氧化法(thermal oxidation)、氮化法(nitridation)、溅镀法(sputtering)或是任何习知形成栅极介电层的方法,其材质可包括氧化硅、氮化硅、氮氧化硅,其厚度约为3-100,或是其它高介电常数(high permittivity;high-k)材质,包括:氧化铝(Al2O3)、氧化铪(HfO2)、氮氧化铪(HfON)、硅烷化铪(HfSiO4)、硅烷化锆(ZrSiO4)、氧化镧(La2O3)等,其等效氧化物厚度(equivalent oxidethickness;EOT)约为3-100,其中栅极介电层314的材质以氮氧化硅为较佳。然后,再于栅极介电层314表面形成一栅极层315,栅极层315知材质包括:多晶硅、多晶硅锗、金属化合物包含:钼(Mo)、钨(W)或氮化钛(TiN),抑或者是其它导电材质,以多晶硅为较佳。栅极介电层314与栅极层315共同构成一栅极结构316、317。然后再利用一掩膜采用选择性蚀刻,图案化栅极介电层314与栅极层315,以定义出栅极结构316、317的图案。并分别于栅极结构316、317两侧的N型有源区(n-井)与P型有源区(p-井)进行n型和p型离子掺杂,以及于栅极结构316、317的侧壁形成间隙壁318,间隙壁318的材质例如为氮化硅或氧化硅。然后再例如利用离子注入法于间隙壁318外侧的半导体基底300内形成漏极/源极。这些晶体管的制成可以根据任何习知半导体晶体管制造技术加以被制,在此并不加限制与赘述。
如此,在半导体基底300上,便形成N型沟道晶体管317于具有拉伸应力的沟道区上方,拉伸应变沟道区的拉伸应变量大体为0.1%-2%,且形成P型沟道晶体管316于具有压缩应力的沟道区上方,压缩应变沟道区的拉伸应变量大体为0.1%-2%。如此一来,N型沟道晶体管317下方的沟道区具有一拉伸应力,可提升电子迁移率。P型沟道晶体管316下方的沟道区具有一压缩应力,可提升空穴迁移率。
请参照图3H,N型沟道晶体管317与P型沟道晶体管316表面更可以分别以化学气相沉积法(chemical vapor deposition;CVD)覆盖一应力膜322、320,加以提供适当的应力。
发明优点:
1.根据本发明的N型沟道晶体管具有拉伸应力而P型沟道晶体管具有压缩应力,因此可同时提升N型沟道的电子迁移率以及P型沟道的空穴迁移率,有效提升组件操作速度。
2.根据本发明的互补式金氧半晶体管(CMOS),以简单的制成方式整合N型沟道晶体管与P型沟道晶体管于同一芯片,分别有适当可提升操作速度的应力。
Claims (48)
1.一种具有应变沟道的互补式金属氧化物半导体,其特征在于,所述互补式金属氧化物半导体包括:
一半导体基底;
多个沟槽隔离区,设置于上述半导体基底内,使得相邻两上述沟槽隔离区之间各定义出一有源区,其中上述有源区包括一N型有源区与一P型有源区;
氮化物衬垫层,保行性设置于上述N型有源区两侧的上述沟槽隔离区与上述半导体基底之间;
一离子注入氮化物衬垫层,保行性设置于上述P型有源区两侧的上述沟槽隔离区与上述半导体基底之间;
一N型沟道晶体管,设置于上述N型有源区上方;以及
一P型沟道晶体管,设置于上述P型有源区上方。
2.根据权利要求1所述的具有应变沟道的互补式金属氧化物半导体,其特征在于:上述沟槽隔离区是由氧化物所构成。
3.根据权利要求1所述的具有应变沟道的互补式金属氧化物半导体,其特征在于更包括:氧化物衬垫层,保行性设置于上述氮化物衬垫层与上述半导体基底之间。
4.根据权利要求1所述的具有应变沟道的互补式金属氧化物半导体,其特征在于更包括:氧化物衬垫层,保行性设置于上述离子注入氮化物衬垫层与上述半导体基底之间。
5.根据权利要求1所述的具有应变沟道的互补式金属氧化物半导体,其特征在于:上述氮化物衬垫层是由氮化硅所构成。
6.根据权利要求1所述的具有应变沟道的互补式金属氧化物半导体,其特征在于:上述离子注入氮化物衬垫层是由被施以离子注入的氮化硅所构成。
7.根据权利要求1所述的具有应变沟道的互补式金属氧化物半导体,其特征在于上述离子注入氮化物衬垫层所被施加的离子包括:硅离子、氮离子、氦离子、氖离子、氩、氙或锗离子。
8.根据权利要求1所述的具有应变沟道的互补式金属氧化物半导体,其特征在于:上述N型有源区的上述半导体基底表层具有一拉伸应变沟道区。
9.根据权利要求8所述的具有应变沟道的互补式金属氧化物半导体,其特征在于:上述拉伸应变沟道区的拉伸应变量为0.1%-2%。
10.根据权利要求1所述的具有应变沟道的互补式金属氧化物半导体,其特征在于:上述P型有源区的上述半导体基底表层具有一压缩应变沟道区。
11.根据权利要求10所述的具有应变沟道的互补式金属氧化物半导体,其特征在于:上述压缩应变沟道区的拉伸应变量为0.1%-2%。
12.根据权利要求1所述的具有应变沟道的互补式金属氧化物半导体,其特征在于上述半导体基底包括:一硅基底、堆叠的一硅层与一硅锗层或堆叠的一第一硅基底、一埋入绝缘层与一第二硅基底。
13.根据权利要求1所述的具有应变沟道的互补式金属氧化物半导体,其特征在于:上述沟槽隔离区的厚度为2000-6000。
14.一种具有应变沟道的互补式金属氧化物半导体,其特征在于,所述互补式金属氧化物半导体包括:
一半导体基底;
多个沟槽隔离区,设置于上述半导体基底内,使得相邻两上述沟槽隔离区之间各定义出一有源区,其中上述有源区包括一N型有源区与一未覆盖氮化物衬垫层于两侧的P型有源区;
氮化物衬垫层,保行性设置于上述N型有源区两侧的上述沟槽隔离区与上述半导体基底之间;
一N型沟道晶体管,设置于上述N型有源区上方;以及
一P型沟道晶体管,设置于上述P型有源区上方。
15.根据权利要求14所述的具有应变沟道的互补式金属氧化物半导体,其特征在于:上述沟槽隔离区是由氧化物所构成。
16.根据权利要求14项所述的具有应变沟道的互补式金属氧化物半导体,其特征在于更包括:氧化物衬垫层,保行性设置于上述氮化物衬垫层与上述半导体基底之间。
17.根据权利要求14所述的具有应变沟道的互补式金属氧化物半导体,其特征在于:上述氮化物衬垫层是由氮化硅所构成。
18.根据权利要求14所述的具有应变沟道的互补式金属氧化物半导体,其特征在于:上述N型有源区的上述半导体基底表层具有一拉伸应变沟道区。
19.根据权利要求18所述的具有应变沟道的互补式金属氧化物半导体,其特征在于:上述拉伸应变沟道区的拉伸应变量为0.1%-2%。
20.根据权利要求14所述的具有应变沟道的互补式金属氧化物半导体,其特征在于:上述P型有源区的上述半导体基底表层具有一压缩应变沟道区。
21.根据权利要求20所述的具有应变沟道的互补式金属氧化物半导体,其特征在于:上述压缩应变沟道区的拉伸应变量为0.1%-2%。
22.根据权利要求14所述的具有应变沟道的互补式金属氧化物半导体,其中上述半导体基底包括:一硅基底、堆叠的一硅层与一硅锗层或堆叠的一第一硅基底、一埋入绝缘层与一第二硅基底。
23.根据权利要求14所述的具有应变沟道的互补式金属氧化物半导体,其特征在于:上述沟槽隔离区的厚度为2000-6000。
24.一种具有应变沟道的互补式金属氧化物半导体的制作方法,包括:
提供一半导体基底;
形成多个沟槽于上述基底内,使得相邻两上述沟槽之间各定义出一有源区,其中上述有源区包括一N型有源区与一未覆盖氮化物衬垫层于两侧的P型有源区;
保行性形成氮化物衬垫层,于各上述沟槽的侧壁与底部;
实施一离子注入于上述P型有源区两侧的上述氮化物衬垫层内;
形成多个沟槽隔离物,以填满各上述沟槽;
形成一N型沟道晶体管于上述N型有源区上方;以及
形成一P型沟道晶体管于上述P型有源区上方。
25.根据权利要求24所述的具有应变沟道的互补式金属氧化物半导体的制作方法,其中上述沟槽隔离物是由氧化物所构成。
26.根据权利要求24所述的具有应变沟道的互补式金属氧化物半导体的制作方法,其中形成上述氮化物衬垫层之前更包括:保行性形成氧化物衬垫层于各上述氮化物衬垫层与上述半导体基底之间。
27.根据权利要求24所述的具有应变沟道的互补式金属氧化物半导体的制作方法,其中上述氮化物衬垫层是由氮化硅所构成。
28.根据权利要求24所述的具有应变沟道的互补式金属氧化物半导体的制作方法,其中上述离子注入所施加的离子包括:硅离子、氮离子、氦离子、氖离子、氩、氙或锗离子。
29.根据权利要求24所述的具有应变沟道的互补式金属氧化物半导体的制作方法,其中上述N型有源区的上述半导体基底表层具有一拉伸应变沟道区。
30.根据权利要求29所述的具有应变沟道的互补式金属氧化物半导体的制作方法,其中上述拉伸应变沟道区的拉伸应变量为0.1%-2%。
31.根据权利要求24所述的具有应变沟道的互补式金属氧化物半导体的制作方法,其中上述P型有源区的上述半导体基底表层具有一压缩应变沟道区。
32.根据权利要求31所述的具有应变沟道的互补式金属氧化物半导体的制作方法,其中上述压缩应变沟道区的拉伸应变量为0.1%-2%。
33.根据权利要求24所述的具有应变沟道的互补式金属氧化物半导体的制作方法,其中上述半导体基底包括:一硅基底、堆叠的一硅层与一硅锗层或堆叠的一第一硅基底、一埋入绝缘层与一第二硅基底。
34.根据权利要求24所述的具有应变沟道的互补式金属氧化物半导体的制作方法,其中上述沟槽的厚度为2000-6000。
35.根据权利要求24所述的具有应变沟道的互补式金属氧化物半导体的制作方法,其中形成上述N型沟道晶体管与上述P型沟道晶体管之后更包括:分别形成一应力膜,覆盖于上述N型沟道晶体管与上述P型沟道晶体管表面。
36.根据权利要求24所述的具有应变沟道的互补式金属氧化物半导体的制作方法,其中上述应力膜是由化学气相沉积法所形成。
37.一种具有应变沟道的互补式金属氧化物半导体的制作方法,包括:
提供一半导体基底;
形成多个沟槽于上述基底内,使得相邻两上述沟槽之间各定义出一有源区,其中上述有源区包括一N型有源区与一P型有源区;
保行性形成氮化物衬垫层,于上述N型有源区两侧的各上述沟槽的侧壁与底部,但未覆盖氮化物衬垫层于上述P型有源区两侧的各上述沟槽的侧壁与底部;
形成多个沟槽隔离物,以填满各上述沟槽;
形成一N型沟道晶体管于上述N型有源区上方;以及
形成一P型沟道晶体管于上述P型有源区上方。
38.根据权利要求37所述的具有应变沟道的互补式金属氧化物半导体的制作方法,其中上述沟槽隔离物是由氧化物所构成。
39.根据权利要求37所述的具有应变沟道的互补式金属氧化物半导体的制作方法,其中形成上述氮化物衬垫层之前更包括:保行性形成氧化物衬垫层于各上述氮化物衬垫层与上述半导体基底之间。
40.根据权利要求37所述的具有应变沟道的互补式金属氧化物半导体的制作方法,其中上述氮化物衬垫层是由氮化硅所构成。
41.根据权利要求37所述的具有应变沟道的互补式金属氧化物半导体的制作方法,其中上述N型有源区的上述半导体基底表层具有一拉伸应变沟道区。
42.根据权利要求41所述的具有应变沟道的互补式金属氧化物半导体的制作方法,其中上述拉伸应变沟道区的拉伸应变量为0.1%-2%。
43.根据权利要求37所述的具有应变沟道的互补式金属氧化物半导体的制作方法,其中上述P型有源区的上述半导体基底表层具有一压缩应变沟道区。
44.根据权利要求43所述的具有应变沟道的互补式金属氧化物半导体的制作方法,其中上述压缩应变沟道区的拉伸应变量为0.1%-2%。
45.根据权利要求37所述的具有应变沟道的互补式金属氧化物半导体的制作方法,其中上述半导体基底包括:一硅基底、堆叠的一硅层与一硅锗层或堆叠的一第一硅基底、一埋入绝缘层与一第二硅基底。
46.根据权利要求37所述的具有应变沟道的互补式金属氧化物半导体的制作方法,其中上述沟槽的厚度为2000-6000。
47.根据权利要求37所述的具有应变沟道的互补式金属氧化物半导体的制作方法,其中形成上述N型沟道晶体管与上述P型沟道晶体管之后更包括:分别形成一应力膜,覆盖于上述N型沟道晶体管与上述P型沟道晶体管表面。
48.根据权利要求37所述的具有应变沟道的互补式金属氧化物半导体的制作方法,其中上述应力膜是由化学气相沉积法所形成。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/423,513 US6882025B2 (en) | 2003-04-25 | 2003-04-25 | Strained-channel transistor and methods of manufacture |
US10/423,513 | 2003-04-25 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1540757A CN1540757A (zh) | 2004-10-27 |
CN1293637C true CN1293637C (zh) | 2007-01-03 |
Family
ID=33299140
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2003101019562A Expired - Fee Related CN1293637C (zh) | 2003-04-25 | 2003-10-17 | 具有应变沟道的互补式金属氧化物半导体及其制作方法 |
CNU2004200483776U Expired - Lifetime CN2751444Y (zh) | 2003-04-25 | 2004-04-23 | 具应变通道的互补式金氧半导体 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNU2004200483776U Expired - Lifetime CN2751444Y (zh) | 2003-04-25 | 2004-04-23 | 具应变通道的互补式金氧半导体 |
Country Status (4)
Country | Link |
---|---|
US (2) | US6882025B2 (zh) |
CN (2) | CN1293637C (zh) |
SG (1) | SG115690A1 (zh) |
TW (1) | TWI222715B (zh) |
Families Citing this family (145)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6657276B1 (en) * | 2001-12-10 | 2003-12-02 | Advanced Micro Devices, Inc. | Shallow trench isolation (STI) region with high-K liner and method of formation |
US20050285140A1 (en) * | 2004-06-23 | 2005-12-29 | Chih-Hsin Ko | Isolation structure for strained channel transistors |
US7081395B2 (en) * | 2003-05-23 | 2006-07-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Silicon strain engineering accomplished via use of specific shallow trench isolation fill materials |
US6887798B2 (en) * | 2003-05-30 | 2005-05-03 | International Business Machines Corporation | STI stress modification by nitrogen plasma treatment for improving performance in small width devices |
US6905941B2 (en) * | 2003-06-02 | 2005-06-14 | International Business Machines Corporation | Structure and method to fabricate ultra-thin Si channel devices |
KR100517559B1 (ko) * | 2003-06-27 | 2005-09-28 | 삼성전자주식회사 | 핀 전계효과 트랜지스터 및 그의 핀 형성방법 |
US7714384B2 (en) * | 2003-09-15 | 2010-05-11 | Seliskar John J | Castellated gate MOSFET device capable of fully-depleted operation |
US8008724B2 (en) * | 2003-10-30 | 2011-08-30 | International Business Machines Corporation | Structure and method to enhance both nFET and pFET performance using different kinds of stressed layers |
JP4046069B2 (ja) * | 2003-11-17 | 2008-02-13 | ソニー株式会社 | 固体撮像素子及び固体撮像素子の製造方法 |
US7247534B2 (en) | 2003-11-19 | 2007-07-24 | International Business Machines Corporation | Silicon device on Si:C-OI and SGOI and method of manufacture |
CN100433275C (zh) * | 2003-12-08 | 2008-11-12 | 国际商业机器公司 | 降低pFETS中的硼扩散性 |
JP4441488B2 (ja) * | 2003-12-25 | 2010-03-31 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置および半導体集積回路装置 |
US7101765B2 (en) * | 2004-03-31 | 2006-09-05 | Intel Corporation | Enhancing strained device performance by use of multi narrow section layout |
US7285829B2 (en) * | 2004-03-31 | 2007-10-23 | Intel Corporation | Semiconductor device having a laterally modulated gate workfunction and method of fabrication |
DE102004020834B4 (de) * | 2004-04-28 | 2010-07-15 | Qimonda Ag | Herstellungsverfahren für eine Halbleiterstruktur |
US7528051B2 (en) * | 2004-05-14 | 2009-05-05 | Applied Materials, Inc. | Method of inducing stresses in the channel region of a transistor |
DE102005005327A1 (de) * | 2004-05-17 | 2005-12-15 | Infineon Technologies Ag | Feldefekttansistor, Transistoranordnung sowie Verfahren zur Herstellung eines halbleitenden einkristallinen Substrats und einer Transistoranordnung |
US20050266632A1 (en) * | 2004-05-26 | 2005-12-01 | Yun-Hsiu Chen | Integrated circuit with strained and non-strained transistors, and method of forming thereof |
GB0411971D0 (en) * | 2004-05-28 | 2004-06-30 | Koninkl Philips Electronics Nv | Semiconductor device and method for manufacture |
JP4102334B2 (ja) * | 2004-06-16 | 2008-06-18 | 株式会社東芝 | 半導体装置及びその製造方法 |
US7160782B2 (en) * | 2004-06-17 | 2007-01-09 | Texas Instruments Incorporated | Method of manufacture for a trench isolation structure having an implanted buffer layer |
JP4813778B2 (ja) * | 2004-06-30 | 2011-11-09 | 富士通セミコンダクター株式会社 | 半導体装置 |
US7186622B2 (en) * | 2004-07-15 | 2007-03-06 | Infineon Technologies Ag | Formation of active area using semiconductor growth process without STI integration |
JP2006049413A (ja) * | 2004-08-02 | 2006-02-16 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US8158488B2 (en) | 2004-08-31 | 2012-04-17 | Micron Technology, Inc. | Method of increasing deposition rate of silicon dioxide on a catalyst |
JP4888118B2 (ja) * | 2004-09-16 | 2012-02-29 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法及び半導体装置 |
WO2006049834A1 (en) * | 2004-10-29 | 2006-05-11 | Advanced Micro Devices, Inc. | A semiconductor device including semiconductor regions having differently strained channel regions and a method of manufacturing the same |
DE102004053307B4 (de) * | 2004-11-04 | 2010-01-07 | Siltronic Ag | Mehrschichtenstruktur umfassend ein Substrat und eine darauf heteroepitaktisch abgeschiedene Schicht aus Silicium und Germanium und ein Verfahren zu deren Herstellung |
US7190036B2 (en) * | 2004-12-03 | 2007-03-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transistor mobility improvement by adjusting stress in shallow trench isolation |
JP2006165335A (ja) * | 2004-12-08 | 2006-06-22 | Toshiba Corp | 半導体装置 |
US7494852B2 (en) * | 2005-01-06 | 2009-02-24 | International Business Machines Corporation | Method for creating a Ge-rich semiconductor material for high-performance CMOS circuits |
US7701034B2 (en) * | 2005-01-21 | 2010-04-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy patterns in integrated circuit fabrication |
US7465972B2 (en) * | 2005-01-21 | 2008-12-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | High performance CMOS device design |
US7429775B1 (en) | 2005-03-31 | 2008-09-30 | Xilinx, Inc. | Method of fabricating strain-silicon CMOS |
US7238990B2 (en) * | 2005-04-06 | 2007-07-03 | Freescale Semiconductor, Inc. | Interlayer dielectric under stress for an integrated circuit |
US7232730B2 (en) * | 2005-04-29 | 2007-06-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a locally strained transistor |
US20060244074A1 (en) * | 2005-04-29 | 2006-11-02 | Chien-Hao Chen | Hybrid-strained sidewall spacer for CMOS process |
US7262484B2 (en) * | 2005-05-09 | 2007-08-28 | International Business Machines Corporation | Structure and method for performance improvement in vertical bipolar transistors |
KR100688547B1 (ko) * | 2005-05-18 | 2007-03-02 | 삼성전자주식회사 | Sti 구조를 가지는 반도체 소자 및 그 제조 방법 |
US7423283B1 (en) * | 2005-06-07 | 2008-09-09 | Xilinx, Inc. | Strain-silicon CMOS using etch-stop layer and method of manufacture |
US7037856B1 (en) * | 2005-06-10 | 2006-05-02 | Sharp Laboratories Of America, Inc. | Method of fabricating a low-defect strained epitaxial germanium film on silicon |
US7858458B2 (en) | 2005-06-14 | 2010-12-28 | Micron Technology, Inc. | CMOS fabrication |
US7528028B2 (en) * | 2005-06-17 | 2009-05-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Super anneal for process induced strain modulation |
KR100688555B1 (ko) * | 2005-06-30 | 2007-03-02 | 삼성전자주식회사 | Mos트랜지스터를 구비하는 반도체 소자 및 그 제조 방법 |
US20070010073A1 (en) * | 2005-07-06 | 2007-01-11 | Chien-Hao Chen | Method of forming a MOS device having a strained channel region |
US7586158B2 (en) * | 2005-07-07 | 2009-09-08 | Infineon Technologies Ag | Piezoelectric stress liner for bulk and SOI |
JP4664760B2 (ja) * | 2005-07-12 | 2011-04-06 | 株式会社東芝 | 半導体装置およびその製造方法 |
US7488670B2 (en) * | 2005-07-13 | 2009-02-10 | Infineon Technologies Ag | Direct channel stress |
US7442618B2 (en) * | 2005-07-16 | 2008-10-28 | Chartered Semiconductor Manufacturing, Ltd | Method to engineer etch profiles in Si substrate for advanced semiconductor devices |
US7358551B2 (en) * | 2005-07-21 | 2008-04-15 | International Business Machines Corporation | Structure and method for improved stress and yield in pFETs with embedded SiGe source/drain regions |
US7655991B1 (en) | 2005-09-08 | 2010-02-02 | Xilinx, Inc. | CMOS device with stressed sidewall spacers |
TWI267926B (en) * | 2005-09-23 | 2006-12-01 | Ind Tech Res Inst | A new method for high mobility enhancement strained channel CMOS with single workfunction metal-gate |
US7202513B1 (en) | 2005-09-29 | 2007-04-10 | International Business Machines Corporation | Stress engineering using dual pad nitride with selective SOI device architecture |
US7582947B2 (en) * | 2005-10-05 | 2009-09-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | High performance device design |
US7936006B1 (en) | 2005-10-06 | 2011-05-03 | Xilinx, Inc. | Semiconductor device with backfilled isolation |
US7615806B2 (en) | 2005-10-31 | 2009-11-10 | Freescale Semiconductor, Inc. | Method for forming a semiconductor structure and structure thereof |
US7575975B2 (en) * | 2005-10-31 | 2009-08-18 | Freescale Semiconductor, Inc. | Method for forming a planar and vertical semiconductor structure having a strained semiconductor layer |
JP2007141912A (ja) * | 2005-11-15 | 2007-06-07 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
DE102005063129B4 (de) * | 2005-12-30 | 2010-09-16 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung eines Halbleiterbauelements mit Isolationsgraben mit reduzierter Seitenwandverspannung |
DE102005063130B4 (de) * | 2005-12-30 | 2017-07-27 | Advanced Micro Devices, Inc. | Verfahren zum Bilden einer Grabenisolationsstruktur mit unterschiedlicher Verspannung |
DE102005063108A1 (de) * | 2005-12-30 | 2007-07-12 | Advanced Micro Devices, Inc., Sunnyvale | Technik zur Herstellung eines Isolationsgrabens als eine Spannungsquelle für die Verformungsverfahrenstechnik |
US7518193B2 (en) | 2006-01-10 | 2009-04-14 | International Business Machines Corporation | SRAM array and analog FET with dual-strain layers comprising relaxed regions |
JP2007189110A (ja) * | 2006-01-13 | 2007-07-26 | Sharp Corp | 半導体装置及びその製造方法 |
US20070164365A1 (en) * | 2006-01-17 | 2007-07-19 | Chan Joseph Y | Single stress liner for migration stability and speed |
US7678630B2 (en) * | 2006-02-15 | 2010-03-16 | Infineon Technologies Ag | Strained semiconductor device and method of making same |
JP2007220892A (ja) * | 2006-02-16 | 2007-08-30 | Toshiba Corp | 半導体装置及びその製造方法 |
US7544584B2 (en) | 2006-02-16 | 2009-06-09 | Micron Technology, Inc. | Localized compressive strained semiconductor |
US8017472B2 (en) * | 2006-02-17 | 2011-09-13 | Infineon Technologies Ag | CMOS devices having stress-altering material lining the isolation trenches and methods of manufacturing thereof |
US20070200196A1 (en) * | 2006-02-24 | 2007-08-30 | Lattice Semiconductor Corporation | Shallow trench isolation (STI) devices and processes |
US7323392B2 (en) * | 2006-03-28 | 2008-01-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | High performance transistor with a highly stressed channel |
US7566605B2 (en) * | 2006-03-31 | 2009-07-28 | Intel Corporation | Epitaxial silicon germanium for reduced contact resistance in field-effect transistors |
US20070267715A1 (en) * | 2006-05-18 | 2007-11-22 | Sunil Mehta | Shallow trench isolation (STI) with trench liner of increased thickness |
US7416989B1 (en) | 2006-06-30 | 2008-08-26 | Novellus Systems, Inc. | Adsorption based material removal process |
US7462916B2 (en) * | 2006-07-19 | 2008-12-09 | International Business Machines Corporation | Semiconductor devices having torsional stresses |
US7485544B2 (en) * | 2006-08-02 | 2009-02-03 | Micron Technology, Inc. | Strained semiconductor, devices and systems and methods of formation |
US7968960B2 (en) | 2006-08-18 | 2011-06-28 | Micron Technology, Inc. | Methods of forming strained semiconductor channels |
US20080044967A1 (en) * | 2006-08-19 | 2008-02-21 | Chartered Semiconductor Manufacturing Ltd. | Integrated circuit system having strained transistor |
DE102006046377A1 (de) * | 2006-09-29 | 2008-04-03 | Advanced Micro Devices, Inc., Sunnyvale | Halbleiterbauelement mit Isoliergräben, die unterschiedliche Arten an Verformung hervorrufen |
WO2008042144A2 (en) * | 2006-09-29 | 2008-04-10 | Advanced Micro Devices, Inc. | A semiconductor device comprising isolation trenches inducing different types of strain |
US7524777B2 (en) * | 2006-12-14 | 2009-04-28 | Texas Instruments Incorporated | Method for manufacturing an isolation structure using an energy beam treatment |
US7471548B2 (en) | 2006-12-15 | 2008-12-30 | International Business Machines Corporation | Structure of static random access memory with stress engineering for stability |
US7727856B2 (en) * | 2006-12-24 | 2010-06-01 | Chartered Semiconductor Manufacturing, Ltd. | Selective STI stress relaxation through ion implantation |
US7521763B2 (en) * | 2007-01-03 | 2009-04-21 | International Business Machines Corporation | Dual stress STI |
US8558278B2 (en) * | 2007-01-16 | 2013-10-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained transistor with optimized drive current and method of forming |
CN101271866B (zh) * | 2007-03-22 | 2010-05-19 | 中芯国际集成电路制造(上海)有限公司 | 用于mos晶体管的隔离结构及其形成方法 |
KR100842749B1 (ko) * | 2007-03-27 | 2008-07-01 | 주식회사 하이닉스반도체 | 반도체소자의 트렌치 소자분리막 형성방법 |
US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
US8110890B2 (en) | 2007-06-05 | 2012-02-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating semiconductor device isolation structure |
US7795119B2 (en) * | 2007-07-17 | 2010-09-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Flash anneal for a PAI, NiSi process |
US8440539B2 (en) * | 2007-07-31 | 2013-05-14 | Freescale Semiconductor, Inc. | Isolation trench processing for strain control |
KR20090016984A (ko) * | 2007-08-13 | 2009-02-18 | 삼성전자주식회사 | 트렌치 소자분리 영역을 갖는 반도체소자 및 그 제조방법 |
US7652335B2 (en) * | 2007-10-17 | 2010-01-26 | Toshiba America Electronics Components, Inc. | Reversely tapered contact structure compatible with dual stress liner process |
KR20090050899A (ko) * | 2007-11-16 | 2009-05-20 | 주식회사 동부하이텍 | 반도체 소자의 제조 방법 |
KR20090056015A (ko) * | 2007-11-29 | 2009-06-03 | 주식회사 하이닉스반도체 | 반도체 소자 및 그 제조 방법 |
KR100929720B1 (ko) * | 2007-12-03 | 2009-12-03 | 주식회사 동부하이텍 | 반도체 소자의 소자 분리막 형성 방법 |
US9412758B2 (en) * | 2007-12-10 | 2016-08-09 | Newport Fab, Llc | Semiconductor on insulator (SOI) structure with more predictable junction capacitance and method for fabrication |
US8187486B1 (en) | 2007-12-13 | 2012-05-29 | Novellus Systems, Inc. | Modulating etch selectivity and etch rate of silicon nitride thin films |
US20090166757A1 (en) * | 2007-12-27 | 2009-07-02 | International Business Machines Corporation | Stress engineering for sram stability |
KR101446331B1 (ko) * | 2008-02-13 | 2014-10-02 | 삼성전자주식회사 | 반도체 소자의 제조 방법 |
US9368410B2 (en) * | 2008-02-19 | 2016-06-14 | Globalfoundries Inc. | Semiconductor devices having tensile and/or compressive stress and methods of manufacturing |
US7943961B2 (en) * | 2008-03-13 | 2011-05-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strain bars in stressed layers of MOS devices |
US7981763B1 (en) * | 2008-08-15 | 2011-07-19 | Novellus Systems, Inc. | Atomic layer removal for high aspect ratio gapfill |
US7808051B2 (en) * | 2008-09-29 | 2010-10-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Standard cell without OD space effect in Y-direction |
US20100193879A1 (en) * | 2009-02-05 | 2010-08-05 | Ming-Han Liao | Isolation Region Implant and Structure |
JP2010283256A (ja) * | 2009-06-08 | 2010-12-16 | Toshiba Corp | 半導体装置およびnand型フラッシュメモリの製造方法 |
CN101630660B (zh) * | 2009-07-07 | 2013-01-23 | 北京大学 | 提高cmos晶体管抗辐照的方法、cmos晶体管及集成电路 |
US8218353B1 (en) | 2009-09-16 | 2012-07-10 | Altera Corporation | Memory element circuitry with stressed transistors |
US8138791B1 (en) | 2010-01-27 | 2012-03-20 | Altera Corporation | Stressed transistors with reduced leakage |
US8293602B2 (en) * | 2010-11-19 | 2012-10-23 | Micron Technology, Inc. | Method of fabricating a finFET having cross-hair cells |
US8609508B2 (en) * | 2010-12-08 | 2013-12-17 | Stmicroelectronics, Inc. | Method of fabricating an integrated circuit having a strain inducing hollow trench isolation region |
FR2972564B1 (fr) * | 2011-03-08 | 2016-11-04 | S O I Tec Silicon On Insulator Tech | Procédé de traitement d'une structure de type semi-conducteur sur isolant |
US8697522B2 (en) | 2011-07-05 | 2014-04-15 | International Business Machines Corporation | Bulk finFET with uniform height and bottom isolation |
US9318370B2 (en) * | 2011-08-04 | 2016-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | High-k dielectric liners in shallow trench isolations |
JP5917861B2 (ja) | 2011-08-30 | 2016-05-18 | 株式会社Screenホールディングス | 基板処理方法 |
FR2981793A1 (fr) | 2011-10-25 | 2013-04-26 | St Microelectronics Crolles 2 | Procede de fabrication de transistors a grille isolee |
FR2981792A1 (fr) * | 2011-10-25 | 2013-04-26 | St Microelectronics Crolles 2 | Procede de fabrication de transistors a grille isolee |
JP5944149B2 (ja) * | 2011-12-05 | 2016-07-05 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US8680576B2 (en) * | 2012-05-16 | 2014-03-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS device and method of forming the same |
US8685816B2 (en) * | 2012-06-11 | 2014-04-01 | Globalfoundries Inc. | Methods of forming semiconductor devices by forming semiconductor channel region materials prior to forming isolation structures |
US9006080B2 (en) * | 2013-03-12 | 2015-04-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Varied STI liners for isolation structures in image sensing devices |
US8962430B2 (en) | 2013-05-31 | 2015-02-24 | Stmicroelectronics, Inc. | Method for the formation of a protective dual liner for a shallow trench isolation structure |
US9419134B2 (en) | 2014-01-13 | 2016-08-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strain enhancement for FinFETs |
US9306067B2 (en) * | 2014-08-05 | 2016-04-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Nonplanar device and strain-generating channel dielectric |
US9941406B2 (en) | 2014-08-05 | 2018-04-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs with source/drain cladding |
CN105448914B (zh) * | 2014-08-28 | 2019-12-03 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
US20160079034A1 (en) * | 2014-09-12 | 2016-03-17 | Applied Materials Inc. | Flowable film properties tuning using implantation |
US9209301B1 (en) * | 2014-09-18 | 2015-12-08 | Soitec | Method for fabricating semiconductor layers including transistor channels having different strain states, and related semiconductor layers |
US9431268B2 (en) | 2015-01-05 | 2016-08-30 | Lam Research Corporation | Isotropic atomic layer etch for silicon and germanium oxides |
US9425041B2 (en) | 2015-01-06 | 2016-08-23 | Lam Research Corporation | Isotropic atomic layer etch for silicon oxides using no activation |
KR102320820B1 (ko) * | 2015-02-24 | 2021-11-02 | 삼성전자주식회사 | 집적회로 소자 및 그 제조 방법 |
US9577101B2 (en) | 2015-03-13 | 2017-02-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Source/drain regions for fin field effect transistors and methods of forming same |
CN104716083B (zh) * | 2015-03-20 | 2018-06-26 | 上海华力集成电路制造有限公司 | 形成浅槽隔离的方法 |
KR102460718B1 (ko) * | 2015-05-28 | 2022-10-31 | 삼성전자주식회사 | 집적회로 소자 |
KR20170065271A (ko) * | 2015-12-03 | 2017-06-13 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
US9847418B1 (en) * | 2016-07-26 | 2017-12-19 | Globalfoundries Inc. | Methods of forming fin cut regions by oxidizing fin portions |
US10699963B2 (en) | 2017-08-31 | 2020-06-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method of semiconductor device structure with isolation feature |
WO2019226341A1 (en) | 2018-05-25 | 2019-11-28 | Lam Research Corporation | Thermal atomic layer etch with rapid temperature cycling |
US10483154B1 (en) * | 2018-06-22 | 2019-11-19 | Globalfoundries Inc. | Front-end-of-line device structure and method of forming such a front-end-of-line device structure |
WO2020014065A1 (en) | 2018-07-09 | 2020-01-16 | Lam Research Corporation | Electron excitation atomic layer etch |
US11101218B2 (en) * | 2018-08-24 | 2021-08-24 | Micron Technology, Inc. | Integrated assemblies having metal-containing regions coupled with semiconductor regions |
US11088022B2 (en) * | 2018-09-27 | 2021-08-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Different isolation liners for different type FinFETs and associated isolation feature fabrication |
CN109616446A (zh) * | 2018-12-10 | 2019-04-12 | 德淮半导体有限公司 | 半导体装置的制造方法 |
US20220319909A1 (en) * | 2021-04-01 | 2022-10-06 | Nanya Technology Corporation | Method for manufacturing a semiconductor memory device |
TWI782553B (zh) * | 2021-05-31 | 2022-11-01 | 力晶積成電子製造股份有限公司 | 半導體元件 |
US20230200238A1 (en) * | 2021-12-17 | 2023-06-22 | Texas Instruments Incorporated | Embedded thermoelectric cooler using thermally anisotropic mesas for power device heat generating source temperature reduction |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6193641A (ja) * | 1984-10-15 | 1986-05-12 | Nec Corp | 半導体装置 |
JPH02273956A (ja) * | 1989-04-15 | 1990-11-08 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US20020031890A1 (en) * | 2000-08-28 | 2002-03-14 | Takayuki Watanabe | Semiconductor device of STI structure and method of fabricating MOS transistors having consistent threshold voltages |
US6475838B1 (en) * | 2000-03-14 | 2002-11-05 | International Business Machines Corporation | Methods for forming decoupling capacitors |
Family Cites Families (88)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US621131A (en) * | 1899-03-14 | Polishing-wheel | ||
US4069094A (en) * | 1976-12-30 | 1978-01-17 | Rca Corporation | Method of manufacturing apertured aluminum oxide substrates |
JPS551103A (en) * | 1978-06-06 | 1980-01-07 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Semiconductor resistor |
US4314289A (en) * | 1979-12-07 | 1982-02-02 | International Business Machines Corporation | Biased pulsed recording systems and methods |
US4497683A (en) * | 1982-05-03 | 1985-02-05 | At&T Bell Laboratories | Process for producing dielectrically isolated silicon devices |
US4631803A (en) * | 1985-02-14 | 1986-12-30 | Texas Instruments Incorporated | Method of fabricating defect free trench isolation devices |
US4892614A (en) * | 1986-07-07 | 1990-01-09 | Texas Instruments Incorporated | Integrated circuit isolation process |
JPH0640583B2 (ja) * | 1987-07-16 | 1994-05-25 | 株式会社東芝 | 半導体装置の製造方法 |
US4946799A (en) * | 1988-07-08 | 1990-08-07 | Texas Instruments, Incorporated | Process for making high performance silicon-on-insulator transistor with body node to source node connection |
JPH0394479A (ja) * | 1989-06-30 | 1991-04-19 | Hitachi Ltd | 感光性を有する半導体装置 |
US5222234A (en) * | 1989-12-28 | 1993-06-22 | International Business Machines Corp. | Combining search criteria to form a single search and saving search results for additional searches in a document interchange system |
US5155571A (en) * | 1990-08-06 | 1992-10-13 | The Regents Of The University Of California | Complementary field effect transistors having strained superlattice structure |
JP3019430B2 (ja) * | 1991-01-21 | 2000-03-13 | ソニー株式会社 | 半導体集積回路装置 |
US5338960A (en) * | 1992-08-05 | 1994-08-16 | Harris Corporation | Formation of dual polarity source/drain extensions in lateral complementary channel MOS architectures |
US5461250A (en) * | 1992-08-10 | 1995-10-24 | International Business Machines Corporation | SiGe thin film or SOI MOSFET and method for making the same |
US5273915A (en) * | 1992-10-05 | 1993-12-28 | Motorola, Inc. | Method for fabricating bipolar junction and MOS transistors on SOI |
US5596529A (en) * | 1993-11-30 | 1997-01-21 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
JPH0846139A (ja) * | 1994-05-06 | 1996-02-16 | Texas Instr Inc <Ti> | ポリシリコン抵抗器とその作成法 |
US5534713A (en) * | 1994-05-20 | 1996-07-09 | International Business Machines Corporation | Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers |
US5479033A (en) * | 1994-05-27 | 1995-12-26 | Sandia Corporation | Complementary junction heterostructure field-effect transistor |
US5447884A (en) * | 1994-06-29 | 1995-09-05 | International Business Machines Corporation | Shallow trench isolation with thin nitride liner |
US6433382B1 (en) * | 1995-04-06 | 2002-08-13 | Motorola, Inc. | Split-gate vertically oriented EEPROM device and process |
US5629544A (en) * | 1995-04-25 | 1997-05-13 | International Business Machines Corporation | Semiconductor diode with silicide films and trench isolation |
US5708288A (en) * | 1995-11-02 | 1998-01-13 | Motorola, Inc. | Thin film silicon on insulator semiconductor integrated circuit with electrostatic damage protection and method |
TW335558B (en) | 1996-09-03 | 1998-07-01 | Ibm | High temperature superconductivity in strained SiSiGe |
US5789807A (en) * | 1996-10-15 | 1998-08-04 | International Business Machines Corporation | On-chip power distribution for improved decoupling |
US5811857A (en) * | 1996-10-22 | 1998-09-22 | International Business Machines Corporation | Silicon-on-insulator body-coupled gated diode for electrostatic discharge (ESD) and analog applications |
US5763315A (en) * | 1997-01-28 | 1998-06-09 | International Business Machines Corporation | Shallow trench isolation with oxide-nitride/oxynitride liner |
US5714777A (en) * | 1997-02-19 | 1998-02-03 | International Business Machines Corporation | Si/SiGe vertical junction field effect transistor |
JP4053647B2 (ja) * | 1997-02-27 | 2008-02-27 | 株式会社東芝 | 半導体記憶装置及びその製造方法 |
US5906951A (en) * | 1997-04-30 | 1999-05-25 | International Business Machines Corporation | Strained Si/SiGe layers on insulator |
DE19720008A1 (de) * | 1997-05-13 | 1998-11-19 | Siemens Ag | Integrierte CMOS-Schaltungsanordnung und Verfahren zu deren Herstellung |
KR100400808B1 (ko) * | 1997-06-24 | 2003-10-08 | 매사츄세츠 인스티튜트 오브 테크놀러지 | 그레이드된 GeSi층 및 평탄화를 사용한 Si상의 Ge의 쓰레딩 전위 밀도 제어 |
US6221709B1 (en) * | 1997-06-30 | 2001-04-24 | Stmicroelectronics, Inc. | Method of fabricating a CMOS integrated circuit device with LDD N-channel transistor and non-LDD P-channel transistor |
EP0923116A1 (en) * | 1997-12-12 | 1999-06-16 | STMicroelectronics S.r.l. | Process for manufacturing integrated multi-crystal silicon resistors in MOS technology and integrated MOS device comprising multi-crystal silicon resistors |
US6100153A (en) * | 1998-01-20 | 2000-08-08 | International Business Machines Corporation | Reliable diffusion resistor and diffusion capacitor |
JP3265569B2 (ja) * | 1998-04-15 | 2002-03-11 | 日本電気株式会社 | 半導体装置及びその製造方法 |
US6558998B2 (en) * | 1998-06-15 | 2003-05-06 | Marc Belleville | SOI type integrated circuit with a decoupling capacity and process for embodiment of such a circuit |
JP3403076B2 (ja) * | 1998-06-30 | 2003-05-06 | 株式会社東芝 | 半導体装置及びその製造方法 |
US6008095A (en) * | 1998-08-07 | 1999-12-28 | Advanced Micro Devices, Inc. | Process for formation of isolation trenches with high-K gate dielectrics |
US6387739B1 (en) * | 1998-08-07 | 2002-05-14 | International Business Machines Corporation | Method and improved SOI body contact structure for transistors |
US6015993A (en) * | 1998-08-31 | 2000-01-18 | International Business Machines Corporation | Semiconductor diode with depleted polysilicon gate structure and method |
JP2000132990A (ja) * | 1998-10-27 | 2000-05-12 | Fujitsu Ltd | 冗長判定回路、半導体記憶装置及び冗長判定方法 |
US6258664B1 (en) * | 1999-02-16 | 2001-07-10 | Micron Technology, Inc. | Methods of forming silicon-comprising materials having roughened outer surfaces, and methods of forming capacitor constructions |
US6358791B1 (en) * | 1999-06-04 | 2002-03-19 | International Business Machines Corporation | Method for increasing a very-large-scale-integrated (VLSI) capacitor size on bulk silicon and silicon-on-insulator (SOI) wafers and structure formed thereby |
US6362082B1 (en) * | 1999-06-28 | 2002-03-26 | Intel Corporation | Methodology for control of short channel effects in MOS transistors |
US6339232B1 (en) * | 1999-09-20 | 2002-01-15 | Kabushika Kaisha Toshiba | Semiconductor device |
US7391087B2 (en) * | 1999-12-30 | 2008-06-24 | Intel Corporation | MOS transistor structure and method of fabrication |
US6255175B1 (en) * | 2000-01-07 | 2001-07-03 | Advanced Micro Devices, Inc. | Fabrication of a field effect transistor with minimized parasitic Miller capacitance |
TW503439B (en) * | 2000-01-21 | 2002-09-21 | United Microelectronics Corp | Combination structure of passive element and logic circuit on silicon on insulator wafer |
US6281059B1 (en) * | 2000-05-11 | 2001-08-28 | Worldwide Semiconductor Manufacturing Corp. | Method of doing ESD protective device ion implant without additional photo mask |
DE10025264A1 (de) * | 2000-05-22 | 2001-11-29 | Max Planck Gesellschaft | Feldeffekt-Transistor auf der Basis von eingebetteten Clusterstrukturen und Verfahren zu seiner Herstellung |
JP2001338988A (ja) * | 2000-05-25 | 2001-12-07 | Hitachi Ltd | 半導体装置及びその製造方法 |
US6555839B2 (en) * | 2000-05-26 | 2003-04-29 | Amberwave Systems Corporation | Buried channel strained silicon FET using a supply layer created through ion implantation |
JP3843708B2 (ja) * | 2000-07-14 | 2006-11-08 | 日本電気株式会社 | 半導体装置およびその製造方法ならびに薄膜コンデンサ |
US6429061B1 (en) * | 2000-07-26 | 2002-08-06 | International Business Machines Corporation | Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation |
FR2812764B1 (fr) * | 2000-08-02 | 2003-01-24 | St Microelectronics Sa | Procede de fabrication d'un substrat de type substrat-sur- isolant ou substrat-sur-vide et dispositif obtenu |
JP4044276B2 (ja) * | 2000-09-28 | 2008-02-06 | 株式会社東芝 | 半導体装置及びその製造方法 |
US6413802B1 (en) * | 2000-10-23 | 2002-07-02 | The Regents Of The University Of California | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture |
WO2002047168A2 (en) * | 2000-12-04 | 2002-06-13 | Amberwave Systems Corporation | Cmos inverter circuits utilizing strained silicon surface channel mosfets |
US6414355B1 (en) * | 2001-01-26 | 2002-07-02 | Advanced Micro Devices, Inc. | Silicon-on-insulator (SOI) chip having an active layer of non-uniform thickness |
US6894324B2 (en) * | 2001-02-15 | 2005-05-17 | United Microelectronics Corp. | Silicon-on-insulator diodes and ESD protection circuits |
US6518610B2 (en) * | 2001-02-20 | 2003-02-11 | Micron Technology, Inc. | Rhodium-rich oxygen barriers |
US6475869B1 (en) * | 2001-02-26 | 2002-11-05 | Advanced Micro Devices, Inc. | Method of forming a double gate transistor having an epitaxial silicon/germanium channel region |
US6593181B2 (en) * | 2001-04-20 | 2003-07-15 | International Business Machines Corporation | Tailored insulator properties for devices |
US6586311B2 (en) * | 2001-04-25 | 2003-07-01 | Advanced Micro Devices, Inc. | Salicide block for silicon-on-insulator (SOI) applications |
JP2002329861A (ja) * | 2001-05-01 | 2002-11-15 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US6952040B2 (en) * | 2001-06-29 | 2005-10-04 | Intel Corporation | Transistor structure and method of fabrication |
US6576526B2 (en) * | 2001-07-09 | 2003-06-10 | Chartered Semiconductor Manufacturing Ltd. | Darc layer for MIM process integration |
WO2003017336A2 (en) | 2001-08-13 | 2003-02-27 | Amberwave Systems Corporation | Dram trench capacitor and method of making the same |
US6521952B1 (en) * | 2001-10-22 | 2003-02-18 | United Microelectronics Corp. | Method of forming a silicon controlled rectifier devices in SOI CMOS process for on-chip ESD protection |
US6621131B2 (en) * | 2001-11-01 | 2003-09-16 | Intel Corporation | Semiconductor transistor having a stressed channel |
JP4173658B2 (ja) * | 2001-11-26 | 2008-10-29 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
US6657276B1 (en) * | 2001-12-10 | 2003-12-02 | Advanced Micro Devices, Inc. | Shallow trench isolation (STI) region with high-K liner and method of formation |
US6600170B1 (en) * | 2001-12-17 | 2003-07-29 | Advanced Micro Devices, Inc. | CMOS with strained silicon channel NMOS and silicon germanium channel PMOS |
US6784101B1 (en) * | 2002-05-16 | 2004-08-31 | Advanced Micro Devices Inc | Formation of high-k gate dielectric layers for MOS devices fabricated on strained lattice semiconductor substrates with minimized stress relaxation |
WO2003105204A2 (en) * | 2002-06-07 | 2003-12-18 | Amberwave Systems Corporation | Semiconductor devices having strained dual channel layers |
US6812103B2 (en) * | 2002-06-20 | 2004-11-02 | Micron Technology, Inc. | Methods of fabricating a dielectric plug in MOSFETS to suppress short-channel effects |
US6686247B1 (en) * | 2002-08-22 | 2004-02-03 | Intel Corporation | Self-aligned contacts to gates |
JP4030383B2 (ja) * | 2002-08-26 | 2008-01-09 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
US6573172B1 (en) * | 2002-09-16 | 2003-06-03 | Advanced Micro Devices, Inc. | Methods for improving carrier mobility of PMOS and NMOS devices |
US6720619B1 (en) * | 2002-12-13 | 2004-04-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator chip incorporating partially-depleted, fully-depleted, and multiple-gate devices |
US6919233B2 (en) * | 2002-12-31 | 2005-07-19 | Texas Instruments Incorporated | MIM capacitors and methods for fabricating same |
US6921913B2 (en) * | 2003-03-04 | 2005-07-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Strained-channel transistor structure with lattice-mismatched zone |
US6794764B1 (en) * | 2003-03-05 | 2004-09-21 | Advanced Micro Devices, Inc. | Charge-trapping memory arrays resistant to damage from contact hole information |
US6762448B1 (en) * | 2003-04-03 | 2004-07-13 | Advanced Micro Devices, Inc. | FinFET device with multiple fin structures |
US6891192B2 (en) * | 2003-08-04 | 2005-05-10 | International Business Machines Corporation | Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions |
US6872610B1 (en) * | 2003-11-18 | 2005-03-29 | Texas Instruments Incorporated | Method for preventing polysilicon mushrooming during selective epitaxial processing |
-
2003
- 2003-04-25 US US10/423,513 patent/US6882025B2/en not_active Expired - Lifetime
- 2003-10-03 TW TW092127405A patent/TWI222715B/zh not_active IP Right Cessation
- 2003-10-17 CN CNB2003101019562A patent/CN1293637C/zh not_active Expired - Fee Related
-
2004
- 2004-04-23 CN CNU2004200483776U patent/CN2751444Y/zh not_active Expired - Lifetime
- 2004-04-23 SG SG200402719A patent/SG115690A1/en unknown
-
2005
- 2005-03-16 US US11/081,919 patent/US7052964B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6193641A (ja) * | 1984-10-15 | 1986-05-12 | Nec Corp | 半導体装置 |
JPH02273956A (ja) * | 1989-04-15 | 1990-11-08 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US6475838B1 (en) * | 2000-03-14 | 2002-11-05 | International Business Machines Corporation | Methods for forming decoupling capacitors |
US20020031890A1 (en) * | 2000-08-28 | 2002-03-14 | Takayuki Watanabe | Semiconductor device of STI structure and method of fabricating MOS transistors having consistent threshold voltages |
Also Published As
Publication number | Publication date |
---|---|
CN2751444Y (zh) | 2006-01-11 |
CN1540757A (zh) | 2004-10-27 |
US6882025B2 (en) | 2005-04-19 |
TW200423306A (en) | 2004-11-01 |
SG115690A1 (en) | 2005-10-28 |
TWI222715B (en) | 2004-10-21 |
US20050156274A1 (en) | 2005-07-21 |
US20040212035A1 (en) | 2004-10-28 |
US7052964B2 (en) | 2006-05-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1293637C (zh) | 具有应变沟道的互补式金属氧化物半导体及其制作方法 | |
CN1263119C (zh) | 用于生产cmos器件的方法 | |
CN1293635C (zh) | 可同时具有部分耗尽晶体管与完全耗尽晶体管的芯片及其制作方法 | |
CN1317772C (zh) | 半导体器件及其制造方法 | |
JP5235784B2 (ja) | 半導体装置 | |
CN100345280C (zh) | 具有晶格不相称区的变形沟道晶体管结构及其制造方法 | |
CN1215554C (zh) | 互补型金属氧化物半导体器件及其制造方法 | |
CN1670965A (zh) | 源极及漏极中聚含掺质金属的晶体管 | |
CN1619817A (zh) | 具有不同栅极介质的半导体器件及其制造方法 | |
CN1941329A (zh) | 用于cmos技术的应变感应迁移率增强纳米器件及工艺 | |
CN101075562A (zh) | 制造晶体管结构的方法 | |
CN1866524A (zh) | 半导体器件及其制造方法 | |
CN1645625A (zh) | 半导体装置及其形成方法 | |
CN1976033A (zh) | 半导体器件及其制造方法 | |
CN1913111A (zh) | 半导体元件及其形成方法 | |
CN1828831A (zh) | 半导体衬底的形成方法及形成的半导体衬底 | |
CN101030541A (zh) | 半导体晶体管元件及其制作方法 | |
CN1858913A (zh) | 半导体器件及其制造方法 | |
CN1702866A (zh) | 半导体器件 | |
CN101076894A (zh) | 绝缘膜半导体装置及方法 | |
CN1925159A (zh) | 半导体器件以及其制造方法 | |
CN1557023A (zh) | 用于包覆栅金属氧化物半导体场效应晶体管的方法 | |
CN1255865C (zh) | 半导体装置的制造方法 | |
CN1301556C (zh) | Cmos组件及其制造方法 | |
CN1112292A (zh) | 半导体器件及其制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070103 |