CN1270417A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

Info

Publication number
CN1270417A
CN1270417A CN00106890A CN00106890A CN1270417A CN 1270417 A CN1270417 A CN 1270417A CN 00106890 A CN00106890 A CN 00106890A CN 00106890 A CN00106890 A CN 00106890A CN 1270417 A CN1270417 A CN 1270417A
Authority
CN
China
Prior art keywords
semiconductor chip
circuitry substrate
chip
bonding agent
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN00106890A
Other languages
English (en)
Other versions
CN1161834C (zh
Inventor
土津田义久
左座靖之
玉置和雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
III Holdings 10 LLC
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of CN1270417A publication Critical patent/CN1270417A/zh
Application granted granted Critical
Publication of CN1161834C publication Critical patent/CN1161834C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29344—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29355—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Abstract

用各向异性导电粘接剂把第一半导体芯片安装到电路衬底上时,使它的一部分伸出第一半导体芯片外。第二半导体芯片安装在第一半导体芯片和用伸出树脂构成的支承部分上。用支承部分从下面支承第二半导体芯片的伸出部分。于是,为了达到高密度,在有多个叠置的半导体芯片的半导体器件中,当叠置于其上的半导体芯片的一部分从叠在电路衬底上的半导体芯片伸出时,可以在伸出部分形成的电极上更好地进行引线键合工艺。

Description

半导体器件及其制造方法
本发明涉及半导体器件及其制造方法。特别涉及叠置多个半导体芯片而使其具有高密度的半导体器件的制造方法和结构。
近年来，随着半导体器件的小型化，已开发出实质上已减小到芯片尺寸的半导体器件。半导体器件的该小型化结构称作CSP(芯片尺寸封装)结构。
图10(a)和10(b)展示出有CSP结构的半导体实例。
图10(a)所示CSP结构的半导体器件中，半导体芯片50用其上形成有例如晶体管的元件(没画出)的表面(以下称作有源面)面向上安装到电路衬底上(面向上接合)。有源面上形成的电极(为了使它们与突起电极有区别以下称作平面电极68)用引线58连接到电路衬底53上，即，更具体地说，连接到电路衬底53上形成的布线层54的平面电极(没画出)上。用这类引线58的电极之间的连接通常称作引线键合(wire bonding)。
这里，图中，数字60代表经过电路衬底53中形成的通孔61连接到布线层54的外引出端。用树脂涂层59覆盖安装有半导体芯片50一侧上的电路衬底53的表面。
图10(b)所示CSP结构的半导体器件中，半导体芯片50用它的有源面面向下地封装在电路衬底53上(面向下接合)。在有源面上形成的平面电极(没画出)上形成突起电极56，使突起电极56直接连接到布线层54上的平面电极(没画出)。这类直接连接电极的连接通常称作倒装接合(flip-chip bonding)。
而且，要封装到便携式信息设备等上的某些结构企图提供“附加值”和进一步增大容量，因此，在一个封壳中包含多个半导体芯片，由此增大了封装密度。这种情况下，在多芯片模块中多个芯片按两维简单放置，这不可能构成比半导体芯片总面积小的半导体封装。
已提出的叠片方式安装多个半导体芯片企图从技术上进一步提高封装密度。图11(a)和11(b)展示出有多个半导体芯片叠片的CSP结构的这种半导体器件。
图11(a)所示CSP结构的半导体器件中，第一半导体芯片51和第二半导体芯片52按叠片方式安装到电路衬底53上，这些半导体芯片用引线58的引线键合方式分别连接到电路衬底53上(现有技术(1))。
图11(b)所示CSP结构的半导体器件中，第一半导体芯片51和第二半导体芯片52叠置在电路衬底53上，上面的第二半导体芯片52用引线键合连接到电路衬底53上，下面的第一半导体芯片51用倒装接合法连接到电路衬底53上。(见日本特开专利申请No.47998/1993(Tokukaihei 5-47998)(公开日1993年2月26日)和日本特开专利申请No.326710/1995(Tokukaihei 7-326710)(公开日1995年12月12日，现有技术(2)))。
而且，如图12所示，日本特开专利申请No.84128/1988(Tokukaishou 63-84128)(公开日期1988年4月14日)披露了一种半导体器件，其中，连接系统采用了与现有技术(2)相同的方式即把引线键合和倒装芯片接合法组合，其中，把上面的第二半导体芯片52设置成比下面的第一半导体芯片51大，而且，这些芯片封装在如母板的电路衬底53′上(现有技术(3))。
但是，这些常规的结构中，适用的半导体芯片的尺寸和组合都有限，使其应用受到限制。
具体地说，图11(a)所示的现有技术(1)中，当上面的第二半导体芯片52大到大于下面的第一半导体芯片51时，就不可能保证有足够的空间用来把平面电极68a安装到第一半导体芯片51的有源面上。因此，不可能用比第一半导体芯片51大的第二半导体芯片52。
另一方面，图11(b)所示的现有技术(2)中，由于用倒装接合法把下面的第一半导体芯片51连接到电路衬底53上，则不会出现现有技术(1)中所述的问题。
但是，现有技术(2)中，通常把第二半导体芯片52的尺寸规定为小于或等于第一半导体芯51的尺寸。其原因是，当把上面的第二半导体芯片52做得较大时，不可能在其上进行稳定的引线键合。换言之，由于不能支承于下面的与第二半导体芯片52的引线连接的平面电极68，因此会因撞击和引线键合时加的负荷或足够大的负荷使第二半导体芯片52损坏，而且，超声波也不能用。
这里，图12所示现有技术(3)中，尽管在它的结构中上面的第二半导体芯片52做得较大，但是，第二半导体芯片52的平面电极68限定在下面的第一半导体51的尺寸范围内，以便使引线键合稳定。
该结构有设置在离开第二半导体芯片52的边缘的平面电极58，该结构会出现的问题是，在把晶片分割成半导体芯片的划片工艺中会使芯片周围的元件受损或接触芯片边缘。
因此，不可能使叠置的芯片中的一个芯片与位于其下的其它芯片组合，例如一个实际上是方形的芯片与另一个窄的矩形芯片的组合。
这里，提出了另一种方法，把其厚度与第一半导体芯片51的厚度相同的支承件插到伸出的第二半导体芯片52的下部；但是，这种结构不适用，因为，很难制成有高精度的相同厚度的支承件，而且，工艺复杂，使成本增加。
而且，当上面的第二半导体芯片52较小时，如果它的第一半导体片51小得多。它们也不能组合。换言之，引线58变得太长，会引起引线移动和变形。当企图在布线层54上尽可能靠近第一半导体芯片51的位置连接引线58时，由于与第一半导体芯片51的边缘接触，因此，可能会出现短路。为避免出现该问题，在布线层54上远离第一半导体芯片51的位置连接引线58时，封装尺寸会变得更大。
本发明涉及半导体器件，用叠置多个半导体芯片的方法获得高密度，本发明的目的是，提供一种半导体器，其中放在其它半导体芯片上的半导体芯片的一部分从叠在电路衬底上的半导芯片伸出时，最好用放在伸出部分的电极进行引线键合，和这种半导体器件的制造方法。
为达到上述目的，本发明的半导体器件的制造方法包括以下工艺步骤；
a)给电路衬底加粘接剂，通过粘接剂用倒装接合法将第一半导体芯片连接到电路衬底上；
b)有从第一半导体芯片伸出的伸出部分的第二半导体芯片用其已连接到第一半导体芯片背面的背面，利用伸出部分的引线键合，连接到电路衬底上；和
c)用粘接剂的一部分形成用于支承伸出部分的支承部分。
上述方法中，通过粘接剂用倒装接合法将第一半导体芯片连接到电路衬底上。用引线键合把第二半导体芯片连接到电路衬底。
半导体器件的常规制造方法中，使用上述的倒装接合和引线键合的组合连接系统时，限制了第一和第二半导体芯片的尺寸和形状。
首先，在常规系统中，用上述连接方法连接芯片和电路衬底时，第二半导体芯片从第一半导体芯片伸出时会出现以下问题：
当在第二半导体芯片从第一半导体芯片伸出的部分进行引线键合时，第二半导体芯片会因其撞击和负荷而损坏。因而，在半导体器件的常规制造方法中，在由第一半导体芯片支承的位置和位于里边的第二半导体芯片的伸出部分进行引线键合，以防止第二半导体芯片损坏。但是，这种常规方法在连接中要用长引线，这会引起引线移动和变形。
第二，常规方法中，当两个芯片中的一个芯片比另一芯片小得多时，较小的芯片用作第二半导体芯片；但是，这也要用长引线，也会出现引线移动和变形的问题，对这种芯片组合也不适用。
相反，在本发明的上述方法中，用连接到第一半导体芯片的粘接剂的一部分构成支承第二半导体芯片伸出部分的支承部分。
随后，由于支承部分支承第二半导体芯片的伸出部分。使支承部分能稳定地进行引线键合工艺而不会损坏第二半导体芯片。
而且，当两个芯片中的一个芯片比另一芯片小得多时，也可以把较小的芯片不用作第二半导体芯片而用作第一半导体芯片；因此，可以避免通常出现的引线移动和变形的问题。
如上所述，按本发明的半导体器件的制造方法中，由于对第一和第二半导体芯片的尺寸和形状无限制，因此，可以应用有各种尺寸和形状的芯片组合，如方形芯片与矩形芯片组合，因此拓宽了设计自由度。
而且，在按本发明的半导体器件的制造方法中，用连接第一半导体芯片的粘接剂的一部分构成支承部分，不需要单独安装新件，因此，防止增加工艺步骤，和防止增加成本。
而且，为达到上述目的，按本发明的半导体器件具有下述部件：
第一半导体芯片，它通过粘接剂用其有源面面向电路衬底连接到电路衬底上；
第二半导体芯片，有由第一半导体芯片伸出的部分，其背面粘接到第一半导体芯片的背面，用引线键合把伸出部分连接到电路板上；和
用于支承伸出部分的支承部分，由粘接剂的一部分构成。
上述的结构中第一和第二半导体芯片用其相互接合在一起的背面相互接合，并分别连接到电路衬底。在从第一半导体芯片伸出的伸出部分使第二半导体芯片与电路衬底连接。
换言之，与常规结构的差别是，在第一半导体芯片支承的第二半导体芯片的部分不用引线连接；但是该布线部分由粘接剂的一部分构成的支承部分支承。因此有可能进行更好的引线键合而不损坏第二半导体芯片。而且不必在第二半导体芯片的由第一半导体芯片支承的部分进行引线键合。因此，可以避免引线变形的常规问题。
通过以下结合附图所做的详细说明将会更充分理解本发明的特性和优点。
图1示出本发明的一个实施例，它是有CSP结构的半导体器件的横截面图；
图2(a)至2(f)是图1所示半导体器件制造工艺的横截面图；
图3(a)至3(c)是展示第一半导体芯片粘接到电路衬底上的粘接工艺的横截面图；
图4(a)是展示第二半导体芯片的安装状态的横截面图；
图4(b)是展示引线键合到电路衬底的第二半导体芯片的状态的横截面图；
图5展示出本发明的另一实施例，它是封装型半导体器件的横截面图；
图6(a)和6(b)是本发明又一实施例的透视图；每个图展示一个第一和第二半导体芯片之间的粘接例。
图7(a)和7(b)是在电路衬底上安装粘接的第一和第二半导体芯片的工艺的横截面图；
图8(a)和8(b)是本发明又一实施例的封装型半导体器件的制造方法的横截面图；
图9(a)和9(b)是图8(b)所示工艺之后的工艺的横截面图。
图10(a)和10(b)是常规半导体器件的横截面图；
图11(a)和11(b)是另一常规半导体器件的横截面图；
图12是又一常规半导体器件的横截面图。
参见图1至5说明本发明的一个实施例如下。
如图1所示，本实施例的半导体器件有CSP(芯片尺寸封装)结构，其中，第一半导体芯片1和第二半导体芯片2叠置在电路衬底3上，这些第一半导体芯片1和第二半导体芯片2用树脂涂层9覆盖。此后，把在有例如晶体管的元件(没画出)一侧上的第一半导体芯片1和第二半导体芯片2的表面称作“有源面”，而把在对着有源面一侧上的表面称作“背面”(在权利要求中称为“背面”)。
在装有第一半导体芯片1一侧的一个表面上的电路衬底3上形成布线层4，在相对一侧的表面上形成封装用的外引线端10。封装用的外引线端10和布线层4经电路衬底3中形成的通孔11而电连接。
第一半导体芯片1用其有源面面向上安装在电路衬底3上。在有源面上形成的平面电极(没画出)上形成伸出电极6，这些伸出电极6与电路衬底3的布线层4的平面电极(没画出)相互连接。换言之，用倒装接合法第一半导体芯片1连接到电路衬底3上。
第二半导体芯片2的长度和宽度均大于第一半导体芯片1的长度和宽度，并用其有源面对着电路衬底3安装。在第二半导体芯片2的背面用绝缘粘接剂7粘接到第一半导体芯片1的背面。第一半导体芯片1和第二半导体芯片2叠置状态中在伸出部分上形成有源面的平面电极18，用引线8使电路衬底3的布线层4的平面电极(没画出)与平面电极18互连。换言之，用引线键合把第二半导体芯片2连接到电路衬底3上。
这里，与图12所示常规半导体器件的差别是，平面电极18是形成在用支承部分21从下面支承的第二半导体芯片2的伸出部分(突出部分)上。因而，即使当平面电极18形成在伸出部分上时，由于伸出部分被支承部分21支承，因此，撞击和负荷均不会损坏第二半导体芯片2，因此，可以加足够的负荷和用超声波进行稳定的引线键合。
正如以下将要说明的，这些支承部分21由薄膜形的各向导性导电粘接剂20的一部分构成，因此，可以用倒装接合法把第一半导体芯片1焊到电路衬底上并使其坚固。
之后，参见图2(a)至2(f)，到图4(a)和4(b)，说明有上述结构的半导体器件的制造工艺。图2(a)至2(f)是展示制造多个半导体器件工艺的横截面图，例如，这些图示出了一批制造四个有CSP结构的半导体器件的典型情况。
首先，如图2(a)所示，把薄膜形的各向异性导电粘接剂20固定到电路衬底3A上，以便暂时压接。图中没具体表示出，在电路衬底3A上形成了四个所述的布线层4，按覆盖各布线层4的方式暂时压接各向异性导电粘接剂20。例如在100℃加热条件下，在10kgf/cm2的压力下经10秒钟进行暂时压接工艺。
各向异性导电粘接剂20最好用热固性树脂制成，其原因将在以后说明；例如，把例如Au和Ni的金属颗粒，或树脂上镀金属的颗粒，分散在以环氧树脂为基的热固性粘接剂中，并混合，制成薄膜形粘接树脂。
这里，除这种各向异性导电粘接剂20之外，也可采用绝缘粘接剂，只要它在伸出电极6和电路衬底3A的平面电极之间的接合工艺中有足够的可靠性即可。关于绝缘粘接剂，例如，是能使伸出电极6和电路衬底3A的平面电极之间具有导电性的粘接剂，例如，只有树脂的粘接强度和收缩力的粘接剂。以下将说明的在实施例3中用的粘接片23(见图8(a)和8(b))是这类粘接剂的一个实例。
之后，如图2(b)所示，第一半导体芯片1安装在各向异性导电粘接剂20上。第一半导体芯片1用其有源面对着电路衬底3A安装，并经伸出电极6连接到电路衬底3A。此时，各向异性导电粘接剂20从第一半导体芯片1挤出，成为伸出部分，因此，由伸出树脂构成支承部分21，支承体的高度与第一半导体芯片1的背面相同。
之后，如图2(c)所示，第二半导体芯片2用其有源面面向上安装在第一半导体芯片1和支承部分21上。
此后，如图2(d)所示，第二半导体芯片2和电路衬底3A用引线8连接，用树脂涂层9覆盖第一半导体芯片1，第二半导体芯片2，引线8和电路衬底3A。因此完成了第一半导体芯片1和第二半导体芯片2的安装工艺。
此后，如图2(e)所示，电路衬底3A的通孔部分11(见图1)上形成焊料珠用作封装用外引线端10，切掉电路衬底3A的不需要部分，如图2(f)所示，完成了作为单个部件的有CSP结构的半导体器件。
参见图3(a)至3(c)和图4(a)和4(b)，将更进一步说明上述工艺中的把第一半导体芯片1和第二半导体芯片2连接到电路衬底3A的工艺。
首先，如图3(a)所示，用粘接工具14(吸气支承件)使第一半导体芯片1和电路衬底3A面对面相互准。粘接工具14有吸嘴12和吸面13，把第一半导体芯片1从其背面1侧吸到吸面13，以面对电路衬底3A。此时，使第一半导体芯片1的伸出电极6与布线层4上形成的平面电极(没画出)之间定位。
之后，如图3(b)所示，伸出电极6和平面电极未画出相互接触并经粘接工具14加压和加热。加热时各向异性导电粘接剂20会软化，其一部分以伸出方式从第一半导体芯片1挤出。由伸出树脂构成的支承部分21会膨胀，并很快与粘接工具14的吸面13接触。按此方式，用粘接工具14的吸面13使支承部分21的高度与第一半导体芯片1的背面相同。
而且，随着第一半导体芯片1和电路衬底3A之间的间隙变窄，各向异性导电粘接剂20与支承部分21之间的定位得到改进。因此，各向异性导电粘接剂20中的导电颗粒在伸出电极6与电路衬底3A的平面电极之间，因此，伸出电极6与平面电极之间构成导电。
关于各向导性导电粘接剂20可用例如Sony Chemical K.K.制造的各向导性导电粘接剂MJ932，该产品在约130℃软化有适当的流动性。
例如，假设第一半导体芯片1的尺寸是8.4×6.3mm2，厚度是0.2mm，那么，第二半导体芯片2的尺寸是10.4×8.3mm2，在认为电路衬底3A一侧上的不均匀性可以忽略不计并认为是平坦的情况下计算出的连接后的凸点高度(第一半导体芯片1的有源面与布线层4之间的距离)是0.025mm。因此，发现需用尺寸为9×7mm2、厚0.15mm左右的膜状各向异性导电粘接剂20。
按预定温度和压力加热加压向使支承部分21充分固定后，冷却粘接工具14，之后，将粘接工具14与第一半导体芯片1分开(见图3(c))。
假设第一半导体芯片1上形成的伸出电极6的数量是40，那么，第一半导体芯片1的尺寸应是8.4×6.3mm2，压力设定为10kgf/芯片，加热条件规定为约200℃时加热30秒。
这种情况下，当粘接工具14的吸面13上预定形成氟树脂涂膜时，则很容易把粘接工具14与支承部分21分开。关于氟树脂涂膜，例如可用NipponProton(k.k)制造的质子系统。
之后，如图4(a)所示，第二半导体芯片2粘接到第一半导体芯片1的背面。粘接剂7预先加到第二半导体芯片2的背面上，用该粘接剂7把第二半导体芯片2固定到第一半导体芯片1上。
关于粘接剂7，当第一半导体芯片1的支承衬底的电位与第二半导体芯片2的支承衬底的电位相同时，用导电粘接剂，当它们之间的电位不同时，用绝缘粘接剂。对膜的形状，无特殊限定，膏状和液体粘接剂都可用作粘接剂7。
之后，如图4(b)所示，用引线8使第二半导体芯片2的平面电极18与电路衬底3A相互连接。此时，由于平面电极18被支承部分21支承，因此，可以加足够的负荷和超声波，即使进行引线键合工艺时也不会损坏第二半导体芯片2。而且，在该情况下，当有热固性能的粘接树脂用作各向异性导电粘接剂20时，即使在加热和用超声波时也能稳定地支承第二半导体芯片2而不使树脂软化。
这里，本实施例中，用有CSP结构的半导体器件为例进行说明。但是，图5所示，上述安装可用于封装型半导体器件中，其中，第一半导体芯片1和第二半导体芯片2封装在例如母板的电路衬底3′上。
换言之，第一半导体芯片1和第二半导体芯片2叠置在电路衬底3′上并用树脂涂膜9覆盖。第一半导体芯片1和第二半导体芯片2分别用倒装接合法和引线键合连接到电路衬底3′。已形成在第二半导体芯片2的伸出部分上的平面电极18用各向异性导电粘接剂20的伸出树脂构成的支承部分21从下面支承。因此，即使在平面电极18上进行引线键合工艺，也能用足够的负荷和超声波，而不会因撞击和负荷造成第二半导体芯片2损坏。
如上所述，本实施例中，第一半导体芯片1倒装接合到电路衬底1上时，用各向异性导电粘接剂20，允许它的一部分在第一半导体芯片1与电路衬底3之间伸出。调节该伸出的粘接剂的高度，使其与第一半导体芯片1的背面高度相同，以构成支承部分21，该支承部分可以用于引线键合第二半导体芯片2的每个伸出部分上构成的平面电极18。
换言之，本发明涉及的半导体器件，它有经各向异性导电粘接剂20已倒装接合到电路衬底3上的第一半导体芯片1，和固定在第一半导体芯片1的背面并引线键合的第二半导体芯片2，其中，第二半导体芯片2的从第一半导体芯片1的外边缘伸出的每个伸出部分用从第一半导体芯片1伸出的粘接剂支承。
更具体地说，其上形成有伸出电极6的第一半导体芯片1经各向异性导电粘接剂20倒装接合到电路衬底3的同时，各向异性导电粘接剂20的一部分可在第一半导体芯片1与电路衬底3之间伸出，调节这样构成的支承部分21的高度，使其与第一半导体芯片1的背面相同。之后，进行以下工艺步骤：设置各向异性导电粘接剂20，第二半导体芯片2固定到第一半导体芯片1的背面上，并生成支承部分21，用引线键合连接第二半导体芯片2的平面电极18和电路衬底3的平面电极。
用该方案，当位于上面的第二半导体芯片2从位于下面的第一半导体芯片1伸出时，也能稳定地在伸出部分上形成的平面电极18上进行引线键合。
不用说，可采用位于上面的半导体芯片比位于下面的另一半导体芯片大的半导体芯片组合任何一种组合，例如必须会引起一个芯片以另一个芯片伸出的方形和矩形芯片组合和一个极小的芯片与另一芯片组合，而不会因为要叠置的半导体芯片的形状和尺寸的组合而带来影响，因此，能获得有高封装密度的半导体器件。
[例2]
参见图6(a)、6(b)、7(a)和7(b)，以下要说明本发明的另一实施例。为便于说明，与实施例1所述元件相同的元件用相同标号表示，在此省略不说。
本实施例中所述的半导体器件，与图1所示的实施例1中所述的CSP结构的半导体器件有相同的配置。
以下说明它的制造方法。
实施例1中，第一半导体芯片1安装到电路衬底3上并粘接之后，第二半导体芯片2安装并粘接到第一半导体芯片1上。但是，本实施例中，第二半导体芯片2和第一半导体芯片1预先相互粘接，因此，第一半导体芯片1和第二半导体芯片2粘接后装到电路衬底3上并粘接。
换言之，如图6(a)和6(b)所示，用粘接剂7粘接第一半导体芯片1和第二半导体芯片2。
图6(a)所示的情形是用膜形粘接剂7，图6(b)所示情形中用的粘接剂是膏状或液状或加热时可以流动的形状。
如图6(a)所示，膜状粘接剂7的情况下，用热压焊在其晶片状态下从晶片背面把膜状粘接剂7固定到第一半导体芯片1上。之后，切割成第一半导体芯片1，使粘接剂7固定到第一半导体芯片1的背面而不会脱落。而且，第二半导体芯片2的背面(在图6(a)的上边的面)用加预定的负荷热压到粘接剂7上。
而且，如图6(b)所示，当使用的粘接剂是膏状或液体或加热时可以流动的状态时，用分散器把适量的粘接剂7加到第二半导体芯片2的背面(图6(b)上侧的面)后，压到第一半导体芯片1的背面。之后，在预定加热条件下加热并固定粘接剂7。此时，粘接剂7是膏状或液体，或加热时可流动的状态时，第一半导体芯片1的四周边缘上形成凸台22。
如图7(a)所示，按该方式相到连接在一起的第一半导体芯片1和第二半导体芯片2与电路衬底3A面对面安装。该图展示出在第一半导体芯片1的四周边缘上有预先形成的凸台22的情形。
之后，如图7(b)所示，降低粘接工具14，使第一半导体芯片1上形成的伸出电极6与电路衬底3A的平面电极相互接触。而且，给它再加负荷，使第一半导体芯片1和电路衬底3A之间的距离逐渐变窄。各向异性导电粘接剂20喷在第一半导体芯片1的整个有源面上，多余的各向异性导电粘接剂20立即伸出到第一半导体芯片1的外边。由伸出树脂构成的支承部分21沿着第一半导体芯片1四周边缘膨胀，并与第二半导体芯片2的背面接触。
此后进行的工艺步骤与例1中的半导体器件的制造工艺相同，并引线键合第二半导体芯片2，用树脂伸出的固定料作为支承部分21，使用足够的负荷和超声波而不会损坏第二半导体芯片2。
按此方式，本实施例中，第一半导体芯片1倒装粘到电路衬底3之前，第一半导体芯片1和第二半导体芯片2相互粘接在一起，用第二半导体芯片2的伸出部分调节构成支承部分21的伸出粘接剂的高度使其与第一半导体芯片1的背面相同。
换言之，工艺步骤包括：其上形成有伸出电极6的第一半导体芯片1的背面与至少有一对侧边比第一半导体芯片1的侧边大的第二半导体导体芯片2的背面相互粘接；第一半导体芯片1的有源面与电路衬底3用各向异性导电粘接剂20的面对面地倒装接合，同时，使部分各向异性导电粘接剂20在第一半导体芯片1与电路衬底3之间伸出，以构成用于第二半导体芯片2部分的从第一半导体芯片1的外部边缘挤出的支承部分21；用引线键合连接第二半导体芯片2的平面电极18和电路衬底3的平面电极。
因此，由于支承部分21被第二半导体芯片2截断，它不与粘接工具14的吸面13接触。这就不必用任何方法来改善吸面13从支承部分21分开的性能，例如例1中所述制造方法中要求的在吸面13上形成氟树脂涂膜的方法，因此，可以避免成本增加。
而且，特别是如图7(b)所示，在第一半导体芯片1的四周边缘上预先形成凸台22时，可以使各向异性导电粘接剂20流动，使第一半导体芯片更平滑地粘接到电路衬底3A上。能有效地防止产生气泡，减少气泡，提高合格率。
[例3]
参见图8(a)，8(b)，9(a)和9(b)，本发明的又一实施例说明如下。为便于说明，与例1和例2中相同的零件用相同的标号表示。这里不再说明。
本例中所述的半导体器件与参考图5的例1中所述的封装型半导体器件的配置实质上是相同的。这里，在上述情形下，第一半导体芯片1与电路衬底3′之间在倒装接合时的电连接和它们之间的机械连接都只用各向异性导电粘接剂20作粘接剂；但是本实施例与它的不同之处是，只用焊料16作电连接，和用焊料16和粘接片23作机械连接。
制造方法几乎与例2的方法相同，只是在电路衬底3′的平面电极上加了焊料16，还加了粘接片23。
以下将说明本例的制造方法。
如图8(a)所示，在第一半导体芯片1粘接到电路衬底3′之前，焊料16和粘接片23预先加到电路衬底3′上。更具体地说，平面电极(没画出)放在例如母板的电路衬底3′的布线层4上，以Ag和Sn为主要成分的焊料16加到平面电极上。而且把热固性树脂制成的粘接片23放到电路衬底3′上使其覆盖平面电极。
粘接片23最好用以环氧树脂为主要成分的热固性粘接树脂材料，它在约100℃至150℃的温度范围内软化而具有流动性，但在超过约200℃时它会固化。例如，可用Nitto Denko(k.k.)等制造的PFM2100。
之后，如图8(b)所示，对所用的粘接工具14加压，使伸出电极6与电路衬底3′的平面电极相互接触。随后加热，使粘接片23流动而焊料16熔化，使Au制成的伸出电极6接合到焊料16上。加热加压预定时间而使粘接片23固化之后，冷却粘接工具14，完成伸出电极6与焊料16之间的焊料连接。
此时，用流出树脂构成的支承部分24，沿第一半导体芯片1的四周边缘膨胀，与第二半导体芯片2的背面接触。
之后，如图9(a)所示，用引线8使第二半导体芯片2的平面电极18和电路衬底3′的平面电极相互连接。
最后如图9(b)所示，用树脂涂膜9覆盖第一半导体芯片1、第二半导体芯片2、引线8和电路衬底3′。因此制成本例的封装型半导体器件。
这里，用以Sn和Pb为主要成分的焊料制成的焊料伸出电极代替第一半导体芯片1的Au制成的伸出电极6。关于焊料伸出电极的形成方法，用焊料引线的引线键合法进行改进后的焊丝凸点法，和用电镀法提供的方法是公知的。这种情况下，对电路衬底3′平面电极上表面镀敷Au。即用于电路衬底3′的焊丝材料是铜，Cu上镀Au或镀Ni之后，在其上再镀Au。
本发明的半导体器件的制造方法中，用已粘到第一半导体芯片的背面的第二半导体芯片将第一半导体芯片倒装接合到电路衬底，并用引线键合将第二半导体芯片焊接到电路衬底，当第二半导体芯片的外边缘中至少一侧从第一半导体芯片的外边缘伸出时，第一半导体芯片的外边缘倒装接合到电路衬底，第一半导体芯片与电路衬底之间的伸出粘接剂的一部分是插入第一半导体芯片与电路衬底之间的粘接剂，调节伸出粘接剂的高度使其与第一半导体芯片的背面相同，以构成用于半导体芯片伸出部分的支承部分。
按上述方法，当第二半导体芯片的外边缘的至少一侧从第一半导体芯片的外边缘伸出时，第一半导体芯片倒装接合到电路衬底上，用插入第一半导体芯片与电路衬底之间的粘接剂构成用于半导体芯片伸出部分的支承部分。
因此，即使在引线键合时给伸出部分上形成的电极加足够大的负荷和超声波，撞击和负荷也不会损坏第二半导体芯片。
用该方案，不用说可采用位于上面的半导体芯片比位于下面的半导体芯片大的半导体芯片组合，任何芯片组合，例如必须会有一个芯片从另一个芯片伸出的方形和矩形芯片的组合和一个极小的芯片与另一芯片的组合，即使放在上面的芯片较小时可能会使引线移动并与位于下面的半导体芯片短路的组合，都可采用，并且在封装时把极小的芯片放在下面的配置也不会出现任何问题。因此，为了具有高密度，半导体器件具有把多个半导体芯片堆叠的配置，它可以拓宽半导体器件的设计自由度。
而且，采用以下要说明的本发明的制造方法，调节第一半导体芯片倒装接合到电路衬底用的粘接剂量，用一简单工艺很容易地形成用于第二半导体芯片的伸出部分的支承部分，并容易保持支承部分的高度精度，不必设置新的分离件。
在倒装接合第一半导体芯片时，用吸附和支承第一半导体芯片的吸附支承部件的吸面可调节构成支承部分的伸出粘接剂的高度。
如果支承部分远低于第一半导体片的背面，它就不能稳定支承第二半导体芯片的伸出部分，相反，如果支承部分太高，它给出过大的负荷；因此，必须规定支承部分与第二半导体芯片的背面处于同一高度。
上述方法中，用吸附支承件从背面吸紧第一半导体芯片把第一半导体芯片倒装接合到电路衬底上，用该吸附支承的吸面把伸出的粘接剂高度调到与第一半导体芯片的背面一样高，因此，很容易调节构成支承部分的粘接剂高度，容易实现上述制造方法。
本发明的半导体器件的制造方法，可以处理吸附支承部件的吸面，以改善它从粘接剂脱离的性能。
上述方法中，为改善从粘接剂脱离特性而对吸附支承部件的吸面进行处理。在第一半导体芯片粘到电路衬底之后，使吸附支承部件容易从粘接剂脱离。例如，为提高从粘接剂脱离的性能，可形成氟树脂涂膜。
按本发明的半导体器件的制造方法中，第一半导体芯片倒装接合到电路衬底之前，第一半导体芯片与第二半导体芯片相互粘接，因此，用第二半导体芯片的伸出部分调节用作支承部分的伸出粘接剂的高度。
按上述方法，第一半导体芯片与第二半导体芯片预先相互粘接，因此，第一半导体芯片倒装接合到电路衬底时，用第二半导体芯片的伸出部分调节构成支承部分的伸出粘接剂的高度。因此，可以把伸出粘接剂容易地定位调节到与第一半导体芯片处于同一高度。也能在制造过程中对常用的接合夹具不用机械工艺。
本发明的半导体器件的制造方法中，为把第一半导体芯片和第二半导体芯片粘接，可用膏状、液体、或在加热时能流动的粘接剂，而且可在第一半导体四周边缘形成凸台。
按上述方法，由于用膏状、液体或加热时可流动的粘接剂使第一半导体芯片与第二半导体芯片相互粘接，并在第一半导体芯片四周边缘上形成凸台，因此，可以使挤出的粘接剂的流动更平滑，以便在随后的工艺中，第一半导体芯片倒装接合到电路芯片时使挤出的粘接剂伸出。能防止包含气泡，减少气泡，提高合格率。
本发明的半导体器件的制造方法中，热固性粘接剂可用作第一半导体芯片倒装粘接电路衬底时用的粘接剂。
按上述方法，第一半导体芯片倒装接合到电路衬底用的粘接剂可以具有热固特性，因此，支承件更耐热。因此，即使对由第二半导体芯片的支承部分支承的部分引线键合，引线键合所产生的热和超声波也不会使支承部分软化。因此，可以稳定地支承第二芯片，并随后进行更好的引线键合工艺。
本发明的半导体器件的制造方法中，第一半导体芯片用已粘在第一半导体芯片背面的第二半导体芯片倒装接合到电路衬底上，用引线键合把第二半导体芯片焊接到电路衬底。当第二半导体芯片的外边缘的至少一侧从第一半导体芯片的外边缘伸出时，第二半导体芯片的伸出部分下面的部分填入粘接第一半导体芯片和电路衬底的粘接剂。
上述方案中，由于位于上面的第二半导体芯片的从位于下面的第一半导体芯片伸出的部分之下的部分中填入用于把第一半导体芯片倒装接合到电路衬底的粘接剂。因此，在第二半导体芯片的伸出部分上构成的电极上能稳定地进行引线键合。
换言之，用上述配置，即使位于上面的第二半导体芯片的一部分从位于下面的第一半导体芯片伸出，也可以把电极放在伸出部分上。
随后，封装半导体器件中两片叠置的半导体芯片，可以用各种尺寸的半导体芯片组合，例如，用两个尺寸差别很大的一个方形芯片和一个矩形芯片组合。
因此，为了得到高密度，半导体器件中有将多个半导体芯片叠置的配置，它能拓宽半导体器件的设计自由度。
以上说明了本发明，显然，本发明还有各种形式的变化。这些变化不脱离发明的精神和范围，对本发明的技术人员而言，所有这些改进均包括在所附权利要求书范围内。

Claims (20)

1、一种半导体器件的制造方法，包括以下步骤：
a)给电路衬底(3)加粘接剂(20、23)，通过粘接剂(20、23)用倒装接合法将第一半导体芯片(1)连接到电路衬底(3)上；
b)有从第一半导体芯片(1)伸出的伸出部分的第二半导体芯片(2)用其已连接到第一半导体芯片(1)背面的背面，利用在伸出部分的引线键合，连接到电路衬底(3)上；和
c)用粘接剂(21、24)的一部分形成用于支承伸出部分的支承部分(21，24)。
2、按权利要求1的半导体器件的制造方法，其中，所述步骤a)包括以下步骤：
用吸附支承部件(14)的吸附面(13)吸附并支承第一半导体芯片(1)，由此支承第一半导体芯片(1)；
所述的步骤c)包括以下步骤：
用所述吸附面(13)调节支承部分(21、24)的高度使其与第一半导体芯片(1)背面的高度相同。
3、按权利要求2的半导体器件的制造方法，其中，对吸附支承部件(14)的吸附面(13)进行处理，以改善从粘接剂(20、24)脱离的性能。
4、按权利要求1的半导体器件的制造方法，其中，所述步骤c)包括以下步骤：
用第二半导体芯片(2)的所述伸出部分调节支承部分(21、24)的高度使其与第一半导体芯片1背面的高度相同。
5、按权利要求4的半导体器件的制造方法，还包括步骤d)：第一半导体芯片(1)和第二半导体芯片(2)相互粘接，并在第一半导体芯片(1)的四周边缘上形成凸台。
6、按权利要求5的半导体器件的制造方法，其中，在所述步骤d)中使用液体粘接剂。
7、按权利要求5的半导体器件的制造方法，其中，在所述步骤d)中使用加热时会流动的粘接剂。
8、按权利要求1的半导体器件的制造方法，其中，在所述步骤a)中使用热固性粘接剂。
9、一种半导体器件的制造方法，其中，第一半导体器件(1)用已连到第一半导体芯片(1)背面的第二半导体芯片(2)倒装接合到电路衬底(3)上，第二半导体芯片(2)用引线键合连到电路衬底(3)上；该方法包括以下步骤：
当第二半导体芯片(2)的外部边缘的至少一侧从第一半导体芯片(1)的外边缘伸出时，第一半导体芯片(1)倒装接合到电路衬底(3)时，将第一半导体芯片(1)与电路衬底(3)之间的粘接剂(20、23)插入第一半导体芯片(1)与电路衬底(3)之间，而一部分粘接剂(20、23)伸出；和
调节伸出粘接剂的高度，使其与第一半导体芯片背面(1)的高度相同，以形成用于第二半导体芯片(2)的伸出部分的支承部分(21、24)。
10、按权利要求9的半导体器件的制造方法，其中，利用在倒装接合第一半导体芯片(1)时吸附并支承第一半导体芯片(1)的吸附支承部件(14)的吸附面(13)来调节形成支承部分(21、24)的伸出粘接剂的高度。
11、按权利要求10的半导体器件的制造方法，其中，对吸附支承部件(14)的吸附面(13)进行处理，以改善从粘接剂(20、23)脱离的性能。
12、按权利要求9的半导体器件的制造方法，其中，第一半导体芯片(1)倒装接合到电路衬底(3)之前，第一半导体芯片(1)和第二半导体芯片(2)相互粘接，以便用第二半导体芯片(2)的伸出部分调节用作支承部件(21、24)的伸出粘接剂的高度。
13、按权利要求12的半导体器件的制造方法，其中，用膏状或液体状或者加热时能流动的粘接剂粘接第一半导体芯片(1)和第二半导体芯片(2)，并在第一半导体芯片(1)的四周边缘上形成凸台。
14、按权利要求9的半导体器件的制造方法，其中，用热固性粘接剂作为第一半导体芯片(1)倒装接合到电路衬底(3)上的粘接剂(20、23)。
15、一种半导体器件的制造方法，包括以下步骤：
用粘接剂(20、23)将其上形成有伸出电极(6)的第一半导体芯片(1)倒装接合到电路衬底(3)时，使粘接剂(20、23)的一部分在第一半导体芯片(1)与电路衬底(3)之间伸出，并调节构成的支承部分(21、24)的高度，使其与第一半导体芯片(1)的背面高度相同，之后，固化粘接剂(20、23)；
将第二半导体芯片(2)固定到第一半导体芯片(1)的背面并构成支承部件(21、24)；和
用引线键合连接第二半导体芯片(2)的平面电极(18)和电路衬底(3)的平面电极。
16、一种半导体器件的制造方法，包括以下步骤：
连接其上形成有伸出电极(6)的第一半导体芯片(1)的背面和其中至少一对边比第一半导体芯片(1)的边大的第二半导体芯片(2)的背面；
用粘接剂(20、23)使相互面对面对准地倒装接合第一半导体芯片(1)的有源面和电路衬底(3)时，使粘接剂(20、23)的一部分在第一半导体芯片(1)与电路衬底(3)之间伸出，以构成从第一半导体芯片(1)的四周边缘挤出的用于第二半导体芯片(2)的支承部分(21、24)；和
用引线键合连接第二半导体芯片(2)的平面电极(18)和电路衬底(3)的平面电极。
17、按权利要求15或16的半导体器件的制造方法，其中，用各向异性导电粘接剂作为所述粘接剂(20、23)。
18、一种半导体器件，包括：
利用粘接剂(20、23)将其有源面对着电路衬底(3)从而连接到电路衬底(3)上的第一半导体芯片(1)；
有从第一半导体芯片(1)挤出的伸出部分、用其背面粘接到第一半导体芯片(1)的背面、伸出部分用引线连接到电路衬底(3)的第二半导体芯片(2)；和
用粘接剂(20、23)的一部分构成的用于支承伸出部分的支承部分(21、24)。
19、一种半导体器件，包括：
第一半导体芯片(1)，它用已与第一半导体芯片(1)的背面粘接的第二半导体芯片(2)倒装接合到电路衬底(3)上，而第二半导体芯片(2)用引线键合连接到电路衬底(3)上；
其中，第二半导体芯片(2)的外边缘的至少一边从第一半导体芯片(1)的外边缘伸出，第二半导体芯片(2)的伸出部分下面的部分用粘接第一半导体芯片(1)和电路衬底(3)的粘接剂(21，24)填充。
20、按权利要求18或19的半导体器件，其中，用各向异性导电粘接剂作为所述粘接剂(20、23)。
CNB001068903A 1999-04-14 2000-03-07 半导体器件及其制造方法 Expired - Lifetime CN1161834C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP107106/1999 1999-04-14
JP10710699A JP3565319B2 (ja) 1999-04-14 1999-04-14 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
CN1270417A true CN1270417A (zh) 2000-10-18
CN1161834C CN1161834C (zh) 2004-08-11

Family

ID=14450628

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB001068903A Expired - Lifetime CN1161834C (zh) 1999-04-14 2000-03-07 半导体器件及其制造方法

Country Status (6)

Country Link
US (1) US6353263B1 (zh)
EP (1) EP1045443A3 (zh)
JP (1) JP3565319B2 (zh)
KR (1) KR100356771B1 (zh)
CN (1) CN1161834C (zh)
TW (1) TW447110B (zh)

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1317761C (zh) * 2003-06-18 2007-05-23 财团法人工业技术研究院 覆晶封装接合结构及其制造方法
CN100373616C (zh) * 2002-11-07 2008-03-05 夏普株式会社 半导体装置及其制造方法
CN100401515C (zh) * 2004-11-19 2008-07-09 矽品精密工业股份有限公司 包覆有倒装芯片封装件的半导体装置及其制法
CN100423258C (zh) * 2003-01-29 2008-10-01 松下电器产业株式会社 半导体器件及其制造方法
CN100539129C (zh) * 2004-05-10 2009-09-09 台湾积体电路制造股份有限公司 半导体封装体及其制造方法
US7629695B2 (en) 2004-05-20 2009-12-08 Kabushiki Kaisha Toshiba Stacked electronic component and manufacturing method thereof
CN101552214B (zh) * 2008-04-02 2011-03-23 力成科技股份有限公司 节约打线工序的多芯片堆叠方法与构造
CN101295710B (zh) * 2004-05-20 2011-04-06 株式会社东芝 半导体器件
CN102117798A (zh) * 2009-12-31 2011-07-06 海力士半导体有限公司 堆叠封装
CN102576704A (zh) * 2009-09-08 2012-07-11 住友电木株式会社 半导体装置
CN101378051B (zh) * 2007-08-27 2012-10-10 富士通半导体股份有限公司 半导体器件及其制造方法
CN102931148A (zh) * 2011-08-10 2013-02-13 三星电机株式会社 半导体封装基板
CN104064479A (zh) * 2013-03-22 2014-09-24 瑞萨电子株式会社 制造半导体装置的方法和半导体装置
CN104183555A (zh) * 2013-05-28 2014-12-03 矽品精密工业股份有限公司 半导体封装件及其制法
CN104637908A (zh) * 2013-11-14 2015-05-20 三星电子株式会社 半导体封装件和制造半导体封装件的方法
CN109314062A (zh) * 2016-05-31 2019-02-05 株式会社新川 管芯的安装方法
CN112466828A (zh) * 2019-09-06 2021-03-09 铠侠股份有限公司 半导体装置

Families Citing this family (115)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001018864A1 (fr) * 1999-09-03 2001-03-15 Seiko Epson Corporation Dispositif a semi-conducteurs, son procede de fabrication, carte de circuit et dispositif electronique
JP2007150346A (ja) * 1999-09-03 2007-06-14 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
NO20001360D0 (no) * 2000-03-15 2000-03-15 Thin Film Electronics Asa Vertikale elektriske forbindelser i stabel
EP1139411A1 (de) * 2000-03-29 2001-10-04 Infineon Technologies AG Flip-chip Halbleiter-Anordnung mit Rückseiten-Kontaktierung
JP2001320014A (ja) * 2000-05-11 2001-11-16 Seiko Epson Corp 半導体装置及びその製造方法
JP3581086B2 (ja) 2000-09-07 2004-10-27 松下電器産業株式会社 半導体装置
JP3683179B2 (ja) * 2000-12-26 2005-08-17 松下電器産業株式会社 半導体装置及びその製造方法
JP2002204053A (ja) * 2001-01-04 2002-07-19 Mitsubishi Electric Corp 回路実装方法、回路実装基板及び半導体装置
JP2002222889A (ja) * 2001-01-24 2002-08-09 Nec Kyushu Ltd 半導体装置及びその製造方法
JP3839323B2 (ja) 2001-04-06 2006-11-01 株式会社ルネサステクノロジ 半導体装置の製造方法
KR100720408B1 (ko) * 2001-05-04 2007-05-22 앰코 테크놀로지 코리아 주식회사 이방성 도전필름을 이용한 플립칩 본딩장치 및 플립칩본딩방법
EP1401020A4 (en) * 2001-06-07 2007-12-19 Renesas Tech Corp SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
JP4633971B2 (ja) * 2001-07-11 2011-02-16 ルネサスエレクトロニクス株式会社 半導体装置
US7176506B2 (en) * 2001-08-28 2007-02-13 Tessera, Inc. High frequency chip packages with connecting elements
US6856007B2 (en) * 2001-08-28 2005-02-15 Tessera, Inc. High-frequency chip packages
DE10142114C1 (de) * 2001-08-30 2003-02-13 Infineon Technologies Ag Elektronisches Bauteil mit wenigstens zwei Halbleiterchips sowie Verfahren zu seiner Herstellung
JP2003086734A (ja) * 2001-09-12 2003-03-20 Nec Corp Ｃｓｐのチップスタック構造
US6514795B1 (en) * 2001-10-10 2003-02-04 Micron Technology, Inc. Packaged stacked semiconductor die and method of preparing same
JP3727587B2 (ja) * 2001-12-28 2005-12-14 シャープ株式会社 半導体装置の実装方法
JP2003204039A (ja) * 2002-01-04 2003-07-18 Mitsubishi Electric Corp 半導体装置
TW529141B (en) * 2002-01-07 2003-04-21 Advanced Semiconductor Eng Stacking type multi-chip package and its manufacturing process
US6867500B2 (en) * 2002-04-08 2005-03-15 Micron Technology, Inc. Multi-chip module and methods
JP2003318360A (ja) * 2002-04-19 2003-11-07 Hitachi Ltd 半導体装置およびその製造方法
US6809416B1 (en) * 2002-05-28 2004-10-26 Intersil Corporation Package for integrated circuit with thermal vias and method thereof
CN100333813C (zh) 2002-05-31 2007-08-29 马特尔公司 可变形的玩偶和可摆姿势的动作人物造型
DE10244664A1 (de) * 2002-09-24 2004-04-01 Infineon Technologies Ag Elektronisches Bauteil mit Halbleiterchips in einem Stapel und Verfahren zur Herstellung desselben
US6825064B2 (en) * 2002-09-30 2004-11-30 Ultratera Corporation Multi-chip semiconductor package and fabrication method thereof
TWI322448B (en) * 2002-10-08 2010-03-21 Chippac Inc Semiconductor stacked multi-package module having inverted second package
KR100618812B1 (ko) * 2002-11-18 2006-09-05 삼성전자주식회사 향상된 신뢰성을 가지는 적층형 멀티 칩 패키지
KR100876876B1 (ko) * 2002-12-03 2008-12-31 주식회사 하이닉스반도체 칩 스택 패키지
JP3566957B2 (ja) * 2002-12-24 2004-09-15 沖電気工業株式会社 半導体装置及びその製造方法
JP3689694B2 (ja) * 2002-12-27 2005-08-31 松下電器産業株式会社 半導体装置及びその製造方法
JP4504204B2 (ja) * 2003-02-25 2010-07-14 テッセラ，インコーポレイテッド 接続要素を有する高周波チップパッケージ
AU2003219633A1 (en) 2003-02-27 2004-09-17 Infineon Technologies Ag Integrated circuit package and method for producing it
TWI220781B (en) * 2003-04-28 2004-09-01 Advanced Semiconductor Eng Multi-chip package substrate for flip-chip and wire bonding
KR101078621B1 (ko) * 2003-07-03 2011-11-01 테쎄라 테크놀로지스 아일랜드 리미티드 집적회로 디바이스를 패키징하기 위한 방법 및 장치
JP3718205B2 (ja) * 2003-07-04 2005-11-24 松下電器産業株式会社 チップ積層型半導体装置およびその製造方法
WO2005031861A1 (en) * 2003-09-26 2005-04-07 Tessera, Inc. Structure and method of making capped chips including a flowable conductive medium
US20050067681A1 (en) * 2003-09-26 2005-03-31 Tessera, Inc. Package having integral lens and wafer-scale fabrication method therefor
JP4381779B2 (ja) * 2003-11-17 2009-12-09 株式会社ルネサステクノロジ マルチチップモジュール
US20050139984A1 (en) * 2003-12-19 2005-06-30 Tessera, Inc. Package element and packaged chip having severable electrically conductive ties
US20050191936A1 (en) * 2004-01-07 2005-09-01 Marine Jon C. Doll
JP2005197491A (ja) * 2004-01-08 2005-07-21 Matsushita Electric Ind Co Ltd 半導体装置
DE102004005586B3 (de) * 2004-02-04 2005-09-29 Infineon Technologies Ag Halbleiterbauteil mit einem Halbleiterchipstapel auf einer Umverdrahtungsplatte und Herstellung desselben
US20050189622A1 (en) * 2004-03-01 2005-09-01 Tessera, Inc. Packaged acoustic and electromagnetic transducer chips
US7183651B1 (en) 2004-06-15 2007-02-27 Storage Technology Corporation Power plane decoupling
TWI249796B (en) * 2004-11-08 2006-02-21 Siliconware Precision Industries Co Ltd Semiconductor device having flip chip package
US8143095B2 (en) * 2005-03-22 2012-03-27 Tessera, Inc. Sequential fabrication of vertical conductive interconnects in capped chips
JP2006310649A (ja) * 2005-04-28 2006-11-09 Sharp Corp 半導体装置パッケージおよびその製造方法、ならびに半導体装置パッケージ用一括回路基板
TWI286805B (en) * 2005-08-18 2007-09-11 Advanced Semiconductor Eng Chip package and package process thereof
US7485969B2 (en) * 2005-09-01 2009-02-03 Micron Technology, Inc. Stacked microelectronic devices and methods for manufacturing microelectronic devices
JP2007103737A (ja) * 2005-10-05 2007-04-19 Sharp Corp 半導体装置
US7342308B2 (en) * 2005-12-20 2008-03-11 Atmel Corporation Component stacking for integrated circuit electronic package
US7936062B2 (en) * 2006-01-23 2011-05-03 Tessera Technologies Ireland Limited Wafer level chip packaging
US20070190747A1 (en) * 2006-01-23 2007-08-16 Tessera Technologies Hungary Kft. Wafer level packaging to lidded chips
US8120156B2 (en) * 2006-02-17 2012-02-21 Stats Chippac Ltd. Integrated circuit package system with die on base package
SG135066A1 (en) 2006-02-20 2007-09-28 Micron Technology Inc Semiconductor device assemblies including face-to-face semiconductor dice, systems including such assemblies, and methods for fabricating such assemblies
US20080002460A1 (en) * 2006-03-01 2008-01-03 Tessera, Inc. Structure and method of making lidded chips
JP2007266111A (ja) * 2006-03-27 2007-10-11 Sharp Corp 半導体装置、それを用いた積層型半導体装置、ベース基板、および半導体装置の製造方法
US8460970B1 (en) 2006-04-28 2013-06-11 Utac Thai Limited Lead frame ball grid array with traces under die having interlocking features
US8492906B2 (en) * 2006-04-28 2013-07-23 Utac Thai Limited Lead frame ball grid array with traces under die
US8461694B1 (en) 2006-04-28 2013-06-11 Utac Thai Limited Lead frame ball grid array with traces under die having interlocking features
US8487451B2 (en) * 2006-04-28 2013-07-16 Utac Thai Limited Lead frame land grid array with routing connector trace under unit
US8310060B1 (en) * 2006-04-28 2012-11-13 Utac Thai Limited Lead frame land grid array
US8013437B1 (en) 2006-09-26 2011-09-06 Utac Thai Limited Package with heat transfer
US8125077B2 (en) * 2006-09-26 2012-02-28 Utac Thai Limited Package with heat transfer
US9711343B1 (en) 2006-12-14 2017-07-18 Utac Thai Limited Molded leadframe substrate semiconductor package
US9761435B1 (en) 2006-12-14 2017-09-12 Utac Thai Limited Flip chip cavity package
JP2008166438A (ja) * 2006-12-27 2008-07-17 Spansion Llc 半導体装置およびその製造方法
US8604605B2 (en) 2007-01-05 2013-12-10 Invensas Corp. Microelectronic assembly with multi-layer support structure
JP2008211125A (ja) * 2007-02-28 2008-09-11 Spansion Llc 半導体装置およびその製造方法
JP2009058244A (ja) * 2007-08-30 2009-03-19 Nippon Seiki Co Ltd 表示装置及び表示装置用表示板の組み付け方法
JP5529371B2 (ja) 2007-10-16 2014-06-25 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及びその製造方法
US7906860B2 (en) * 2007-10-26 2011-03-15 Infineon Technologies Ag Semiconductor device
US7790512B1 (en) 2007-11-06 2010-09-07 Utac Thai Limited Molded leadframe substrate semiconductor package
US8063470B1 (en) 2008-05-22 2011-11-22 Utac Thai Limited Method and apparatus for no lead semiconductor package
US7956449B2 (en) * 2008-06-25 2011-06-07 Stats Chippac Ltd. Stacked integrated circuit package system
US8923004B2 (en) * 2008-07-31 2014-12-30 Micron Technology, Inc. Microelectronic packages with small footprints and associated methods of manufacturing
JP2010040835A (ja) * 2008-08-06 2010-02-18 Toshiba Corp 積層型半導体装置の製造方法
US9947605B2 (en) * 2008-09-04 2018-04-17 UTAC Headquarters Pte. Ltd. Flip chip cavity package
US8022539B2 (en) * 2008-11-17 2011-09-20 Stats Chippac Ltd. Integrated circuit packaging system with increased connectivity and method of manufacture thereof
US8569877B2 (en) * 2009-03-12 2013-10-29 Utac Thai Limited Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide
US20100327419A1 (en) 2009-06-26 2010-12-30 Sriram Muthukumar Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
US9449900B2 (en) * 2009-07-23 2016-09-20 UTAC Headquarters Pte. Ltd. Leadframe feature to minimize flip-chip semiconductor die collapse during flip-chip reflow
US9355940B1 (en) 2009-12-04 2016-05-31 Utac Thai Limited Auxiliary leadframe member for stabilizing the bond wire process
US8368189B2 (en) * 2009-12-04 2013-02-05 Utac Thai Limited Auxiliary leadframe member for stabilizing the bond wire process
US8541886B2 (en) * 2010-03-09 2013-09-24 Stats Chippac Ltd. Integrated circuit packaging system with via and method of manufacture thereof
US8575732B2 (en) * 2010-03-11 2013-11-05 Utac Thai Limited Leadframe based multi terminal IC package
US8871571B2 (en) 2010-04-02 2014-10-28 Utac Thai Limited Apparatus for and methods of attaching heat slugs to package tops
JP5453678B2 (ja) * 2010-06-29 2014-03-26 新光電気工業株式会社 半導体パッケージおよびその製造方法
JP2012049175A (ja) * 2010-08-24 2012-03-08 Toshiba Corp 半導体装置の製造方法
KR20120062366A (ko) * 2010-12-06 2012-06-14 삼성전자주식회사 멀티칩 패키지의 제조 방법
US9721872B1 (en) * 2011-02-18 2017-08-01 Amkor Technology, Inc. Methods and structures for increasing the allowable die size in TMV packages
WO2013007029A1 (en) * 2011-07-14 2013-01-17 Sandisk Semiconductor (Shanghai) Co., Ltd. Chip-on-package structure for multiple die stacks
JP5721593B2 (ja) * 2011-09-12 2015-05-20 積水化学工業株式会社 接続構造体の製造方法
KR20130105175A (ko) * 2012-03-16 2013-09-25 삼성전자주식회사 보호 층을 갖는 반도체 패키지 및 그 형성 방법
KR101906269B1 (ko) 2012-04-17 2018-10-10 삼성전자 주식회사 반도체 패키지 및 그 제조 방법
US9449905B2 (en) 2012-05-10 2016-09-20 Utac Thai Limited Plated terminals with routing interconnections semiconductor device
US9029198B2 (en) 2012-05-10 2015-05-12 Utac Thai Limited Methods of manufacturing semiconductor devices including terminals with internal routing interconnections
JP5980566B2 (ja) 2012-05-17 2016-08-31 新光電気工業株式会社 半導体装置及びその製造方法
US9006034B1 (en) 2012-06-11 2015-04-14 Utac Thai Limited Post-mold for semiconductor package having exposed traces
WO2014041684A1 (ja) 2012-09-14 2014-03-20 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
KR102041502B1 (ko) 2013-04-01 2019-11-07 삼성전자 주식회사 관통 전극 및 접착 층을 갖는 반도체 패키지
KR102116987B1 (ko) 2013-10-15 2020-05-29 삼성전자 주식회사 반도체 패키지
US10242934B1 (en) 2014-05-07 2019-03-26 Utac Headquarters Pte Ltd. Semiconductor package with full plating on contact side surfaces and methods thereof
KR102245003B1 (ko) 2014-06-27 2021-04-28 삼성전자주식회사 오버행을 극복할 수 있는 반도체 패키지 및 그 제조방법
JP2016048756A (ja) 2014-08-28 2016-04-07 マイクロン テクノロジー， インク． 半導体装置
JP2015046643A (ja) * 2014-12-10 2015-03-12 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置
US10269686B1 (en) 2015-05-27 2019-04-23 UTAC Headquarters PTE, LTD. Method of improving adhesion between molding compounds and an apparatus thereof
US9917038B1 (en) 2015-11-10 2018-03-13 Utac Headquarters Pte Ltd Semiconductor package with multiple molding routing layers and a method of manufacturing the same
DE112016006704T5 (de) * 2016-04-02 2018-12-13 Intel Corporation Halbleiterbaugruppe mit abgestütztem gestapeltem Halbleiterplättchen
US10276477B1 (en) 2016-05-20 2019-04-30 UTAC Headquarters Pte. Ltd. Semiconductor package with multiple stacked leadframes and a method of manufacturing the same
CN110914982A (zh) * 2017-02-10 2020-03-24 微芯片技术股份有限公司 背面偏置式半导体管芯的接地技术以及相关的设备、系统和方法
JP6906228B2 (ja) * 2017-08-18 2021-07-21 ナミックス株式会社 半導体装置
CN110233113A (zh) * 2019-06-17 2019-09-13 青岛歌尔微电子研究院有限公司 一种芯片的封装方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5731166A (en) * 1980-07-31 1982-02-19 Fujitsu Ltd Semiconductor device
JPS6384128A (ja) * 1986-09-29 1988-04-14 Oki Electric Ind Co Ltd 混成集積回路装置
JPH0456262A (ja) * 1990-06-25 1992-02-24 Matsushita Electron Corp 半導体集積回路装置
JPH0499056A (ja) * 1990-08-06 1992-03-31 Seiko Epson Corp 複合集積回路チップ
JPH0547998A (ja) * 1991-08-21 1993-02-26 Sony Corp 高密度実装化半導体装置
JPH05343609A (ja) * 1992-06-04 1993-12-24 Nec Corp 半導体集積回路装置
JP3186236B2 (ja) * 1992-08-25 2001-07-11 松下電器産業株式会社 半導体装置の製造方法
US5721452A (en) * 1995-08-16 1998-02-24 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
US6096576A (en) * 1997-09-02 2000-08-01 Silicon Light Machines Method of producing an electrical interface to an integrated circuit device having high density I/O count
US6300686B1 (en) * 1997-10-02 2001-10-09 Matsushita Electric Industrial Co., Ltd. Semiconductor chip bonded to a thermal conductive sheet having a filled through hole for electrical connection
JPH11219984A (ja) * 1997-11-06 1999-08-10 Sharp Corp 半導体装置パッケージおよびその製造方法ならびにそのための回路基板
WO2001018864A1 (fr) * 1999-09-03 2001-03-15 Seiko Epson Corporation Dispositif a semi-conducteurs, son procede de fabrication, carte de circuit et dispositif electronique

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100373616C (zh) * 2002-11-07 2008-03-05 夏普株式会社 半导体装置及其制造方法
CN100423258C (zh) * 2003-01-29 2008-10-01 松下电器产业株式会社 半导体器件及其制造方法
CN1317761C (zh) * 2003-06-18 2007-05-23 财团法人工业技术研究院 覆晶封装接合结构及其制造方法
CN100539129C (zh) * 2004-05-10 2009-09-09 台湾积体电路制造股份有限公司 半导体封装体及其制造方法
US8268673B2 (en) 2004-05-20 2012-09-18 Kabushiki Kaisha Toshiba Stacked electronic component and manufacturing method thereof
US7629695B2 (en) 2004-05-20 2009-12-08 Kabushiki Kaisha Toshiba Stacked electronic component and manufacturing method thereof
CN101295710B (zh) * 2004-05-20 2011-04-06 株式会社东芝 半导体器件
US9024424B2 (en) 2004-05-20 2015-05-05 Kabushiki Kaisha Toshiba Stacked electronic component and manufacturing method thereof
US8008763B2 (en) 2004-05-20 2011-08-30 Kabushiki Kaisha Toshiba Stacked electronic component and manufacturing method thereof
CN100401515C (zh) * 2004-11-19 2008-07-09 矽品精密工业股份有限公司 包覆有倒装芯片封装件的半导体装置及其制法
CN101378051B (zh) * 2007-08-27 2012-10-10 富士通半导体股份有限公司 半导体器件及其制造方法
CN101552214B (zh) * 2008-04-02 2011-03-23 力成科技股份有限公司 节约打线工序的多芯片堆叠方法与构造
CN102576704A (zh) * 2009-09-08 2012-07-11 住友电木株式会社 半导体装置
CN102117798A (zh) * 2009-12-31 2011-07-06 海力士半导体有限公司 堆叠封装
CN102117798B (zh) * 2009-12-31 2015-07-29 海力士半导体有限公司 堆叠封装
CN102931148B (zh) * 2011-08-10 2015-06-03 三星电机株式会社 半导体封装基板
CN102931148A (zh) * 2011-08-10 2013-02-13 三星电机株式会社 半导体封装基板
CN104064479A (zh) * 2013-03-22 2014-09-24 瑞萨电子株式会社 制造半导体装置的方法和半导体装置
CN104183555A (zh) * 2013-05-28 2014-12-03 矽品精密工业股份有限公司 半导体封装件及其制法
CN104183555B (zh) * 2013-05-28 2018-09-07 矽品精密工业股份有限公司 半导体封装件及其制法
CN104637908A (zh) * 2013-11-14 2015-05-20 三星电子株式会社 半导体封装件和制造半导体封装件的方法
CN109314062A (zh) * 2016-05-31 2019-02-05 株式会社新川 管芯的安装方法
CN109314062B (zh) * 2016-05-31 2022-04-29 株式会社新川 管芯的安装方法
CN112466828A (zh) * 2019-09-06 2021-03-09 铠侠股份有限公司 半导体装置
CN112466828B (zh) * 2019-09-06 2024-01-30 铠侠股份有限公司 半导体装置

Also Published As

Publication number Publication date
JP2000299431A (ja) 2000-10-24
US6353263B1 (en) 2002-03-05
EP1045443A3 (en) 2004-01-21
JP3565319B2 (ja) 2004-09-15
KR20000076778A (ko) 2000-12-26
KR100356771B1 (ko) 2002-10-18
CN1161834C (zh) 2004-08-11
EP1045443A2 (en) 2000-10-18
TW447110B (en) 2001-07-21

Similar Documents

Publication Publication Date Title
CN1161834C (zh) 半导体器件及其制造方法
CN1229863C (zh) 半导体装置及其制造方法、电路基板和电子装置
CN1235286C (zh) 一种电子装置与制作此装置的方法
CN1265455C (zh) 半导体器件及其制造方法
CN1171298C (zh) 半导体器件
CN1280884C (zh) 半导体装置及其制造方法、电路板以及电子机器
CN1271712C (zh) 具有从密封树脂暴露出来的散热器的半导体器件
CN1291467C (zh) 电子器件的制造方法
CN1779951A (zh) 半导体器件及其制造方法
CN1516898A (zh) 半导体装置及其制造方法
CN1790651A (zh) 芯片集成基板的制造方法
CN1723556A (zh) 可叠置的半导体器件及其制造方法
CN1828880A (zh) 用于指纹识别的半导体装置
CN1449232A (zh) 电路部件内装模块及其制造方法
CN1700466A (zh) 半导体封装体及其形成方法
CN1338779A (zh) 半导体器件
CN1591861A (zh) 电路元件内置模块及其制造方法
CN1641832A (zh) 半导体器件及其制造方法
CN1702857A (zh) 半导体器件及其制造方法
CN1622328A (zh) 半导体器件及其制造方法
CN1185698C (zh) 半导体装置及其制造方法、电路板以及电子设备
CN1532932A (zh) 半导体装置及其制造方法、电子设备、电子仪器
CN1476100A (zh) 摄像机模块及其制造方法
CN1459855A (zh) 半导体器件及其制造方法
CN1574346A (zh) 一种制造半导体器件的方法

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
C14 Grant of patent or utility model
GR01 Patent grant
C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20161207

Address after: Delaware

Patentee after: III Holding 10 limited liability company

Address before: Osaka, Japan

Patentee before: sharp corporation

CX01 Expiry of patent term
CX01 Expiry of patent term

Granted publication date: 20040811