CN1267396A - 多芯片组件构造体及其制造方法 - Google Patents

多芯片组件构造体及其制造方法 Download PDF

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CN1267396A
CN1267396A CN98808253A CN98808253A CN1267396A CN 1267396 A CN1267396 A CN 1267396A CN 98808253 A CN98808253 A CN 98808253A CN 98808253 A CN98808253 A CN 98808253A CN 1267396 A CN1267396 A CN 1267396A
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mentioned
interarea
substrate
bare chip
recess
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CN1167131C (zh
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关根健治
山田宏治
山崎松夫
加贺谷修
山下喜市
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Hitachi Ltd
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Hitachi Ltd
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Priority claimed from JP25958997A external-priority patent/JP3840761B2/ja
Priority claimed from JP6972798A external-priority patent/JP3815033B2/ja
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Abstract

一种装载有多个半导体裸芯片器件的基底金属基板,具有第1和第2主面,在第1主面上形成了至少一个凸部和用来决定裸芯片器件的装载位置的至少2个凹部。凹部的深度比凸部的长度大且具有比金属基板的主面更好的平滑度。金属基板被部分地进行化学刻蚀以形成凸部,同时还进行机械加工以形成第1主面。导电性的凸部与已装载上裸芯片器件的基板的部分进行隔离,在基底基板的第1和第2主面一侧,用做用来进行电连的外部端子。

Description

多芯片组件构造体及其制造方法
技术领域
本发明涉及把多个裸半导体芯片器件和至少一个导电性接线端子装配到基底基板上边构成的多芯片组件构造体及其制造方法。
作为电子装置小型化和高性能化的一个手段，有使裸半导体芯片和无源元件多个相互连接变成为一个组件的所谓多芯片组件。
现有的裸半导体芯片的装配方法的一例，如日本特开平3-155144(1991年7月3日公开)所示，在由裸半导体IC芯片的厚度规定的量那么厚的绝缘薄膜上，预先形成由半导体裸IC芯片的外形尺寸规定的量那么大的穴，中间介有粘接剂地把绝缘薄膜粘贴到支持板上，再中间介有粘接剂地把上述裸半导体IC芯片粘接到上述粘贴绝缘薄膜的穴部内，用与绝缘薄膜同种的液态树脂涂敷裸半导体芯片与绝缘薄膜的空隙和裸半导体IC芯片的表面，使得高度变成为与绝缘薄膜层均一之后，进行热硬化，在用光刻法除去了裸半导体IC芯片焊盘上边的树脂之后，在整个面上形成导体膜，再用光刻法进行规定的导体布线的形成。
此外，现有的半导体装置(特别是多芯片组件)及其制造方法的一例，如特开平5-47856(1993年2月26日公开)所示，其构成如下：把芯片装配到已设置到封装上的至少一个载物台上，把绝缘膜涂敷到上述封装和芯片上，在上述绝缘膜上设置与上述封装上边的连接焊盘和上述芯片上边的焊盘导通的通孔，用布线图形连接上述通孔。
在特开平3-155144和特开平5-47856的实施例中，支持板或封装由绝缘基板构成，一般说绝缘基板的材料与导电材料和半导体材料比，热导率要低一个数量级以上，故对于功耗大的功率放大器等的装配是不合适的。
此外，特开平5-47856的实施例中，在芯片背面的装配用导体层(例如Au-Sn共晶或导电性粘接剂)和绝缘薄膜上边的导电布线之间没有电性接合。
再有，在特开平3-155144中所示的现有的裸半导体芯片的装配方法的一例中，在用与绝缘薄膜同种的液态树脂涂敷裸半导体芯片与绝缘薄膜的空隙和裸半导体IC芯片的表面，使得高度变成为与绝缘薄膜层均一之后，在进行热硬化的工序中，有时候会因为热硬化时的液态树脂的收缩，在裸半导体IC芯片与绝缘薄膜间的空隙中产生凹坑。当在上述空隙部分处产生了凹坑时，则有时候会在上述空隙部分的导体布线上产生短路或断线等。
另外，在特开平5-47856中所示的半导体装置及其制造方法的一例中，在液态树脂的热硬化工序中，有时候也会因为热硬化时的收缩，在封装和芯片间的空隙部分的绝缘膜上产生凹坑。该凹坑有时候也会在上述空隙部分的布线图形上产生短路或断线等的不合格。
作为解决这些问题的一个手段，有一种芯片埋入式多芯片组件。该方法在金属基底基板上预先设置多个凹凸，接着，用树脂状的绝缘膜进行覆盖，以便把上述裸半导体芯片埋进去，再用研削等进行平坦加工，使得上述绝缘膜和上述裸半导体芯片上边的焊料凸点电极变成为规定的同一高度，再在其上边设置薄膜无源部件的同时，用金属层和绝缘膜设置多层布线。但是，该方法的课题是不能在基底基板上容易地制作所希望的凹凸。
再有，若使用现有例，则不能变成为可以以多芯片组件构造体单位装配管帽的构造。因此，对于来自外部的损伤不能形成机械性的保护而易于破损。此外，在使之在高频区域动作的情况下，电磁屏蔽减弱，易受来自别处的干扰。
发明的公开
若根据本发明的一个侧面，用来装载多个半导体芯片装置的基底基板，具备第1和第2主面，在第1主面上，形成至少一个凸部，和用来决定应当分别装载半导体裸片器件的位置的至少2个凹部。凹部的深度比凸部的长度小，且具有比凹部或金属基板的主面高的平滑度。
若根据本发明的的另一侧面，则在由金属或半导体构成的基底基板的一个主面上，预先设置多个用来装载裸片器件的凹部和使基底基板的一部分接线端子状地突出出来的多个凸部，设置把若干个的接线端子的根部围起来的沟，在上述凹部的上边，装配在电极上边含有具有导电性的焊料凸点的半导体器件或IC芯片的裸芯片器件，并用绝缘膜进行覆盖，使得把上述裸芯片器件埋进去，把上述绝缘膜和上述裸芯片器件的焊料凸点平坦化加工成规定的同一高度，再在其上边用金属层和绝缘膜形成布线图形，采用从背面借助于刻蚀或研削使上述基底基板薄层化的办法，借助于上述绝缘膜，形成分离开来的岛状的导体部分，借助于此，可以在基底基板的背面上形成与基准电位导体电隔离的电极。
此外，在切割成与上述基板的已装载上裸芯片器件的主面相反的主面上的单位组件尺寸时，在将成为单位组件的侧面的部位上，预先设置下深度比用上述刻蚀或研削使之薄层化时的切削余量还深的凹部，并在上述刻蚀或研削之后，再切成单位组件尺寸，并设置具有相反的凹坑的金属制造的管帽，使得埋入到在组件的侧面形成的凹坑的部分中去。
此外，在切割成与上述基板的已装载上裸芯片器件的主面相反的主面上的单位组件尺寸时，在将成为单位组件的侧面的部位上，预先设置下深度比用上述刻蚀或研削使之薄层化时的切削余量还深的凹部，并在上述刻蚀或研削之后，再切成单位组件尺寸，并设置具有相反的凹坑的金属制造的管帽，使得埋入到在组件的侧面形成的凹坑的部分中去。
若根据本发明的另一侧面，则用来装载多个半导体裸芯片器件的构造体，可以用下述方法得到：对具有第1和第2主面的金属基板部分地进行化学刻蚀，使得在金属基板的第1主面上边至少形成1个凹部，对金属基板的第1主面进行机械加工，使得在该刻蚀后的金属基板的第1主面的尚未形成凸部的规定的部分上，分别形成用来决定应当装载半导体裸芯片器件的位置的至少2个凹部。用机械加工步骤形成的上述凹部的深度，比用化学刻蚀步骤形成的上述凸部的长度小，且上述凹部具有比刻蚀后的金属基板的主面还高的平滑度。
若根据本发明的另一侧面，则用同时使用刻蚀和冲压的2阶段加工法进行基底基板的制作。首先，用第1阶段的刻蚀加工，制作用来装载裸半导体芯片器件的位置对准用标记。这时，位置对准标记部分将变成为凹状，在其侧面实质上设置15～60度的斜度。若有斜度，则特别是在装载芯片装置时装置将向标记内滑落，借助于自我整合进行的位置对准将会变得容易起来。
就是说，上述2阶段加工法，用第1阶段的刻蚀加工把金属基底基板面往下挖得大一点，同时制作埋设多个裸半导体芯片器件的凹部和连接接线端子的凸部。用第2阶段的冲压加工，使因刻蚀而变得粗糙的金属表面平坦化，并用凸部模具容易地制作具有斜度的多台阶的凹部。
在作成了基底基板后，把具备金属性的焊料凸点的半导体裸芯片器件粘接到上述芯片装置装载用的标记上边。接着，用树脂状的绝缘膜进行覆盖，使得把上述裸芯片器件埋进去，再用研削或研磨等进行平坦化加工，在其上边形成布线图形，完成微型且小型的多芯片组件构造体。
附图的简单说明
图1a～图1e是说明本发明的一个实施例的基底基板的制作工序的剖面图。
图2a～图2d是说明本发明的另一个实施例的基底基板的制作工序的剖面图。
图3a和图3b的平面图和剖面图示出了本发明的一个实施例的基板中的引导标记和围墙的布局。
图4a～图4d的剖面图示出了本发明的一个实施例的多芯片组件构造体的制作工序。
图5a和图5b的剖面图示出了本发明的一个实施例的基底基板的制作工序。
图6是本发明的一个实施例的多芯片组件构造体的剖面图。
图7的平面图示出了图6所示的构造体的背面。
图8a～图8g示出了本发明的一个实施例的多芯片组件构造体的制作工序。
图9的剖面图示出了本发明的另一实施例的多芯片组件构造体的制作工序。
图10的平面图示出了图9所示的构造体的背面。
图11是本发明的一个实施例的多芯片组件构造体的剖面图。
图12的平面图示出了图11所示的构造体的背面。
图13示出了在多芯片组件构造体中含有的电路的一个例子。
图14示出了在本发明的一个实施例的多芯片组件构造体的上表面上描画的图形的一个例子。
优选实施例
图1a～图1e示出了本发明的一个实施例的基底基板的制作工序。首先，作为第1个阶段，在图1a中，在例如由Cu构成的金属基底基板11的第1主面上边，用光刻法制作刻蚀用的光刻胶掩模12。接着，在图1b中，用氯化铁构成的化学刻蚀液，把金属基底基板11刻蚀加工成深度180微米，制作凸状的接线端子或凸部13。接着，在图1c中，进入第2阶段的冲压加工。在模具14、14’之间，插入已制作上接线端子13的金属基底基板11，然后，慢慢地加上加重16开始进行冲压(圆圈内表示具备斜度的模具凸部15)。接着，在图1d中，加上最后的加重结束冲压。凹部17的深度，一般说比凸部13的长度小。
接着，在图1e中，在从模具中取出来的基底基板11上，在装载、粘接裸半导体芯片器件的位置上，形成深度20微米、15度～60度范围的斜度角，在这里，形成45度的凹状标记或凹部17，完成用2阶段加工进行的基底基板的制作。斜度是向着凹部17的底面其面积变小的那样的斜度。
如上所述，2阶段加工的特征在于：在第1阶段的刻蚀加工中把基底基板面向下挖得大一点，设置用来埋设裸半导体芯片器件的凸部，在第2阶段的加工中，用具备斜度的凸状模具使因刻蚀而变得粗糙的金属表面平坦化，并用低加重设置比受到刻蚀的表面平滑度还高的凹状标记或凹部。作为基底基板11的材料，也可以使用Al。
图2a～图2d示出了本发明的另一个实施例的含有多个半导体裸芯片器件的单一组件构造体用基底基板的制作工序。
作为金属基底基板21使用Cu。在基板上边形成的组件尺寸为10mm见方。首先，作为第1阶段，在图2a中，在基底基板21上边，用光刻法制作形成直径200微米的略呈圆柱状的接线端子和用来隔开组件构造体相互之间的井字形的宽600微米的围墙的刻蚀用光刻胶掩模22。接着，在图2b中，用氯化铁系的化学刻蚀液把金属基底基板21刻蚀深度约180微米，制作接线端子或凸部23和把组件构造体相互间隔开来的围墙24。围墙24是对于基底基板来说配置在最外侧的导电性块，起着对构造体进行电磁屏蔽，进行机械性增强的作用。
接着，在图2c中，进入第2阶段的冲压加工。在用预先在基底基板21上形成的引导标记和模具25的标记进行了位置对准之后，对模具25、25’之间的金属基底基板21慢慢地加上加重26开始进行冲压(圆圈内表示具备斜度的模具凸部27)。这时，必须设计为：对于接线端子23、围墙24，模具要制作得大一点，使得在冲压时，上述接线端子23等的形状不变形。在图2d中，参照标号28是在加工后的基底基板21的刻蚀面上边形成的裸半导体芯片器件装载用的凹状标记或凹部。经过该2阶段加工的工序，借助于刻蚀加工，在基底基板内形成接线端子23、把组件构造体相互间隔开来的井字形围墙24，借助于冲压加工，形成裸半导体芯片器件装载用的凹状标记28。
图3a和图3b是把在本发明的实施例的基底基板上设置的引导标记和组件间井字形隔开的围墙的布局图。
图3a是作为用来制作多个组件构造体的基底基板，使用直径75mmφ、厚度700微米、组件构造体尺寸10mm见方的Cu时的平面图。作为引导标记31，在基板周边的4个地方设有直径3mmφ的贯通孔，在冲压之前进行与模具标记之间的位置对准。此外，在各个组件构造体相互之间设有井字形围墙32，把它用做作为使用裸芯片器件装载后的绝缘膜的埋入工序中的基底基板防止挠曲和单位组件构造体切下来时的屏蔽用侧壁。另外，参照标号33表示在各个组件构造体上形成的接线端子或凸部。
此外，图3b示出了沿图3a中的线IIIB-IIIB的剖面图。在用冲压加工形成的裸芯片器件装载部分的标记34上，在其侧面设有45度的斜度。
图4a～4d是本发明的另一实施例的多芯片组件构造体的制作工序。
首先，在图4a中，在设有用刻蚀和冲压在基底基板的第1主面上预先制作的连接接线端子(凸部)42(也形成将其周围围起来的沟部42’)、把组件构造体相互之间隔开的围墙(凸部)43、电极44和裸芯片装载用标记(凹部)45的基底基板41上边，用Au-Sn共晶焊料粘接、装载含有使金属(例如Au或Al等)的焊料凸点46置放在电极上边的多个半导体器件或IC芯片的裸芯片器件47。标记45用与上边说的实施例同样的冲压加工形成，具有斜度。凸部42、43用刻蚀法形成，而标记45和沟部用冲压加工形成。接着，在图4b中，对基底基板41上边的凹部和凸部或裸芯片器件47，进行使用作为第1绝缘膜的环氧树脂48的埋入。接着，借助于研削或研磨热硬化后的环氧树脂48使表面平坦化，使连接接线端子42、围墙43和裸芯片器件47上边的金属焊料凸点46露出来。接着，在图4d中在平坦化后的绝缘膜48上边依次叠层形成用来形成薄膜无源部件和多层布线的第2绝缘膜49、第3绝缘膜50，用金属形成的第1布线图形51，在第1布线图形51上边形成的电容器52，在其上边用金属形成的第2布线图形53和贯通第2、第3绝缘膜49、50的导电性的贯通孔54。之后，从多芯片组件构造体的背面，一直到绝缘膜48露出来为止，进行切削使得借助于研削或刻蚀，使围墙43和电极44与基底基板41隔离开来形成导电块。
然后，在把组件构造体隔开的围墙43的正中间进行切断，变成为单位多芯片组件构造体。导电接线端子42用填充在沟部42’和连接接线端子42与裸芯片器件47之间的埋入树脂进行保持，与基底基板41分离独立。因此，为了从基板背面直接取出电极，可以把多芯片组件构造体直接焊接到母板上，与有导线进行电连的情况比，可以缩小装配面积。
在图5a、图5b中示出了本发明的另一实施例的基底基板的制作方法。在本实施例中，在对已用刻蚀法形成了导电接线端子和围墙的基板进行加工之际，使用与上模具的凸部对应地在下模具上设置了凹部的一组模具。
如图5a所示，进行用刻蚀法形成了导电接线端子61和围墙65的基板60和上模具70a及下模具70b之间的位置对准，用塑性变形之一的冲压加工，形成导电接线端子61周边的树脂埋入沟62和芯片装载用的凹状标记63。
在本实施例中，由于与上模具70a的凸部对应起来在下模具70b上形成了凹部，故被上模具70a的凸部挤压出来的基板，可以向下模具70b的凹部逃逸。因此，与使用平坦的下模具的情况比，在冲压后的基板上难以产生挠曲等的变形。
另外，虽然在冲压加工后的基板上，如图5b所示，会在基板背面形成凸部，但可以用为了使导电接线端子露出来而进行的基板背面的研削工序除去。这时，导电接线端子61的周边的沟部的一部分，起着使围墙65变成为独立的导电块的作用。
倘采用使用并用刻蚀和冲压的2阶段加工的上述实施例，则可以在基底基板的规定部分上以良好的再现性制作规定的深度的凹部和凸部。此外，借助于刻蚀和冲压一揽子形成技术，可以使处理简化和处理时间缩短化。
此外，还可以抑制刻蚀时制作的围墙在用绝缘膜形成的埋入之际的基底基板的挠曲，实现处理的稳定化。
此外，借助于冲压加工，还可以使因刻蚀而变得粗糙的金属表面平坦化，实现裸芯片装载时的粘接条件的容限扩大。即，将会实现在芯片与基板的界面上的无气泡发生和良好的粘接性。此外，由于粘接性提高，故芯片的散热性也将改善。
再有，还可以实现从组件背面取下电极的无引线构造。
图6是本发明的另一实施例的多芯片组件构造体的剖面图。在图6中，用在导电性的例如由金属或半导体构成、含有部分71-1、71-2、71-3、71-4的基底基板71，和在其上边设有裸芯片器件装载用的带斜度的凹坑2，且装载含有在电极上边具有金属(例如Au或Al等)的焊料凸点(连接导体)4的多个半导体器件IC芯片的裸芯片器件3，覆盖为使得把上述裸芯片器件73和基底基板的接线端子部分71-3埋进去的例如树脂的第1绝缘膜75，在其上边用用来进行多层布线的第2绝缘膜76和第3绝缘膜77和金属层形成的第1布线图形78和在第1布线图形上边形成的电容器79和在其上边用金属层形成的第2布线图形80和贯通第2、第3绝缘膜的导电性的贯通孔81-1、81-2、81-3以及覆盖基底基板1的全体的金属制造的管帽82构成。在该多芯片组件构造体中，将成为信号的输入输出端子或电源供给端子的电极(导电性块)在基底基板的背面上实质上并排设置且可以进行与外部之间的电连，借助于基底基板1的接线端子部分71-3用金属层形成，且连接到布线图形80上。管帽也可以使用进行了金属电镀的树脂材料。这时，管帽与用金属制作的情况下一样，起着构造体的屏蔽和机械增强的作用。
此外，图7是从其背面看图6的构造体的图。在图7中，将成为基底基板71的基准电位的部分71-1和将成为电极的部分71-2，借助于第1绝缘膜75进行电隔离。此外，作为电磁屏蔽用，在侧面上设有导电性的壁71-4。
从图8a到图8g，示出了本发明的另一实施例的多芯片组件构造体的制作工序。图8a示出了在对基底基板71的背面进行刻蚀或研削前的状态下的剖面。是借助于刻蚀或机械加工在基底基板的第1主面上，设有平坦部分71-1、电极部分71-2、接线端子部分(凸部)71-3、屏蔽壁(凸部)71-4，和在其上边设有裸芯片器件装载用的带斜度的凹坑72的图。该刻蚀或机械加工，也可以使用在上边所述的实施例中使用的刻蚀或机械加工。但是，在基底基板使用半导体(例如Si)的情况下，要使用冲压加工以外的例如铣削或研削等的机械加工。
图8b是在用图8a示出的基底基板上边，装载含有在电极上边具有金属性(例如Au或Al等)的焊料凸点4的多个半导体器件或IC芯片的裸芯片器件3的图。图8c是把在图8b中所示的基底基板的凹部、凸部和裸芯片器件用绝缘性的树脂75埋进去后的图。图8d是图8c所示的用绝缘性的树脂75把基底基板的凹部、凸部和裸芯片器件埋进去后，借助于研削或研磨树脂75使表面平坦化后的图。图8e是在平坦化后的表面上边，形成了用用来进行多层布线的第2绝缘膜76和第3绝缘膜77和金属层形成的第1布线图形78和在第1布线图形上边形成的电容器和在其上边用金属层形成的第2布线图形80和贯通第2、第3绝缘膜的贯通孔81的图。
图8f示出了借助于刻蚀或研削，一直到沿线VIII-VIII的剖面为止，从其背面切削图8e所示的多芯片组件构造体的情况下的背面。信号的输入输出端子和电源供给用端子(导电性块)71-2，用绝缘树脂，与将成为大地(公用电位)导体的基底电极71-1进行隔离。图8g在借助于刻蚀或研削一直到沿线VIII-VIII为止从背面切削图8f所示的多芯片组件构造体后，在形成屏蔽壁(导电性块)71-4的位置上进行切断，变成为单位多芯片组件的情况。
图9示出了另一实施例，作为基底基板，是与上述实施例一样用刻蚀和机械加工一体地设置平坦部分71-1、电极部分71-2、接线端子71-3和在其上边设置的芯片装载用的凹坑72的图。
图10示出了从背面用刻蚀或研削一直到沿线IX-IX的剖面为止切削图9所示的多芯片组件构造体后的背面。信号输入输出端子和电源供给用端子71-2用绝缘树脂75与将成为大地(公用电位)导体的基底电极71-1进行隔离。此外，在切成为单位组件尺寸时在将成为单位组件的侧面的部位上，预先设置深度比借助于上述刻蚀或研削进行薄层化时的切削余量还深的凹坑部分83。
图11是本发明的另一实施例的多芯片组件构造体的剖面，它是这样的图：在切成与基底基板71的已装载上裸芯片器件的面相反的面的单位组件尺寸时，在将成为单位组件构造体的侧面或基板边缘部分上，预先设置好深度比借助于上述刻蚀或研削进行薄层化时的切削余量还深的固定用凹坑部分83，借助于刻蚀或研削一直到规定的厚度为止进行薄层化，在切成为单位组件尺寸后，设置具有相反的凹坑的金属制造的管帽82，以便向上述凹坑83的部分内填埋。金属管帽82由于起着构造体的屏蔽和机械增强的作用，故没有必要设置屏蔽壁71-4。图12示出了图1所示的多芯片组件构造体的背面。另外，图11是沿图12中的线IX-IX的剖面图。
图13示出了本发明的一个实施例中的多芯片组件构造体中所含有的电路的一个例子。是作为半导体器件使用2个FET的两级高频放大器。图14是图13所示的高频放大器的图形图，信号的输入输出端子Pin、Pout和栅极偏压Vg、漏极偏压Vd通过通孔和导电性接线端子连接到背面的电极端子上。在本实施例中，FET1和FET2分别组装到个别的裸芯片器件中去。其它的电路元件和连接导体则可作为多层布线实现。
倘采用上述实施例，则采用在基底基板上在电极上边装载具有金属性的焊料凸点的多个裸芯片器件，并用树脂状的第1绝缘膜进行覆盖使得将之埋进去，把上述焊料凸点和上述绝缘膜平坦化加工成规定的相同的高度，变成为在其上边形成多层布线图形的多芯片组件构造体，在基底基板的一个面上设置多个用来装载裸芯片器件的凹部和基底基板的一部分接线端子状地突出出来的凸部，在其若干个接线端子的周围预先一揽子地设置好根部岛状地鼓起来那样的沟的办法，使多芯片组件构造体的制作变得容易起来的同时，使在上述基底基板的背面一侧设置信号的输入输出端子和用来供给电源电压的电极成为可能，因此，可以使把多芯片组件构造体组装到母板上去时的引线部分形成得极其之短，可以大幅度地改善在高频区域中的特性。
此外，在把多芯片组件构造体切成单位组件尺寸时，可以在将成为单位组件的侧面的部位形成屏蔽用的壁，因此可以对来自外部的损伤进行机械性的保护，同时在使之在高频区域进行动作这样的情况下，还可以增强电磁屏蔽效果，使得难以受到来自别处的干扰。
工业上利用的可能性
如上所述，已装载上多个半导体裸芯片器件的多芯片组件构造体，通过采用导电性基底基板和在该基板上一揽子地形成的导电性凸部和器件定位用凹部，具有可以改善散热性、高频特性优良、难以受到来自外部的干扰的影响的构造。此外，采用在导电性凸部的形成中和裸芯片器件定位用凹部的形成中分别使用化学刻蚀和机械加工的办法，提高了导电性凸部和器件定位用凹部的再现性。因此，本发明在电子装置的小型化和高性能化方面是有用的。

Claims (37)

1.一种用来装载多个半导体裸芯片器件的基底基板，其特征是：上述基板用金属制作，具备第1和第2主面，在上述第1主面上形成至少一个凸部、和用来决定应当分别装载半导体裸芯片器件的位置的至少2个凹部，上述凹部的深度比上述凸部的长度小，上述凹部具有比上述金属基板的第1主面高的平滑度。
2.权利要求1所述的基底基板，其特征是：上述金属是铜或铝。
3.权利要求1所述的基底基板，其特征是：上述凹部具有向着凹部的底面其面积减小这样的斜度。
4.权利要求3所述的基底基板，其特征是：上述凹部的斜度的角度，实质上为15度～60度。
5.一种多芯片组件构造体，其特征是具有：
具备第1和第2主面，在上述第1主面上形成用来决定应当分别装载半导体裸芯片器件的位置的至少2个凹部的导电性基底基板；
装载在上述第1主面的凹部中的至少多个半导体裸芯片器件；
与上述基底基板绝缘，在上述基底基板的第2主面上边实质上并排设置，在上述基底基板的第1主面一侧和第2主面一侧可以与外部电连的至少一个导电性块；
填充在它们之间的空间内，使得上述导电性块与上述基底基板和半导体裸芯片器件隔离的绝缘物；
设置于上述绝缘物的上方的电连导体。
6.权利要求5所述的多芯片组件构造体，其特征是：上述导电性块设置多个，对于上述基底基板来说配置在最外侧的导电性块可以用来屏蔽构造体。
7.权利要求5所述的多芯片组件构造体，其特征是：还具有覆盖上述基底基板、导电性块、绝缘物和电连导体的管帽。
8.权利要求7所述的多芯片组件构造体，其特征是：上述管帽用树脂制作，起着机械性地增强构造体的作用。
9.权利要求7所述的多芯片组件构造体，其特征是：上述管帽用金属构成，与上述配置在最外侧的导电性块一起工作，起着屏蔽上述构造体的作用的同时，还起着机械性地增强上述构造体的作用。
10.权利要求7所述的多芯片组件构造体，其特征是：上述管帽用电镀上金属的树脂制作，与上述配置在最外侧的导电性块一起工作，起着屏蔽上述构造体的作用的同时，还起着机械性地增强上述构造体的作用。
11.权利要求5所述的多芯片组件构造体，其特征是：上述导电性基底基板和导电性块用金属或半导体材料制作。
12.权利要求5所述的多芯片组件构造体，其特征是：上述凹部具有向着凹部的底面其面积减小这样的斜度。
13.权利要求12所述的多芯片组件构造体，其特征是：上述凹部的斜度的角度，实质上为15度～60度。
14.一种制作用来装载多个半导体裸芯片器件的构造体的方法，具有下述步骤：
对具有第1和第2主面的金属基板部分地进行化学刻蚀，使得在金属基板的第1主面上边至少形成1个凸部的步骤；
对上述金属基板的第1主面进行机械加工，使得在上述金属基板的第1主面的尚未形成上述凸部的规定的部分上，至少形成分别用来决定应当装载半导体裸芯片器件的位置的至少2个凹部的步骤，
用上述机械加工步骤形成的上述凹部的深度，比由上述化学刻蚀步骤形成的上述凸部的长度小，且上述凹部具有比上述刻蚀后的金属基板的主面还高的平滑度。
15.权利要求14所述的制作方法，其特征是：上述金属是铜或铝。
16.权利要求14所述的制作方法，其特征是：上述机械加工是冲压加工。
17.权利要求16所述的制作方法，其特征是：上述冲压加工，包括对于上述凹部的壁面加上向着凹部的底面面积减小这样的斜度。
18.权利要求17所述的制作方法，其特征是：上述凹部的斜度的角度，实质上为15度～60度。
19.权利要求14所述的制作方法，其特征是：用上述化学刻蚀步骤在上述基板的第1主面上形成多个凸部，用上述机械加工步骤，在上述金属基板的第1主面的尚未形成上述凸部的规定的部分上，除了形成上述凹部之外，对于上述多个凸部的至少一个，还形成将其周围围起来的沟部。
20.一种制造多芯片组件构造体的方法，其特征是具有下述步骤：
对具有第1和第2主面的金属基板部分地进行化学刻蚀，使得在金属基板的第1主面上边形成多个凸部的步骤；
对上述金属基板的第1主面进行机械加工，使得在上述金属基板的第1主面的尚未形成上述凸部的规定的部分上，形成分别用来决定应当装载半导体裸芯片器件的位置且深度比上述凸部的长度小的至少2个凹部，和对于上述多个凸部的至少一个，形成将其周围围起来的沟部的步骤；
向上述每一凹部内装载在表面上具有连接导体的半导体裸芯片器件的步骤；
用绝缘层把上述金属基板的第1主面和已装载到其上边的半导体裸芯片器件覆盖起来的步骤；
使上述半导体裸芯片器件的连接导体露出来那样地实质上使上述绝缘层的表面平坦化的步骤；
在上述平坦化后的绝缘层的表面上边形成电连导体的步骤；
使上述沟部露出来并使上述多个凸部的至少一个与上述基板电隔离为止，对上述基板的第2主面进行研削的步骤。
21.权利要求20所述的制作方法，其特征是：上述金属是铜或铝。
22.权利要求20所述的制作方法，其特征是：上述机械加工是冲压加工，上述凹部具有比上述被刻蚀后的金属基板的主面高的平滑度。
23.权利要求22所述的制作方法，其特征是：上述冲压加工，包括对于上述凹部的壁面加上向着凹部的底面面积减小这样的斜度。
24.权利要求23所述的制作方法，其特征是：上述凹部的斜度的角度，实质上为15度～60度。
25.权利要求22所述的制作方法，其特征是：用来形成上述至少2个凹部和将上述凸部的周围围起来的沟部的对上述金属基板的第1主面进行的冲压加工，使用具有上模具和下模具的一对模具进行，上述下模具具有与上述沟部的个数和形状对应的凹坑部分。
26.权利要求22所述的制作方法，其特征是：用上述冲压加工，在上述金属基板的第1主面上，除了上述至少2个凹部和上述沟部之外，在基板的缘部上还形成管帽固定用凹部，在上述研削步骤之后，具有使覆盖上述基板的第1主面的管帽啮合到上述管帽固定用凹部上的步骤。
27.一种制造多芯片组件构造体的方法，其特征是具有下述步骤：
对具有第1和第2主面的半导体基板部分地进行化学刻蚀，使得在半导体基板的第1主面上边形成多个凸部的步骤；
对上述半导体基板的第1主面进行机械加工，使得在该半导体基板的第1主面的尚未形成上述凸部的规定的部分上，形成分别用来决定应当装载半导体裸芯片器件的位置且深度比上述凸部的长度小的至少2个凹部，和对于上述多个凸部的至少一个，形成将其周围围起来的沟部的步骤；
向上述每一凹部内装载在表面上具有连接焊盘的半导体裸芯片器件的步骤；
用绝缘层把上述半导体基板的第1主面和已装载到其上边的半导体裸芯片器件覆盖起来的步骤；
使上述半导体裸芯片器件的连接导体露出来那样地实质上使上述绝缘层的表面平坦化的步骤；
在上述平坦化后的绝缘层的表面上边形成电连导体的步骤；
使上述沟部露出来并使上述多个凸部的至少一个与上述基板电隔离为止，对上述基板的第2主面进行研削的步骤。
28.一种多芯片组件构造体，其特征是具有：导电性基底基板、具有装载于该基板上边的金属性的焊料凸点的多个裸芯片器件、和进行覆盖使得把上述裸芯片器件埋进去的第1绝缘膜，上述绝缘膜的表面和上述裸芯片器件的焊料凸点实质上处于同一高度，在上述绝缘膜的上方形成布线图形，上述焊料凸点和上述图形进行电连，上述布线图形和上述基底基板借助于导电性的接线端子连接，上述导电性接线端子借助于第2绝缘膜与上述基底基板隔离开来构成岛状的电极，上述裸芯片器件装载用的凹部和导电性接线端子与上述基底基板一体形成。
29.权利要求28所述的多芯片组件构造体，其特征是：在基底基板的一部分上设置凸部使得把上述多芯片组件构造体围起来，在其上边设置金属性的凹状管帽。
30.权利要求28所述的多芯片组件构造体，其特征是：在多芯片构造体的侧面一部分上设置凹坑，设置覆盖上述多芯片组件构造体的金属制造的管帽，使得上述凹坑作为限制器起作用。
31.一种多芯片组件构造体的制作方法，其特征是具有下述步骤：在具有第1和第2主面的导电性基底基板的第1主面上边，设置多个用来装载裸芯片器件的凹部和基底基板的一部分接线端子状地突出出来的块的步骤；在上述块的至少一个的根部设置沟的步骤；向上述芯片装载用的凹部内装载具有电极的裸芯片器件的步骤；在上述裸芯片器件的各个电极上边，设置高度至少比上述裸芯片器件的高度之间的偏差高的金属性焊料凸点的步骤；用第1绝缘膜进行覆盖使得把上述裸芯片器件和上述焊料凸点和上述块埋进去的步骤；使上述焊料凸点和上述块和上述第1绝缘膜平坦化为规定的同一高度的步骤；在上述第1绝缘膜的上方形成布线图形的步骤；采用用该第2主面使上述基底基板薄层化的办法，作为电极形成用上述第1绝缘膜进行隔离的岛状的导体部分的步骤。
32.权利要求31所述的多芯片组件的制作方法，其特征是：在基底基板的一部分上，预先设置凸部，使得把上述多芯片组件构造体的整个侧面围起来，并切成在该位置上进行切断那样大小的单位组件尺寸，在其上边设置金属性的凹状管帽。
33.权利要求31所述的多芯片组件构造体的制作方法，其特征是：在切割成与已装载上述裸芯片器件的基底基板的第1主面相反的第2主面上的单位组件尺寸的情况下，在将成为组件的侧面的部位上，预先设置下深度比上述薄层化时的切削量还深且比基底基板厚度浅的多个凹部，并在上述薄层化之后，再切成单位组件尺寸，并设置覆盖上述多芯片组件构造体的金属制造的管帽，使得在基底基板的侧面形成的凹坑作为限制器起作用。
34.一种用来装载多个裸芯片器件的基底基板的制作方法，其特征是具有：用刻蚀法一直到规定的深度为止使导电性基底基板的规定的部分凹下去的第1步骤，和用使用模具的冲压加工使在上述第1步骤中形成的凹部的规定的部分凹下到规定的深度的第2步骤。
35.权利要求34所述的制作方法，其特征是：至少在上述第2步骤之前，还有形成用来使上述模具的位置对准的由2个以上的贯通孔构成的引导标记的步骤。
36.权利要求34所述的制作方法，其特征是：用上述第1步骤用井字形框把多个组件间分隔开来形成凸状的围墙。
37.权利要求34所述的制作方法，其特征是：用上述第2步骤形成的凹部是上述裸芯片器件的装载位置，上述凹部的侧面具有15到60度的斜度角。
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KR100543836B1 (ko) 2006-01-23
WO1999009595A1 (en) 1999-02-25
US6495914B1 (en) 2002-12-17
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