CN1261765A - 复合叠层电路结构及其制作方法 - Google Patents

复合叠层电路结构及其制作方法 Download PDF

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CN1261765A
CN1261765A CN99120976A CN99120976A CN1261765A CN 1261765 A CN1261765 A CN 1261765A CN 99120976 A CN99120976 A CN 99120976A CN 99120976 A CN99120976 A CN 99120976A CN 1261765 A CN1261765 A CN 1261765A
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voltage plane
circuit board
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CN1182763C (zh
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罗斯·W·基斯勒
沃雅·R·马克维奇
吉姆·鲍勒蒂
马里伯斯·伯里诺
威廉·E·威尔逊
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Core Usa Second LLC
GlobalFoundries Inc
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4641Manufacturing multilayer circuits by laminating two or more circuit boards having integrally laminated metal sheets or special power cores
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/429Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4623Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
    • H05K2201/09509Blind vias, i.e. vias having one side closed
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
    • H05K2201/09536Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
    • H05K2201/096Vertically aligned vias, holes or stacked vias
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09809Coaxial layout
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • H05K3/0023Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer

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Abstract

制作复合叠层结构的方法:提供各具有在其至少一个表面上的电路和镀敷的通孔的第一和第二电路板元件。提供具有至少一个电压平面的电压平面元件,两面上有局部固化的感光介电材料层。至少一个孔穿过电压平面元件但隔离于电压平面。在电压平面元件上提供与镀敷的通孔连通的表面。电压平面被层叠在电路板元件之间且电压平面上的光成像材料被完全固化。用导电材料镀敷电压平面元件的表面建立电路板元件电路之间的连接。

Description

复合叠层电路结构及其制作方法
本发明一般涉及到用光刻技术制作叠层电路结构,更确切地说是涉及到利用多个具有信号平面和电压平面的预制电路的复合叠层结构的制作方法以及具有接地平面而没有信号平面的叠层结构。
本申请涉及到1998年12月2日提出的题为“二个信号平面和一个功率平面的电路板”的申请No.09/203956和1998年12月2日提出的题为“多电压平面和多信号平面电路板”的申请No.09/203978。
制作叠层电路板结构的常规技术包括制作介电材料层和导电材料层以提供多层电路和电压平面。电压平面可以是接地平面或功率平面,有时被统称为功率平面。在制作这种结构的现有技术中,介电材料层和导电材料层相继涂敷,亦即涂敷介电材料,然后在其上提供电压平面,而且,如果需要的话,还用钻孔或腐蚀通孔或盲孔的方法制作通孔。此技术依赖于增加额外结构的各个相继的步骤,而电路层被单独地制作;亦即,在制作信号平面的各个步骤中,在制作前一信号平面之后制作各平面,并在制作的功率平面上制作信号平面。这需要钻孔以形成镀敷的通孔,所有这些都很费时间,特别是当大量钻出的孔需要形成镀敷的通孔时,情况更是如此。
于是,希望提供一种比较廉价的光刻技术来制作复合叠层结构,使得能够从单个的分立叠层结构得到复合叠层结构。
制作复合叠层结构的方法包括提供各具有在其至少一个表面上的电路和镀敷的通孔的第一和第二电路板元件。电压平面元件被制作成具有至少一个电压平面,它具有相反的表面,各个表面上有局部固化的感光介电材料层。至少一个孔被光图形化和腐蚀穿过电压平面元件,但完全隔离于电压平面。电压平面元件中的各个通孔与各个电路板元件中的镀敷的通孔对准,以便在电压平面元件上提供与镀敷的通孔连通的表面。电压平面被层叠在电路板元件之间,而电压平面上的光成象材料被完全固化。与电路板元件中的镀敷的通孔连通的电压平面元件的表面被导电材料镀敷,以便在第一和第二电路板元件上的电路之间建立连接。
图1是示意平面图,示出了用于最佳实施例的复合叠层结构具有二个元件的卡或板;
图2是基本上沿图1的2-2线所示平面的剖面图;
图3a-3c是示意剖面图,示出了电压平面复合结构的制作;
图4a-4f示出了将图2所示的二个元件与图3c中的元件层叠以形成最终复合叠层结构的顺序步骤;以及
图5是相似于图4a的待要用于本发明中的电压平面元件的二个元件的另一实施例的剖面图。
本发明提供了一种技术并得到了一种结构,其中二个或更多个基本上完全电路化的元件可以用一个或更多个功率平面元件连接在一起,这些功率平面元件在连接时不被电路化,而是在与电路化元件连接之后被电路化,以便形成多层电压平面和信号平面的复合叠层结构,其中信号平面元件的电路化在层叠各元件以形成最终结构之前基本上完成。
下面利用根据此处列为参考的1998年12月2日提出的题为“二个信号平面和一个功率平面的电路板”的申请No.09/203956制作的元件,在其最佳实施例中来描述本发明。但要理解是的,也可以采用诸如根据此处也被列为参考的1998年12月2日提出的题为“多电压平面和多信号平面电路板”的申请No.09/203978制作的其他电路化元件以及用其他方法制作的元件,或可以采用这些或其他技术制作的电路化分立元件的组合。从本发明的以下详细描述中,这一点将变得更为清楚。
现参照附图,暂时先看图1,示出了用来制作形成本发明的复合叠层结构的电路化元件的多个电路卡或电路板或者电路卡区或电路板区的面板的示意图。如从图1可见,面板10具有多个由参考号12所示的制作在其上的电路卡或电路板,且各个卡或板12被完全围绕各个卡或板12延伸的边界14分隔。还制作了在卡内部提供电隔离的边界16。电路18制作在面板10的二侧上。如将要描述的那样,此处用术语“卡”或“电路卡”来表示可以用作安装芯片和其他电学元件的芯片载体或电路板或电路卡的电路化衬底,它本身成为由二个或更多个这种“卡”或“电路卡”形成的层叠到电压平面元件的复合叠层结构的电路化元件。
图2剖面图示出了用于复合结构的“卡”12的部分结构。在1998年12月2日提出的题为“二个信号平面和一个功率平面的电路板”的申请No.09/203956中,描述了这种面板的制作。各个卡12由作为电压平面的薄铜箔20组成。如此处所用的那样,电压平面可以被认为是接地平面或功率平面,且各个电压平面有时被统称为功率平面,而不管它们是接地平面还是“电压平面”。铜箔接地平面20具有至少一个最好是多个穿过其中而制作的通孔22,以便使镀敷的通孔能够从零件的一个表面延伸到另一个表面。第一层光图形化介电材料24被涂敷在铜箔20的一侧,而第二层光成象介电材料26被涂敷在铜箔20的相反的一侧,且介电材料填充在28所示的通孔22中。
各个介电材料层的厚度最好在2-4密尔之间。特别有用的光成象材料是此处列为参考的共同受让的题为“光成象组分”的美国专利No.5026624所述类型的环氧树脂基材料。这种材料24和26被光成象即光图形化,并被显影以显现所需图形,从而提供其上能够制作电路板的诸如镀敷的铜的金属电路图形的介电衬底(具有通孔)。此介电材料可以如美国专利No.5026624所述那样幕涂,并可以包含触变剂并如美国专利No.5300402所述那样遮蔽涂敷,或可以提供成干膜。如所述申请No.09/203956所述的那样,光成象材料24和26被光图形化、显影和完全固化,其上具有电路和通孔。光成象材料的最终固化提供了其上制作电路的韧化介电基底。此电路包括电路图形44、穿过介电材料24或26到铜箔20的盲孔46、穿过介电材料24和26二者的镀敷的通孔48、以及制作在铜箔20中而不接触铜箔20的通孔22。如所述申请No.09/203956所述,还制作了边界14。在这种条件下,图2示出了面板10。在面板10保持在流水线中,所有的板仍然固定的情况下,或在各个板被切割并在各个板上分立地执行所述层叠程序的情况下,可以完成复合叠层的制作。下面将描述用保持面板10在流水线中作为一个整体的方法实施的工艺。
为了便于描述,此工艺将被描述成利用二个完全相同地制作的面板10,用电压平面叠层元件面板将它们连接到一起。但应该理解的是,如在后续描述中将变得清楚的那样,能够连接各种各样的不同的面板结构,不要求待要连接的各个面板的结构完全一样。而且,面板可以分离成单个的板,然后连接。
如上所述,二个完全相同的面板被用作电路板元件,且为了参照方便,一个板将用没有下标的参考号表示,而被连接的二个面板中的另一个使用后面有下标“a”的参考号。
用电压平面面板60将其上具有卡12和12a的二个面板10和10a连接起来,其制作示于图3a-3c。借助于首先提供最好是具有1盎司常规使用的标准材料铜的铜箔(半盎司或1盎司)的金属层70,来制作电压平面面板60。正如面板10的铜箔20,此金属层的厚度最好应该约为0.7-2.8密尔。
用机械钻孔或用腐蚀方法,在箔70中制作示于72的孔。一种腐蚀技术是利用光刻工艺,其中各个孔的位置被图形化和显影在涂敷于铜箔70二侧上的光刻胶中,并用诸如氯化铜(CuCl2)之类的腐蚀剂将孔腐蚀穿过铜。然后剥离光刻胶。此工艺在本技术领域中是众所周知的。
此工艺简要如下:参照图3a-3c,第一光成象介电材料层74被涂敷在铜箔70的一侧上,而第二光成象介电材料层76被涂敷在铜箔70的相反的一侧上,且介电材料74和76填充示于78的通孔72。此时,光成象材料74和76的厚度最好与面板10的光成象介电材料层24和26的厚度相同;亦即厚度最好在大约0.7-2.8密尔之间。所要求的是,光成象材料74和76能够局部固化并以其局部固化的形式粘附到面板10和10a的介电材料24和26、电路44和46、以及镀敷的通孔48,然后完全固化以接纳电路。
特别有用的光成象材料是此处列为参考的共同受让的题为“光成象组分”的美国专利No.5026624所述类型的环氧树脂基材料。如图2b所示,这种材料被光成象即光图形化,并被显影以显现所需图形,然后固化,以提供其上能够制作形成电路板的诸如镀敷的铜的金属电路图形的介电衬底。此介电材料可以如所述专利No.5026624所述那样幕涂,或可以包含触变剂并如美国专利No.5300402所述那样遮蔽涂敷,此材料也可以涂敷成干膜。制作干膜的技术如下:
制备固体含量约为86.5-89%的光成象介质组分,这种固体包含:大约27.44%的PKHC苯氧树脂;41.16%的Epirez 5183四溴双酚A;22.88%的Epirez SU-8八功能环氧双酚A甲醛合成酚醛树脂;4.85%的UVE 1014光引发剂;0.07%的乙基紫染料;从3M公司得到的0.03%Fc 430氟化聚酯非离子表面活化剂;从Degussa得到的3.85%的Aerosil380非晶二氧化硅;以便提供固体组分。溶剂约为总光成象介质组分的11-13.5%。光成象介电组分被涂敷在从DuPont得到的称为Mylar D的1.42密尔厚的聚对苯二甲酸乙二醇酯聚酯层上。可以对光成象介电组分进行干燥,以便在聚对苯二甲酸乙二醇酯背面提供厚度为2.8密尔的光成象介电膜。
所述专利No.5026624和5300402所述的特定材料74和76是负性感光介质。因此,当此材料在显影液中被显影时,暴露于光化辐照(此时为紫外线)的区域将不被显影(亦即仍然保留),而不暴露的区域将被清除,亦即被显影出来。
电压面板平面元件的目的是在平面10和10a或卡12和12a中提供一个额外的电压平面,以便形成由二个面板10a或二个卡12a、电压平面面板60或电压平面单元62组成的复合叠层结构,电压平面面板60或电压平面单元62提供额外的电压平面和结构,用来使面板10和10a层叠到一起,成为稍后能够切割成二个卡12和12a的单一的叠层结构,如前面所指出的,可以由卡12和12a和电压平面单元62a组成。为此目的,介电材料74和76以及孔填充材料78配备了通孔84,它使电路44a能够与电路44b连通,且电路44-44a的盲孔82和82a能够与铜箔70连通,以形成额外的电压平面。
为此目的,其上具有光刻材料74、76和78的面板60被光图形化和显影,以形成必须的窗口。用常规方法掩蔽图3b所示的结构,并暴露于紫外线,以便提供延伸到箔70的材料74中的通路80和延伸到箔70的材料76中的通路82。还制作了穿过孔72的通孔84,通孔84的边沿与箔20分隔。如所述申请No.09/203956所述,用来显影环氧树脂材料的适当试剂是丙烯碳酸酯,用紫外线完成曝光。
在工艺的这一时刻,光成象介电材料74、76和78处于B阶段固化,亦即,以可控制和可重复的方式,固化到材料能够流动的程度,以便机械地键合到面板10和10a的相反的表面,从而形成复合结构,然后如所述完全固化光成象材料74、76和78。
对应于卡12和12a周围的边界14和14a,还形成了各个电压平面单元62周围的边界88。以相似于制作面板10和10a以及卡12和12a的方式,这些边界被制作成只通过光成象介电材料74而不通过介电材料76,还通过铜箔70,从而保持整体性,然后切割芯片。
图4a-4f示出了最终复合结构的制作。由于电压平面单元62的目的是提供二个卡12和12a之间或者卡12和12a中的一个与铜箔70所确定的电压平面之间的电连接,故必须提供电压平面60或各个电压平面单元62中的必须的电路。电压平面面板60或单元62还必须将二个面板10和10a或二个单元12和12a连接到一起,以形成复合结构。如将要看到的那样,在层叠之后,提供对电压平面面板60或单元62的访问的唯一方法是利用面板10和10a中的镀敷的通孔48。于是,面板10和10a中的镀敷的通孔22必须与面板60上待要制作到各个面板60或穿过各个面板60的电连接的任何位置对准。而且,如将要看到的那样,电压面板60中的通孔84的直径必须小于镀敷的通孔48的直径,且窗口80和82的直径必须小于镀敷的通孔48的内径。
还要求在各个面板待要连接到确定电压平面的铜箔70处,面板10或10a中的镀敷的通孔48必须分别与介质74或76中的窗口80或窗口82对准。各个面板10和10a中的镀敷的通孔48还必须与电压平面60中的通孔84对准。
如图4a所示,部分面板10和10a被示为位于并对准在叠层中,所有电压面板60都要连接以形成复合结构。如早先指出的那样,面板60的介电材料74、76和78处于B阶段固化,因而在面板10和10a上的介电材料24和26被完全固化时,其粘性足以提供对面板10和10a二者的粘附界面。如图4a所示,通孔48和48a与窗口80或82或者与通孔84对准。面板10和10a与电压面板60的相反的侧面接触,而光成象介电材料74、76和78被固化成最终固化状态。最好利用在大约500psi下,将复合面板结构加热到大约190℃的温度,停留大约2小时的方法,来执行这一过程,这将得到至少大约95%的固化,并得到图4b的叠层结构。
利用图4b所示的层叠到电压面板60的相反的侧的一对面板10和10a组成的复合结构,介电材料74和76的固化提供了接纳铜镀层的适当的表面。为此目的,用光刻技术镀敷面板10和10a与电压面板60之间所需的互连。
如图4c所示,用钯层或其他引晶层99,对面板10和10a、开放的通孔48或48a以及边沿106和108的暴露的表面进行引晶,并如图4d所示,用光刻胶材料对其进行涂敷。可以是负性或正性光刻胶。如图4d所示,光刻胶被图形化和显影,以便在所有与待要用来提供到面板60或穿过面板60的互连的通孔48或48a之一对准的位置处提供窗口102和102a。(记得,能够形成对面板60的连接的唯一路径是通过镀敷的孔48和48a)。此布局于是提供了穿过电压面板60的通孔84、待要通过镀敷的通孔48形成连接处的孔84周围的边界106、以及窗口80和82周围的边界108。
然后最好用常规的叠加镀敷技术,用铜110对复合面板进行无电镀敷或电镀,以便提供必要的互连。镀敷的结构示于图4e,且包括孔84中的镀敷的连接112和孔80和82中的镀敷的连接114。
接着,剥离光刻胶100,并快速腐蚀引晶层99,以便提供图4f所示的由通过电压面板60而物理和电学连接的面板10和10a组成的所希望的复合结构。从具有由一对卡12和12a以及电压平面单元62组成的各个卡的复合结构的面板,切割出各个板。
如早先所述,最佳实施例利用二个板12和12a以及电压平面单元62。但需要理解的是,可以利用额外的卡12和12a和额外的电压平面单元62来制作由三个或更多个卡12、12a、…、12n组成的复合体,也可以采用二个或更多个电压平面单元62。同样,如早先指出的那样,卡12和12a不一定要完全相同,而是可以预先设计和镀敷成执行所希望的电学功能。同样,如早先指出的那样,本发明不局限于申请No.09/203956所述的制作板的技术。例如,以与申请No.09/203956的板或与其他相同类型的板或不同类型的板进行组合的形式,也可以使用由申请No.09/203978所述的二个功率平面组成的板。根据申请No.09/203978的情况示于图5。
因此,已经描述了本发明的最佳实施例。但记住前面的描述,要理解的是,本描述仅仅是以举例的方式进行的,本发明不局限于此处所述的特定的实施例,而是可以进行各种各样的重组、修正和替换而不超越以下权利要求所述的本发明的真实构思。

Claims (17)

1.一种制作复合叠层结构的方法,它由下列步骤组成:
提供各具有在其至少一个表面上的电路和镀敷的通孔的第一和第二电路板元件,
提供具有至少一个电压平面的电压平面元件,它具有相对的表面,其各个表面上有局部固化的光图形化介电材料,
光图形化和腐蚀至少一个穿过所述电压平面元件的孔和至少一个穿过各个光图形化介电材料层的终止于所述电压平面的窗口,
使所述电压平面元件中的各个通孔和各个窗口与至少一个所述电路板元件中的镀敷的通孔对准,以便在所述电压平面元件上提供与所述镀敷的通孔连通的表面,各个所述电路板元件的所述至少一个表面与所述电压平面元件分隔开,
将所述电压平面元件层叠在所述电路板元件之间,并完全固化所述电压平面元件的所述光成象材料,以及
对与所述电路板元件中的所述镀敷的通孔连通的所述电压平面元件的表面进行镀敷。
2.权利要求1所述的发明,其中所述电路板元件至少部分地由完全固化的光成象材料组成。
3.权利要求1所述的发明,其中在所述电路板元件的各个表面上有电路。
4.权利要求1所述的发明,其中用光刻技术对所述表面进行镀敷。
5.权利要求1所述的发明,其中的镀层是铜镀层。
6.权利要求1所述的发明,其中所述电压平面元件具有单个电压平面。
7.权利要求1所述的发明,其中各个电路板元件具有至少一个电压平面。
8.权利要求7所述的发明,其中各个电路板元件具有穿过所述至少一个电压平面的镀敷的通孔。
9.权利要求1所述的发明,其中至少一个电路板元件具有多个电压平面。
10.权利要求1所述的发明,其中所述光图形化介电材料是环氧树脂。
11.一种复合叠层结构,它包含:
各具有在其至少一个表面上的电路和镀敷的通孔的第一和第二电路板元件,
层叠在所述第一和第二电路板元件之间的具有至少一个电压平面的电压平面元件,它具有相反的表面,其各个表面上有完全固化的光图形化介电材料层,各个电路板元件的至少一个表面与所述电压平面元件分隔开,
腐蚀至少一个穿过所述电压平面元件的孔和至少一个穿过各个光图形化介电材料层的终止于所述电压平面的窗口,
所述电压平面元件中的各个通孔和各个窗口与至少一个所述电路板元件中的镀敷的通孔对准,以便在所述电压平面元件上提供与所述镀敷的通孔连通的表面,各个所述表面包括环孔或所述电压平面元件的所述光图形化材料,
所述电压平面元件上的与所述电路板元件中的所述镀敷的通孔连通的在所述电压平面元件中的所述电路与所述电压平面之间建立电连通的导电材料。
12.权利要求11所述的发明,其中在所述电路板元件的各个表面上有电路。
13.权利要求11所述的发明,其中所述电压平面元件具有单个电压平面。
14.权利要求11所述的发明,其中各个电路板元件具有至少一个电压平面。
15.权利要求14所述的发明,其中各个电路板元件具有穿过所述至少一个电压平面的镀敷的通孔。
16.权利要求11所述的发明,其中至少一个电路板元件具有多个电压平面。
17.权利要求11所述的发明,其中所述光图形化介电材料是环氧树脂。
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CN110996526A (zh) * 2019-12-27 2020-04-10 生益电子股份有限公司 一种信号过孔的制作方法
CN110996526B (zh) * 2019-12-27 2020-11-03 生益电子股份有限公司 一种信号过孔的制作方法

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US6451509B2 (en) 2002-09-17
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US20010023044A1 (en) 2001-09-20
HK1027468A1 (en) 2001-01-12
CN1182763C (zh) 2004-12-29
KR20000047807A (ko) 2000-07-25
US6175087B1 (en) 2001-01-16

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