CN1247632A - 使阈值电压上升的升压阱 - Google Patents

使阈值电压上升的升压阱 Download PDF

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CN1247632A
CN1247632A CN97181967A CN97181967A CN1247632A CN 1247632 A CN1247632 A CN 1247632A CN 97181967 A CN97181967 A CN 97181967A CN 97181967 A CN97181967 A CN 97181967A CN 1247632 A CN1247632 A CN 1247632A
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alloy
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S·E·汤普森
P·A·帕坎
T·哈尼
M·斯特特勒
S·S·阿梅德
M·T·波尔
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Intel Corp
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Abstract

一种改进的升压阱注入,它可比传统的辉光注入提供更好的特性,特别是对于短沟道装置(例如0.25微米或更小)。事实上,注入物可被分布在整个沟道内,但当器件的栅长度小于临界尺寸时,须使较高的浓度发生在沟道的中央,这时可采用很大的倾斜角(例如30°－50°)、较轻的搀入物品种和比传统的辉光注入大的能量来注入。

Description

使阈值电压上升的升压阱
本发明的背景
1.本发明的领域
本发明涉及金属氧化物半导体(MOS)场效应晶体管的制造。
2.现有技术
各种技术曾被用来注入MOS晶体管的沟道区域以资控制短沟道效应或改变其他一些特性。一个常用的技术为所谓“辉光”注入(haloimplant)，其中邻近这些区域注入导电类型与源区域和漏区域所用相反的离子。这些高掺杂的区域提供较高的穿通电阻包括对抗漏极引起的位垒降低的较高电阻。
在现有技术中在辉光区域内注入掺杂物通常是在形成栅后晶片倾斜时进行的。可参阅发表在IEDM 88上从394页开始的Hori和Kurimoto的著作“一个新的半微米P沟道的带有LATIPS的MOSFET”，(LATIPS为LArgc-Tilt-Angle Implanted Punchthrough Sfopper的缩写)。
本发明的综述
下面说明用来制造MOS器件的一种改进方法，该MOS器件具有属于第一导电类型的栅、源区和漏区，它们是在属于第二导电类型的衬底区域上形成的。将属于第二导电类型的掺杂物注入到衬底内，这样在栅长度减短时，来增加属于第二导电类型的掺杂物在某一区域内的掺杂物浓度，这个区域一般在源区和漏区的中间。这点特别有用，因为对给定的临界尺寸，由于栅长度的变化某些器件的栅长度小于临界尺寸。这些器件将具有较高的搀入物浓度从而得到改进的穿通特性。
附图的简要说明
图1为现有技术的几沟道MOS晶体管的横剖面立视图，图中示出辉光注入在源区域和漏区域的邻近。
图2为按照本发明的几沟道MOS晶体管的横剖面立视图。
图3为一横剖面立视图，示出用来获得本发明的升压阱的加工步骤。
图4为一曲线图，分别示出对于现有技术的辉光注入，现有技术的无辉光器件和本发明的升压阱的沟道中的栅长度对闸值电压的关系。
图5为一曲线图，示出本发明的掺杂物浓度在栅长度不同的晶体管的沟道中的情况。
本发明的详细说明
现在说明栅长度较短时如何提供升压阱使阈值电压上升的方法。在下面的说明中列出众多的具体细节，如特定的浓度水平、掺杂物等，为的是使人们对本发明有一透彻的理解。显然对本行业的技术人士来说，不需这些具体细节也可将本发明付诸实施。另外公知的加工步骤不再详细列出以免与本发明混淆。
参阅图1所示的在P型衬底或阱上形成的现有技术的MOS的晶体管的横剖面立视图，栅10用绝缘层17与晶体管的沟道区域绝缘。在栅两侧形成的间隔层11和12被用来限定源区13和漏区14的较浅的延伸部，这是本行业中公知的。用离子注入形成的辉光区域15和16例如是在源区和漏区掺杂之前用较重的P型掺杂物以两个不同的角度注入而形成的，因此掺杂物如图所示那样分布，这样造成以后要形成源区和漏区的区域在初始时被P型掺杂物掺杂。但被n型掺杂物的反掺杂盖上，形成如图1所示的留下辉光区域的n沟道器件。如同在本申请的现有技术部分中所提到的那样，辉光区域15和16被用来改进晶体管的穿通特性。
图2示出按照本发明制造的场效应晶体管。人们将可了解到，当栅20的栅长度约为0.25微米或更小时，本发明的优点可充分体现。在制造图2的晶体管时，栅先用绝缘层27与衬底绝缘。例如，栅的长度可为0.22微米，高度可为0.25微米，用厚度为40A的二氧化硅层与衬底绝缘。现在就可形成本发明的升压阱，这在下面还要论述。然后在多晶硅栅20的两侧设置间隔层21和22。间隔层是用非导电的材料如氮化硅制成的。间隔层如同图1的晶体管那样，被用来限定源区和漏区的较浅的延伸部23和24。然后，源区和漏区被掺杂。接下来再形成金属层，这是公知的，以便完成集成电路。
与图1中的辉光区域不同，按照本发明，区域25被用在图2中的晶体管内。这个P型的区域比图2的晶体管将制造于其中的所用的衬底或阱被较重地掺杂。不是如同图1所示的那样，是在源和漏的延伸部下面的两个分开的辉光区域，就本发明而言，是希望在栅氧化物27之下的沟道的中央部有尽可能多的掺杂。这个较高浓度的搀入物在图2中由区域26示出。可以看到，这正好发生在阀门长度减少的地方，因此在补偿临界尺寸的变化时特别有用。掺杂的区域25代表本发明的升压阱，由于还可提供其他优点，如阈值电压可在较短的沟道内上升，这将结合图4来说明。
现在参阅图3，其中示出图2中区域25的制造。首先，在形成区域25之前，在衬底上形成栅绝缘层如二氧化硅层27。随后，一个通常由多晶硅制成的栅在绝缘层27上形成。栅20是通过掩蔽，然后腐蚀多晶硅层形成的。现在一个光刻胶层33被暴光并显影从而形成开口34，这就是用来进行本发明的升压阱注入和形成源区域和漏区域的延伸部的开口。
就本发明而言，在形成开口34后，对在其上制出栅20的衬底进行离子注入，所注入的离子具有与在其上制出晶体管的区域相同的导电类型。这个区域一般为在CMOS工艺所用体衬底内形成的掺杂的阱。对于n沟道晶体管，P型掺杂物被注入到P阱30内。这个注入是在对法线成很高倾斜角的情况下发生的，并且最好用轻掺杂物品种以较高的能量注入。这样可迫使掺杂物进到栅之下并进入到沟道的中央区域内。
就本发明而言，掺杂物以30°或更大的角度注入，一般在30°和60°之间。在图3中可看到的掺杂物先按角度37注入，注入掺杂物的轨迹用平行线36示出。然后将该角度倒转，掺杂物按角度38注入，掺杂物的轨迹用平行线35示出。这两个角度都约为30°或更大。一般地说，由于晶体管是沿正交线注入的，可用四个注入方向，相互错开90°，而每一个注入的倾斜角约为30°或更多，如图3的角度37和38。
在一注入硼的典型应用中，B11用四个相互相差90°的注入方向注入，而每一次注入对衬底的倾斜约为30°。这四次注入的总剂量为2×1013，所用能量为10-20KEV。这个掺杂物是在源区和漏区被掺杂后被一快速的热退火(例如10秒内退900到1100℃)推进的。
在这种升压阱注入完成后，晶体管的源区和漏区可按标准方式形成。例如，n型掺杂物的较浅的注入可形成源区和漏区的延伸部。随后可用n型掺杂物的注入和推进来制造间隔层，借以限定源区域和漏区域的主要部分。或者，源区和漏区的延伸部可从形成间隔层一部分的掺杂玻璃层扩散而成。
虽然没有示出，在制造P沟道晶体管时，可用n型的掺杂物如砷或磷，以很大的倾斜角和较高的能量注入，来确保沟道区的中央部分具有较大的掺杂物浓度。
现在参阅图4的曲线图，该图示出三种方法的沟道长度(横座标)对阈值电压(纵座标)的曲线关系。首先，曲线42代表一个没有使用辉光注入的晶体管的特性，曲线43说明在使用图1所示的辉光注入时的特性。可以看到，不管是标准的辉光注入，还是没有辉光注入，当栅长度减少时阈值电压都有一个急剧的滑落。曲线41示出按照本发明的升压阱。从该典型可以看到，当栅长度减少时阈值电压可以上升。这一点很重要，因为它允许将器件的沟道制成极短的长度(例如小于0.1微米)并能给临界尺寸的变化提供容差。
事实上除非沟道长度约为0.25微米或更小，是不能得到本发明所能得到的重大收益的。图5中示出在用本发明加工后，相应于数个不同栅长度的沟道中的掺杂物浓度的变化。曲线50示出5微米长栅的掺杂物浓度。如从图上可见，较高的掺杂物浓度并不在沟道的中央而是在沟道的两边。与此类似，曲线51是0.8微米栅长度的，再一次可以看到在沟道的中央掺杂物浓度有一小的下垂。但随着栅长度的减少，在沟道中央的掺杂物浓度也是在增加的。曲线52代表0.3微米长的栅，其浓度就比0.8微米长的栅的沟道中央的浓度高。曲线53指出栅长度为0.22微米时，例如与5微米的栅相比，整个沟道的掺杂物浓度较高。最后，曲线54示出对于长度为0.18微米的栅，沟道内的掺杂物浓度还要高。由此可见，本发明的最佳结果是在栅长度大约为0.25微米或更小时获得的。如同以前曾提出的，沟道中的最高浓度应在沟道的中央而不是在源区和漏区的延伸部上。
本发明的显著优点是，对于一个给定的注入剂量，较高的浓度发生在较短的栅长度上。这样，当临界尺寸为0.22微米(栅长度)时，如果预期会发生变化，其中某些栅长度例如可小到0.18微米。那么从图5可以看到，这些0.18微米的器件的沟道将被更高地掺杂，从而可给临界尺寸的变化提供补偿。但如果沟道在栅形成之前已被注入，那么在较短的栅长度内进行较高的注入将不会发生。
以上我们说明了升压阱方法，该方法能在较短的栅长度上使阈值电压上升。除了能从辉光注入提供更多的传统效果如减少从源到漏的泄漏电流和改善穿通特性外，还已发现，可用本发明的升压阱注入来改善晶体管的高频特性。

Claims (11)

1.用来制造具有栅的MOS器件的一种改进方法，该MOS器件具有属于第一导电类型源区和漏区，它们是在属于第二导电类型的衬底区域上形成的，该改进方法的特征为，将属于第二导电类型的掺杂物注入到衬底内，这样在栅长度减短时，来增加属于第二导电类型的掺杂物在某一区域内的掺杂物浓度，这个区域一般在源区域和漏区域的中间。
2.按照权利要求1的方法，其特征为，注入是在30°或更大的角度下进行的。
3.按照权利要求1的方法，其特征为，注入是按四个步骤进行的，每一步骤都对衬底倾斜约30°或更大。
4.在制造具有标称栅长度1的MOS器件而其中某些器件的栅长度小于1时，改进的特征为，将器件的栅下面的沟道掺杂，使栅长度小于1的那些器件的栅下面的掺杂物浓度比栅长度为1的那些器件的栅下面的掺杂物浓度高。
5.一种在第一导电类型的衬底区内形成晶体管的方法包括下列步骤：
形成与衬底区域绝缘的栅；及
将属于第一导电类型的掺杂物以约为30°或更大的角度注入到衬底内。
6.按照权利要求5的方法，其特征为，注入的第一导电类型的掺杂物包括以约为15KEV或更大的能量注入的B11。
7.按照权利要求5的方法，其特征为，注入的第一导电类型的掺杂物包括磷。
8.按照权利要求5的方法，其特征为，注入的第一导电类型的掺杂物包括砷。
9.按照权利要求6的方法，其特征为，栅的长度约为0.25微米或更小。
10.按照权利要求7的方法，其特征为，栅的长度约为0.25微米或更小。
11.按照权利要求8的方法，其特征为，栅的长度约为0.25微米或更小。
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