CN1247613A - 对数字运算和逻辑运算进行处理以及在处理机(cpus)、多计算机系统中使用的装置 - Google Patents

对数字运算和逻辑运算进行处理以及在处理机(cpus)、多计算机系统中使用的装置 Download PDF

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CN1247613A
CN1247613A CN97181623A CN97181623A CN1247613A CN 1247613 A CN1247613 A CN 1247613A CN 97181623 A CN97181623 A CN 97181623A CN 97181623 A CN97181623 A CN 97181623A CN 1247613 A CN1247613 A CN 1247613A
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马丁·福尔巴赫
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    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
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    • C01B13/11—Preparation of ozone by electric discharge
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30134—Register stacks; shift registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3893—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
    • G06F9/3895—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
    • G06F9/3897—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path
    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B01J2219/00—Chemical, physical or physico-chemical processes in general; Their relevant apparatus
    • B01J2219/08—Processes employing the direct application of electric or wave energy, or particle radiation; Apparatus therefor
    • B01J2219/0803—Processes employing the direct application of electric or wave energy, or particle radiation; Apparatus therefor employing electric or magnetic energy
    • B01J2219/0805—Processes employing the direct application of electric or wave energy, or particle radiation; Apparatus therefor employing electric or magnetic energy giving rise to electric discharges
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    • C01B2201/30—Dielectrics used in the electrical dischargers
    • C01B2201/32—Constructional details of the dielectrics
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S422/00—Chemical apparatus and process disinfecting, deodorizing, preserving, or sterilizing
    • Y10S422/907—Corona or glow discharge means

Abstract

本发明涉及一种计算装置,它根据下述配置由一逻辑装入部件(PLU)控制,并可在运行时间过程中进行配置和重新配置:本发明提供一算术逻辑部件(EALU),它的功能和联网在寄存器中编程。寄存器内可在处理大量数据而不必对处理机(PAE)重新编程。为了控制算术逻辑部件(EALU),本发明提供一状态机(SM－UNIT);另外还分别为每一种运算数和结果提供寄存器(分别是O－REG和R－REQ),这些寄存器是按照部分充当移位寄存器设计的。结果寄存器数据经过一多路转换器(R10－MUX)反馈到EALU的一个输入端。一总线多路转换部件(BM－UNIT)有可能自总线系统读取数据和将结果输送到总线系统,同时。在有多个接收机的情况下,总线部件可以自动将数据传送给多个接收机,寄存器防止EALU中的数据处理系统访问总线,因此,每一个PAE可视为一个独立的装置,其中,PAE的配置和重新配置不影响数据发动机和接收机或各个独立的PAE。

Description

对数字运算和逻辑运算进行处理以及在处理机(CPUS)、 多计算机系统中使用的装置
1.本发明的背景
1.1技术现状
在公开说明书DE 16 881 A1中描述了一种进行数据处理的技术。其中，在其功能和联网中广泛地运用了可自由配置的、均匀排列的元件。
与上述公开说明书无关，为了设计由许多单一的逻辑元件构成的运算器和数据处理装置，EPGA部件(可自由编程逻辑部件)得到了越来越多地应用。
另外一个已知的技术是设计由在很大程度上固定联网的固定程控运算器，即所谓的脉冲处理机构成的数据处理装置。
1.2问题
1.2.1根据DE44 16 881 A1的部件
根据DE 44 16 881 A1所述技术的部件(以下简称为VPU)是基于大量的小型逻辑元件以很高的代价配置起来的。为了控制一个逻辑元件，要在一个静态存储器(SRAM)内提供许多控制位。每一个逻辑元件具备一个SRAM地址。需要配置的SRAM部件数量很大，这必然导致很大的空间需求量和花费很多时间，才能配置和重新配置一个这样的部件。高空间需求特别不能接受，因为一VPU的处理能力是随着元件数量的增加而提高。但是，一个部件的可利用面积受到芯片制造技术的限制。芯片的价格与芯片的面积成平方关系。基于多重图象显示的下一个邻点联网结构，广播通信，也就是把数据同时发送给多个接收机，是不可能的。如果VPU在运行中进行重新配置，则一行需要达到短暂的重新配置时间。然而，与此相反，为了重新配置芯片，需要拥有大量的配置数据。不存在将元件与电源分离或缓慢地提供时钟脉冲的可能性，以便把损耗功率减少到最低限度。
1.2.2 FPGA部件
对于上述应用领域至关重要的FPGA部件，多半是由多路或查表结构(LUT)组成的。执行采用了SRAM部件。由于拥有很多小SRAM部件，所以其配置费用很高。需要有大量的数据，要求花费相当多的时间进行配置和重新配置。SRAM部件需要占用很多空间。但是一个部件的可用面积受芯片制造技术的限制。价格的上升与芯片面积大致成平方关系。SRAM所依赖的技术由于在SRAM上的存取时间而比直接集成逻辑要慢。虽然很多FPGA部件建立在总线结构上，但根本没有广播通信能力，迅速而有效地同时向多个接收机发送数据。如果要FPGA部件在运行中进行重新配置，则迫切需要达到很短的配置时间。但这样就需要有大量的配置数据。FPGA部件对运行中有意义的重新配置完全不提供支持。编程人员必须顾及过程能正常进行，对数据和相关的逻辑不存在有干扰作用的影响。把损耗功率减少到最低限度的智能逻辑是不存在的。没有专门的功能部件允许把运行状态的信息反馈给控制FPGA的逻辑电路。
1.2.3脉动处理机
脉动处理机上完全取消了重新配置，不过这种处理机是没有灵活性的，因为它有刚性的内部结构。指令在每一循环中都被重新解码。正如在上面两节中已经说明的，缺少执行广播通信和把损耗功率减少到最低限度的功能。
1.3本发明的改进，任务
本发明包括一个级联的运算器，该运算器在其功能上和联网方面具有灵活性，是可配置的。
在执行算法的过程中不需要指令解码。它在运行中是可重新配置的，对周围的运算器、处理模块和数据流没有影响。配置数据的量很小，这对空间需求量和配置速度的影响都是有利的。为了迅速和有效地分配大量数据，经过内部总线系统支持广播通信。运算器配备了省电功能，借以可完全切断功率消耗，同样还有时钟分配器，可使运算器以较小的时钟脉冲工作。为了把内部状态反馈给外部控制电路，有特别的机制可供使用。
2.本发明的说明
2.1本发明概况，简介
本发明说明根据DE 44 16 881 A1一种元件或已知FPGA元件的结构或已知的FPGA部件集成于这种元件中的是一围绕特殊功能扩充了的、进行数据处理的算术逻辑部件(EALU)。这种EALU经过一功能寄存器进行配置，因而可明显地降低配置所需要的数据量。元件可经过一总线系统进行自由级联，让EALU经过输入、输出寄存器与总线系统分离。输出寄存器返回到EALU的一输入上，以便能进行串行操作。接入到总线接受一总线控制部件，该总线控制部件根据总线寄存器相应地与总线耦合。这样就构成了能够将数据分配给多个接收机(广播通信)的器件。一个同步电路经过总线系统控制多个元件之间的数据交换。EALU、同步电路、总线控制部件和寄存器的电路连接方法使得一个元件可以在运行中独立于其它外围元件被重新配置。经过功能寄存器可以配置一个与元件断开的省电模式，同样可以接通减低工作频率的时钟分配器。
2.2本发明的详细说明
本发明说明符合DE 44 16 881 A1主旨的一种元件(PAE＝阵列处理机)或已知的FPGA元件的结构，其中，阵列处理机可与一阵列(处理阵列＝PA)级联。一个阵列处理机由许多个功能部件构成。
2.3 EALU
运算器由一个固定在逻辑电路中执行的扩充算术逻辑部件(EALU)组成。一个EALU就是符合当前技术水准的普通的算术逻辑部件(ALU)，它通过特殊功能，诸如计数器之类，而加以扩充。这种EALU能进行大量的算术和逻辑运算，无须在这里作详细规定，因为可以根据当前技术水准追溯到ALU。EALU直接存取它自己的结果，对此，我们将在后面作为运算数加以追述。这样，计数器或串行操作，诸如串行乘法、除法或级数展开，都是可行的。EALU除了它的结果以外，还提供信号CarryOut-AlessB和AequalB-Odetect。CarryOut-AlessB或者在算术运算时说明进位，或者在利用减去两个值进行比较时，进位也就是CarryOut-AlessB，说明A＜B或B＜A，取决于求反的运算数。这个信号是通过一个全加器产生的普通进位。AequalB-Odetect说明在结果寄存器R-REGsft中的结果等于0。这个信号经过一“或非”从结果中产生。两个信号被用来对状态进行简单处理，并可以重新提供给PLU(逻辑装入部件)。其它的状态信号根据应用情况是可执行的。
EALU的功能在一功能寄存器(F-PLUREG)中配置。
2.3.1 O-REG
EALU的输入运算数被存储在两个独立的运算数寄存器(O-REG)中。借此，这些运算数可供使用，与提供数据的部件(数据发送器)的状态无关。这是必要的，以便能实现与总线脱开和PA(PA＝处理阵列)的自由重新配置。一个或两个O-REG具有移位功能，由每一个相关O-REG的EALU进行控制。移位功能允许在EALU中进行串行操作，诸如乘法或除法等。具有移位功能的O-REG被称为O-REGsft。
2.3.2 R-REGsft
EALU的结果被存储在一个结果寄存器中(R-REGsft)。由此实现了时间上与一个或数个接收结果的部件(数据接收机)的不相关性。R-REGsft具有移位功能，由EALU控制，因而允许进行串行操作。
2.3.3 R2O-MUX
存在于R-REGsff中的结果数据，经过在两个O-REG中的一个与EALU之间的一多路转换器(R2O-MUX)作为运算数并入电路，以保证串行操作、计数器和类似功能结果的反馈。多路转换器通过F-PLUREG调整。
2.2.4时钟脉冲周期
重要的，但不是迫切需要的事，是在一时钟脉冲边沿上控制O-REG(sft)并在其后否定的时钟脉冲边沿上控制O-REGsft。这样，EALU就有一个“半时钟脉冲”可用来执行其功能。第二个“半时钟脉冲”供信号传输时间和多路转换器使用。于是有可能在每一个时钟脉冲中进行一次完整的运算。
2.2.5状态机，SM-Unit
为了在EALU中进行过程控制，设有一个SM-UNIT。它控制O-REG和R-REGst及其移位功能，还控制R2O-MUX。借此，可以达到串行操作、移位和计数功能能简单地由EALU执行的目的。其中的状态机可以根据当前技术水准简单地实现。
2.2.6 Sync-UNIT
为了在诸阵列处理机的一个阵列(PA)中对一阵列处理机进行整步，设有一个同步部件(Sync-UNIT)。这个Sync-UNIT为一系列执行信号交换协议的输入信号求值。rACK(h/l)：这个数据接收机认收已收到的数据。其中，rACKh是高结果位(8到
       15位)的认收，rACK1是低结果位(0到7位)的认收。两者进行
       “与”运算(rACKh“与”rACK1)，并产生信号rACK。当一个或
       两个数据接收机正在处理其数据的过程中时，rACK是不真实的；
       当两个数据接收机的数据处理已经结束，并已将结果存储在相关的
       数据接收机的R-REGsft中时，rACK是真实的。另外，信号
       rACK(h/l)往往采用经过“与”运算的形式，被视为rACK(＝rACKh
       & rACK1)。oRDY(1/2)：这个数据发送机信号化其准备状态，发送新数据。当数据发送机正
       在处理其数据的过程中时，oRDY是不真实的；当数据发送机提供
       结果(它是阵列处理机的运算数)供使用时，oRDY是真实的。其
       中，oRDY1是第一个运算数数据发送机的释放信号，oRDY2是第
       二个运算数数据发送机的释放信号。两者进行“与”运算(oRDY1
       “与”oRDY2)，并产生信号oRDY。只有当两个数据发动机准备
       好发送数据时，oRDY才是真实的。信号oRDY(1/2)往往采用经过
       “与”运算的形式，被视为oRDY(＝oRDY1 & oRDY2)。
由输入信号和Sync-UNIT的状态(它与EALU的过程控制一道代表阵列处理机的总状态)生成输出信号，该输出信号被数据发送机和接收机的Sync-UNIT从它们一面视为输入信号。为了进行EALU的过程控制，需要使用其状态信息和寄存器F-PLUREG。rRDY：表示阵列处理机已经结束了它的数据处理，结果在R-REGsff中提供使
  用。rRDY被作为rRDYh和rRDY1传输给两个数据接收机。但它所涉
  及的是同一个信号！oACK：表示阵列处理机已经处理了它的运算数，新的数据可以录入o-
  REG(sft)。oACK被作为oACK1和oACK2传输给两个数据发送机。但
  它所涉及的是同一个信号！
RDY信号保持其电平，直到通过ACK输入认收为止。当数据接收机在数据准备过程中进行重新配置时，必需如此。如果RDY排队等候，直到通过ACK认收，则数据接收机在重新配置后确认数据准备就绪，并接受数据。
信号经过若干个阵列处理机的逻辑电路表示如下：
数据发送机 阵列处理机 数据接收机
    rRDY   →   oRDY rRDY   →     oRDY
    rACK   ←   oACK rACK   ←     oACK
这意味着，例如数据发送机的输出信号rRDY代表阵列处理机的输入信号oRDY1或oRDY2。阵列处理机的输出信号rRDY代表数据接收机的输入信号oRDY。
Sync-UNIT具有系列过程形式：
    模式     说明     备注
Warten OP(等待运算数) 阵列处理机等待运算数 只有当无多循环操作正在执行时
Zyklus 1(循环1) 一个单循环操作正在执行 运算数被认收
Zyklus n(循环n) 一多循环操作中的一个循环正在执行
Zyklus Z(循环Z) 一多循环操作中的最后一个循环正在执行 运算数被认收
Warten ERG(等待结果) 阵列处理机等待结果的被认收 只有当前面的结果已存在时
Stop(停止) 结束正在运行的循环后停止执行，然后，如果结果已被认收，则认收ReConfig(重新配置)
Sync-UNIT提供一个特别模式供使用，只有当有运算数提供使用时，该模式才释放时钟脉冲信号。只有当数据发送器不在每一个处理机时钟脉冲中提供数据，而是每到第n个时钟脉冲时提供数据，这一模式才特别有意义。其时，时钟脉冲对应标准时钟脉冲的一个周期，并经过rACK或oRDY(1/2)释放。释放被称为为“单冲”(OneShot)。这一模式被称为“单冲模式”。这种情况下，时钟脉冲经过一“与”门用释放信号之一进行“与”运算。模式和信号的选择经过F-PLUREG进行。经过rACK或oRDY(1/2)生成的释放信号可由SM-UNIT(状态机部件)延长。这是必要的，以便于需要一个以上时钟脉冲的运算能在单冲模式下执行。为了能够如此，SM-UNIT的相应的信号线路要用释放信号进行“或”运算处理。
如果寄存器记录STOP放在F-PLUREG中，则Sync-UNIT引导运行的功能结束。尔后，再没有其它的运算数被接受和认收。一旦rACK指示结果已被数据接收机接受，则PLU的重新配置准备状态通过信号ReConfig说明。通过将F-PLUREG的“停止”存入一D触发器(D-Flip-Flop)，即生成这一信号。ReConfig可以通过在F-PLUREG上在“停止”的位位置上对PLU的一次读数访问进行查询。
同样，Sync-UNIT可用来生成事故状态或其它状态信号，并进行处理。
2.2.7 BM-UNIT
为了将运算数和结果接到外部总线系统上，设有一总线多路转换部件(BM-UNIT)。这个BM-UNIT由两个多路转换器和2个门组成，其中，两个多路转换器是运算数多路转换器(O-MUX)，两个门电路是结果门(R-GATE)，同时，高值和低值结果分别各使用一个开关。多路转换器和开关经过多路转换器寄存器({M-PLUREG})进行控制。Sync-UNIT信号经过开关到总线上进行控制。如此，多路转换器/开关和信号的密切关系如下：O-MUX1：    oRDY1，oACKO-MUX2：    oRDY2，oACKRH-GATE：   rRDY，rACKhRL-GATE：   rRDY，rACK1
结果门R-GATE可以经过M-PLUREG进入一种不激励总线系统的状态。
下表给出信号的说明及其有关的接口结构：
    信号     oRDY     OACK     rRDY   rACK  D7..0
  表示的内容   运算数准备就绪 运算数被认收 结果准备就绪 结果被认收 数据
  类型   输入 集电极开路 激励器 输入 双向的
有可能从一个数据发送器出发去询问多个数据接收机(广播通信)。为此，要把多个数据接收机接到同一根总线上。为了保证数据的认收，将认收线路的激励器级oACK设计成集电极开路激励器。这样，总线作为线“与”电路(wired-AND)工作，也就是说，当所有数据接收机都认收时，才出现认收所要求的H电平。要做到这一点，每一个没有认收的数据接收机都要经过一个集电极开路晶体管将总线降低到L电平。认收的数据接收机不控制集电极开路晶体管，因而不给总线加载。当所有的数据接收机认收时，总线便不在被加载，并经过一个上拉电阻接受H电平。
2.2.8 StateBack-UNIT(状态信号返回部件)
阵列处理机能把关于经过其运行状态的回答信号提供给它的逻辑装入部件(以下简称为PLU)(比较DE 44 16 881 A1)。逻辑装入部件配置PA，并需要有关每一个阵列处理机状态的信息，以便能进行合理的重新配置。为此，需要经过StateBack-UNIT(状态信号返回部件)。这一部件或者根据F-PLUREG中的记录传送R-REGsft中结果的低3位(为了把计算值提供给PLU)，或者把信号CarryOut-AlessB和AequalB-Odetect传送到一3位状态总线。为了能从多个阵列处理机接通信号，采用了经过集电极开路激励器的简单线“或”电路技术。为了能在接收机认收数据后才开始重新配置阵列处理机，可以在信号与集电极开路激励器之间跨接一个锁存器级，该锁存器级在输入rACK之后才释放信号。状态总线由PLU监视。PLU在它的程序流中和它的重新配置中对由总线提供的状态作出反应。
2.2.9电源装置
阵列处理机具有一种省电模式({休眠方式})，省电模式如同EALU在F-PLUREG中的功能一样进行调整。为此备有一个位，当它被置放时，即接通休眠方式。这样，阵列处理机的时钟脉冲电路或者被置于恒定的逻辑0或1，或者经过一个晶体管切断阵列处理机的电压。F-PLUREG在阵列处理机内始终通电，而且是不能断开的。每次执行功能时没有使用的阵列处理机区段(门电路)通过充分利用F-PLUREG而断开。这种情况经过一个将区段与供电部分分离的晶体管而发生。为了防止不希望发生的干扰影响，区段的输出经过上拉/下拉电阻加以限定。
另外，在由Sync-UNIT控制的“单冲模式”内，可以使用省电方式。这种情况下，除F-PLUREG、M-PLUREG和Sync-UNIT以外，阵列处理机的所有部件都与电源分离。只有当Sync-UNIT确定一个“单冲”时，所有需用的阵列处理机部件才经过电源装置接通。Sync-UNIT延迟时钟脉冲信号一定的时间，直到所有新接通的部件都能工作为止。
2.2.10寄存器
寄存器F-PLUREG和M-PLUREG与PLU总线相连接。由PLU发送的数据包的地址在一比较器中被解码。如果阵列处理机的地址被识别，则数据存入寄存器。PLU总线被设计成如下：AX7..0：X/Y矩阵的X地址AY7..0： X/Y矩阵的Y地址RS：     寄存器的选择，逻辑0选定F-PLUREG，逻辑1选定M-PLUREG。AEN：    地址启动，总线包含一有效地址。只要AEN是逻辑0，地址必须解
     码。AEN在整个总线访问过程中，即在数据传送过程中为逻辑0。D23..00：数据DEN：    允许数据传送，总线含有有效数据。在信号DEN的脉冲前沿上升
     时，数据必须传送到寄存器中。OEN：    允许输出，PLU从诸PLUREG中读取有效数据。
2.2.11 F-PLUREG的结构
1.写入访问时寄存器的结构
  F11   F10..9     F8     F8     F5     F4..0
  Stop(停止)   StateBack(状态信号返回)   Sleep(休眠)   OneShot(单冲) PowerSave(省电) EALU function(EALU功能)
各个位的功能
功能 状态 作用
Stop(停止) 0 正常功能
1 停止运行周期后的功能，没有认收运算数。
StateBack(状态信号返回) 00 没有回答信号，总线开路
01 D2..0在总线上
10 CarryOut-AlessB，AequalB-Odetect在总线上
11 非法
Sleep(休眠) 0 没有功能，无电压
1 正常功能，有电压
OneShot(单冲) 00 正常功能
01 OneShot在oRDY1上
  10   OneShot在oRDY2上
  11   OneShot在(rACKh & rACK1)上
  PowerSave(省电)   0   无省电
  1   与OneShot相连接的省电方式
  EALU function(EALU功能)   00000   没有运算(NOP)
  00001
  ...   与执行EALU适应的功能
  11111
复位状态在各个位都是0。
2.读出访问时寄存器的结构
  F11
  ReConfig(重新配置)
各个位的功能
  功能   状态     作用
ReConfig(重新配置)     0     不能进行重新配置
    1     能进行重新配置
复位状态在各个位都是0。
M-PLUREG的结构
M23..18     M17..12     M11..06     M05..00
    结果高值     结果低值     运算数1     运算数0
值M(n+5)..n＝000000，n∈{0，6，12，18}意味着多路转换器/开关是开放的，并且没有母线接点。经过信号ReConfig阻断M-PLUREG可能是有意义的，就是说，一旦ReConfig被激活，阵列处理机就与所有的总线系统断开。
复位状态在各个位都是0。
3.总结
通过把配置数据缩减到F-PLUREG可以比用已知技术，特别是比用FPGA技术更简单和更迅速地配置和重新配置阵列处理机的功能。在M-PLUREG中确定运算器的联网，而在传统的技术中必须占有大量单一的和不相关联的配置位。通过寄存器清晰的结构简化了(重新)配置。
由于直接设计成运算器，阵列处理机的空间需求比用传统技术要小，因为传统技术中运算器是通过大量的逻辑部件实现的。同时，运行时滞也缩短了，可达到的时钟脉冲频率也相应地提高了。
广播通信功能由于BM-UNIT的设置而得到了保证，认收是自动进行的。通过输入和输出端的寄存器(O-REG，R-REG)，在很大程度上与时间无关的数据传送得到了保证。
由于经过寄存器O-REG和R-REG将每一个阵列处理机与整个系统脱开，配置和重新配置得到了简化，这是因为每一的单一的阵列处理机在很大程度上是互相独立的。给PLU的回答信号以及STOP(“停止”)和ReConfig(重新配置)联合作用，使得对(重新)配置的有效控制成为可能。
实现了省电功能，省电功能—部分自动地(单冲模式)—导致了功率消耗的减少。
为了提高FPGA在其结构体系上的有效性，可以实施阵列处理机结构。这样可大大提高算术运算的能力。
4.对附图的简要说明图1 将多个阵列处理机排列成一个具有PLU(逻辑装入部件)的PA(处理阵列)
的布置图，没有连接到输入/输出系统或存储器。图2 一阵列处理机的结构图。图3 F-PLUREG和M-PLUREG的结构图。图4 一O-REG的结构图。图5 一具有右移位功能的O-REGsft的结构图。图6 一具有1-2右/左位桶形移位器的O-REGsft的结构图。图7 R2O-MUX以及利用传输门技术执行一MUX的结构图。图8 时钟脉冲同步、延迟和同步信号图。图9 Sync-UNIT的工作原理图。说明。图10电源装置的结构图。图11Sync-UNIT的结构图。图12BM-UNIT的结构图。图13一O-MUX的结构图，限定到4个总线系统。图14一R-GATE的结构图，限定到4个总线系统。图15StateBack-UNIT的结构图。图16单冲模式和单冲/省电模式的功能原理图。图17一阵列处理机的实施例图。图18一阵列处理机的结构图，其中各个单一功能的连接是通过一总线系统实
现的。图19一配置状态机的工作原理图。图20一循环状态机的工作原理图。图21配置寄存器数据的循环处理图。
4.1附图的详细说明
图1表示一经过简化的根据DE 44 16 881 A1的处理机。其中示出了PLU(0101)及其总线系统(0102)。各个阵列处理机(0103)都是作为阵列装入的，芯片上的总线(0104)是按示意图表示的。
图2所示为一阵列处理机的示意结构图。芯片上的总线(0201)被引到BM-UNIT(0202)上，BM-UNIT再将通过M-REG(0203)选定的总线继续接到作为运算数1的O-REGlsft(0204)和作为运算数2的O-REG(0205)。在运算数2的数据通路中有选择地经过R2O-MUX(2026)并入存放在结果寄存器R-REGsft(0207)中的结果。来自O-REGsft(0204)和R2O-MUX(2026)的数据在ELAU(2028)中进行处理。回答信号经过StateBack-UNIT(2029)传给PLU。PLU总线(0210)与寄存器F-PLUREG(0211)和M-PLUREG(0212)以及StateBack-UNIT(0209)连接。经过该总线配置和监视阵列处理机。F-PLUREG包含所有的功能配置数据，M-PLUREG包含阵列处理机的联网信息。Sync-UNIT(0212)控制数据接收机、数据发送机与处理阵列处理机之间数据交换的联合作用。SM-UNIT(0213)控制阵列处理机的整个内部过程。电源装置Power-UNIT(0214)调节供电和管理功率消耗。
图3说明寄存器M-PLUREG和F-PLUREG的工作原理。只要AEN(地址启动)显示有一有效的总线传送，PLU总线(0308)的地址AX和AY节就在一比较器(0301)中与阵列处理机的地址进行比较。其时，每一个阵列处理机占有一个唯一的地址，该地址是由它在一PA内的行和列组合而成的。如果DEN(允许数据传送)显示数据传送，则经过RS(寄存器选择)或者选定M-PLUREG(0302)，或者选定F-PLUREG(0303)。当DEN的脉冲前沿上升时，数据被存储到有关的寄存器中。寄存器作为D触发器(D-Flip-Flop)(0304)执行。时序图0305用来说明运行过程。要在F-PLUREG上进行读出访问，只需经过门电路(0306)由Sync-UNIT把信号ReConfig传给PLU总线。通路发生于比较器(0301)“与”信号OEN的结果。
图4a表示O-REG的方块图。在图4b中可以看出源于D触发器(D-Flip-Flop)的O-REG的构造。图4c表示时序图。时钟脉冲由SYNC-SM产生。
图5a表示O-REGsft的方块图。在图5b中可以看出源于D触发器(D-Flip-Flop)的O-REGsff的构造。“与”门电路和“或”门电路经过变换电路(0504)构成一个由模式控制的多路转换器(0506)，该多路转换器或者将输入数据接到D触发器(D-Flip-Flop)(0501)，或者将D触发器(D-Flip-Flop)的输出引动一位后传导到它的输入上。“与”门电路(0505)是不必要的，因为有一输入永久地处在逻辑0上。它仅用于直观的目的。在图5c中说明时序图于信号模式的关系。时钟脉冲是由SYNC-SM生成的。
图6a表示R-REGsft的方块图。寄存器(0601)之前是一多路转换器(0602)，该多路转换器或者将输入数据接到寄存器(0601)，或者将寄存器(0601)的输出数据移位后输送到起输入端。由SYNC-SM生成的时钟脉冲移位半个节拍后输送到寄存器。在图6b中示出了门电路层面上的方块图。经过一个解码器(0603)，Mode0-2接通由“与”门电路与串接的“或”门电路构成的多路转换器(0606)。其中，用虚线画出的门电路(0605和其它)只是为了说明的目的才画上的。这些门电路没有功能，因为输入始终在L上。多路转换器在Mode0-2＝010的状态下将输入信号接到寄存器(06067)。寄存器(0607)的输出值在Mode0-2＝000到Mode0-2＝001的状态下和在Mode0-2＝011到Mode0-2＝100的状态下分别向左和向右移动一到两个位后，输送大寄存器的输入端。移位功能与Mode0-2状态的关系在图6c中说明。
图7a表示多路转换器R2O-MUX的结构，该多路转换器根据与模式的相关性将运算数和结果接转到EALU。这种情况下，图7a是作为传动的多路转换器构成的，而图7b所示则是因采用CMOS传输门(0701)而节省空间和功率的变体。本文件中描述的所有多路转换器都可以利用传输门构成。
门电路可以设计得与由传输门构成的多路转换器等效。但数据交换的方向则恰好相反！
图8表示阵列处理机内部的时钟脉冲CLR与正在进行的活动的关系。当脉冲前沿上升(0801)时，运算数储存到O-REG中。在H电平(0802)时，阵列处理机处理数据(ΔPAE＝处理相位)。这包括O-REG与R-REG之间的数据交换。当脉冲前沿下降(0803)时，结果存储到R-REG中。L电平(0804)被应用于包括在总线系统中的BM-UNIT(ΔNetwork(网络)＝总线相位)。由SYNC-SM生成的信号(oRDY和oACK，tRDY和rACK)随时间的变化记录在时序图中。
Sync-UNIT的流程图示于图9中。状态机识别两种固定状态“数据”(0901)和“结果”(0902)。“数据”被整步到上升的脉冲前沿，“结果”被整步到下降的脉冲前沿。同时，输入参数的状态被分别处理，并根据结果跳跃到支路“是”(0903/0904)或“否”(0905/0906)。如果在“数据”中运算数没有准备就绪，则跳转到“否”。下面的步骤中没有操作被执行，直到机器向“数据”回跳，并重新处理。如果操作数准备就绪(通过oRDY显示)，则操作被存储在O-REG(0907)中。操作数被处理(0908)，同时被评定(0909)，确定在多循环操作(需要多于一个时钟脉冲循环的的串行操作)情况下关键是否在最后一个循环，或者是否是一个单循环操作在运行。在这种情况下运算数通过oACK认收(0910)。脉冲前沿下降时，“结果”被整步。这时是检查是否安放了“结果存在”标志(0911)。当完成的结果通过rRDY发送信号时(0912)，总是安放这一标志。在两种情况下跳跃到“是”支路(0904)：
1.没有先前的结果存在(标记“结果存在”不真实)。
2.有先前的结果存在(标记“结果存在”真实)，并且这一结果用rACK认收。在这种情况下(并且只有在这种情况下！)0902将结果复位(0913)。
否则跳跃到“否”支路(0906)，并且没有操作被执行，直到状态机向“结果”(0902)返回。在“是”支路(0904)，结果存储到输出寄存器R-REGsft((0914)。然后判断关键是否在一个多循环操作的最后一个循环(0915)(比较0909)，或者是否是一个单循环操作在运行。如果是。通过rRDY发信号表示结果的存在(0916)。状态机向“数据”(0901)回跳。识别关键是否在最后一个循环(或者是否是一个单循环操作在运行)，可以由SM-UNIT经过信号FINISH(“完成”)(0616)询问。当最后一个(或唯一的一个)循环发生时，该信号有效。SYNC-UNIT的状态经过RUN(“运行”)停止SM-UNIT。在有一操作发生的情况下，“运行”有效，否则无效。F-PLUREG中STOP(“停止”)项的机理以及由此生成的ReConfig(“重新配置”)的机理在图9中没有表示出来，因为运行过程出现，而且可从对SYNC-UNIT的说明中推知。
图10表示电源装置的基本结构。信号“休眠”由F-PLUREG传导到一个晶体管或一个晶体管级(1001)。该晶体管级控制所有可断开的元件功能的供电。Sync-UNIT(同步部件)提供单冲省电信号(比较图16)，经过该信号，通过一个晶体管或一个晶体管级(1002)释放剩余元件功能的供电。根据元件中实际应用的功能，晶体管或晶体管级(1003)断开不需要的功能(掉电)。显然，对于正规的供电和电磁容量特性，必须采取其它相应的预防措施，例如电容器等。
图11所示是机器从图9到设计的实现。经过BM-UNIT(1101)，信号oRDY(1/2)和rACK(简化表示，实际存在的是rACKh和rACK1，rACK＝rACK1 & rACKh)被接到中央时钟(CCLK)控制的锁存器(1102)。其中，锁存器的电路这样的，即锁存器在中央时钟的低相位(总线相位)下是透明的，而在高相位下保持状态。锁存器的输出提供信号供同步状态机(1103)使用。1103的rRDY(简化表示：实际存在的是rRDYh和rRDY1，两者完全相同，但被传导到不同的接收机)经过门电路接到总线。1103的信号oACK(1/2)在BM-UNIT(1101)中被否定，并提供给重新反相的集电极开路总线激励器(1104)。总线经过电阻(1105)被拉到H。此时BM-UMIT被接通，发生下面的情况：
1.如果相应的总线不受BM-UNIT控制，则L是在晶体管(1104)的基极上。因此，晶体管不给总线加载。
2.如果相应的总线受BM-UNIT控制，而且信号不被认收，则H是在晶体管(1104)的基极上。这意味着总线被拉到L。如果每次广播通信的结果被分配给多个接收机，则尚未认收结果数据和需要等待循环的所有阵列处理机将总线拉倒L。
3.如果相应的总线受BM-UNIT控制，而且信号被认收，则L是在晶体管(1104)的基极上。这意味着总线不被加载。如果每次广播通信的结果被分配给多个接收机，则已认收结果数据和不需要等待循环的所有阵列处理机不给总线加载。
由于总线在其基本状态接受H电平，也就是接受认收，则根据总线被拉到L的情况2，不认收的负载超过认收。这种情况下，只有当所有阵列处理机认收时，总线才走入H电平，即走入认收状态。这样便实现了一个线“与”电路(Wired-AND-Schaltung)。同步状态机将信号RUN(1107)提供给SM-UNIT(1106)使用。后者根据RUN启动。如果SM-UNIT处在一处理过程的最后一个(或唯一的一个)循环中，则它就将该信号经过FINISH(1108)发给同步状态机。FINISH在估算部件中进行计算，以识别最后一个循环(0907，0915)。SM-UNIT与阵列处理机内部时钟脉冲CLK同步运行。
图12表明BM-UNIT的结构。根据输入到M-PLUREG中的项，多路转换器(1201，1202)把运算数从内部总线(1203)接到O-REG。同样，门电路(1204，1205)把结果的下半部分和上半部分接到总线。多路转换器1026分别根据1201和1202的位置把oRDY(1/2)和根据1204和1205的位置把rACK从总线接入阵列处理机。此时，两个数据接收机的rACK互相进行“与”运算。如果只存在一个数据接收机，则多路转换器这样进行连接，即它送回一个逻辑1取代缺少的rACK。1207包括一个把信号oACK(1/2)和rRDY接到总线上的门电路。其中信号oACK(1/2)首先进行反相，然后经过集电极开路激励器(1104)接到总线上。
图13说明一O-MUX的结构。其中有一个3∶5解码器(1301)处理来自M-PLUREG的Mode2..0信号。多路转换器经过“与”门电路(1302)采用串接的“或”门电路(1303)构成。解码器(1301)的Mode2..0＝000的求值信号被直接接到“或”门电路(1304)。这样造成的结果是，在开路状态，即没有连接到总线时，始终是逻辑1被反馈。(比较图12的rACK)。为了简化起见，只示出了缩减的总线尺寸。
图14说明一R-GATE的结构。其中有一个3∶4解码器(1401)处理来自M-PLUREG的Mode2..0信号。解码器的Mode2..0＝000的求值信号没有被使用。因此，在这一位组合中没有建立总线连接。门电路(1402)或者由有“与”门电路构成，或者由传输门电路(比较0701)构成。这种情况下，在前或在后串接一放大级以驱动总线负载。为了简化起见，只示出了缩减的总线尺寸。
StateBack-UNIT(状态信号返回部件)示于图15。根据在N-PLUREG中的设定，一多路转换器(1501)或者连接EALU的信号CarryOut-AlessB，AequalB-Odetect，或者连接R-REG R-REGD2..0的输出。信号到达一集电极开路晶体管级(1502)，并被接到PLU总线上。这里，PLU总需要若干外部的、位置靠近PLU的上拉电阻(1503)。锁存器1504是可选件。如果把它闭合到1501的输出信号中，则在数据接收机经过rACK认收数据后，把该输出信号接到总线(1503)上；这样造成的结果是，只有当数据被接受后，进行重新配置准备就绪的状态才经过状态信号显示出来。通常，这需要通过STOP(“停止”)和ReConfig(重新配置)联合作用在Sync-UNIT中进行调节；因此，锁存器是可选件。这种情况下，rACK被当作锁存器时钟脉冲使用。这时锁存器在rACK＝1时是透明的，在rACK＝0被存储。
图16表明OneShot-MODE(单冲模式)的工作方式。经过一个多路转换器(1601)，根据F-PLUREG中的设定，信号
1.Vcc
2.oRDY1
3.oRDY2
4.(oRDY1 & rACK)
脱开部件时钟脉冲。经过Vcc脱开造成的结果是时钟脉冲始终在运行(见时序图“正常运行”)。
在其余3个模式下，只有当信号或信号组合释放时钟脉冲时，时钟脉冲才开始运行。释放由时钟脉冲CCLK上的一个锁存器(1602)进行整步，以便当释放信号短促时，相位不提前中断。这种情况下，锁存器在CCLK的低相位下是透明的，在高相位下保持其值。释放信号到达“与”门对(1603和1604)，“与”门对释放时钟脉冲。经过一个反相器(1605)产生反相的时钟脉冲信号为了保证！CLK同相，CLK通过一个延迟元件(1606)运行(见时序图“单冲运行”)。这时，CCLK在通往1604的引线中经过两个延时时限(1610)被延迟，以保证与邻近1603的、被多路转换器(1608)延迟了的CCLK同相。如果在省电模式中插进了一个阵列处理机，则元件的供电电源在很大程度上被断开。这种情况是经过“或”门电路1161而发生的。如果接通省电模式，即PowerSave＝1，则产生反向信号L。如果这时接通单冲模式，并让寄存器1602在L上，则经过一个单冲省电信号断开电源装置上的供电晶体管(比较图17)但是，如果寄存器1602在逻辑1上(或PowerSave＝0)，则供电晶体管经过1611接通。下表对功能加以概述：
  省电   锁存器(1602)   电压     备注
  L     X   通
  H     L   断     只有当使用单冲模式时
    H     H   断
在接通电源时出现一规定时间的苏醒时间，直到元件能工作为止。但为了正常地发挥功能，信号必须相应地延迟。为此，经过延迟线路(1607)引导CCLK。一多路转换器(1608)根据信号PowerSave相应地选择是向元件传送标准时钟脉冲还是延迟时钟脉冲传。如果要延迟时间间隔S\DeltaSPowerOn，只能选择非反向时钟脉冲，反向时钟脉冲不延迟。这样，可提供使用与其余部件功能的同步的结果。借此，可利用的处理时间减小到Δprocess。部件的最大时钟脉冲频率取决于ΔPowerOn+Δprocess。(见时序图“OneShot Betrieb mit PowerSave”“单冲运行带省电”)。
图17表示阵列处理机的一实施例。图中，BM-Unit、电源装置、StateBack-Unit、Plu总线和M-PLUREF没有表示出来。
阵列处理机拥有三个供有待处理数据使用的输入寄存器oREG1(1701)、oREG2(1702)和oREG3(1703)。输入寄存器经过前导诸阵列处理机的BM-Unit得到其数据。所有输入寄存器都是没有移位功能的寄存器。
P-PLUREG(1704，1705，1706)决定一批阵列处理机的配置。它们由PLU经过PLU总线装入。它们分别存入一种经过多路转换器(1723)选定的配置。多路转换器(1723)受寄存器(1724)控制。寄存器(1724)从一前导阵列处理机通过BM-Unit得到数据或触发器。该阵列处理机与提供输入寄存器的诸阵列处理机不是等同的。当然，数量较大或较小的F-PLUREG也是可以想象的。
第三个输入寄存器oREG 3(1703)提供乘法和加法功能的运算数。其中，oREG1(1701)的内容与oREG2(1702)的内容在一乘法器(1709)中相乘，紧接着，在加法器/比较器(1718)中加上oREG3(1703)的内容。其中，加法器/比较器是按照执行一次相加进行配置的。如果只需执行一次相乘，则oREG3(1703)装入“零”值。如果只需执行一次相加，则P-PLUREG转换位乘法器(1711)。这样，oREG1(1701)的值直接达到加法器/比较器(1718)。加法器/比较器(1718)的第二功能接受oREG1(1701)的值和oREG3(1703)的值，并比较该两个值。输出信号CarryOut-AlessB和AequalB-Odetect(1719)显示两个值是否相等，或oREG3(1703)的值大于或小于oREG1(1701)的值。
在阵列处理机中实现的其它功能有：一个移位寄存器(1712)，一个除法器(1713)，诸如“与”、“或”、“非”等逻辑功能(1714)以及一个计数器(1715)。一旦计数器(1715)从一个前导值数到零，它就产生一个激发器信号(1720)。计数器(1715)直接装入oREG3(1703)得到的值。也可以想象插入其它的计数器，如从零数到被装入值的，然后产生一个激发器信号的上行计数器。
功能部件的结果通过提高多路转换器(1716)继续传送到两个输出寄存器rREG1(1710)和rREG2(1717)，这两个输出寄存器与BM-Unit连接，数据继续走向后续的各个阵列处理机。运行过程由一个与触发器逻辑电路(1707)连接的Sync-Unit(1708)控制。此外，它还与配置状态机交换控制信号，这些控制信号在通过多路转换器(1723)改变配置时保证正确运行。触发器逻辑电路(1707)与F-PLUREG连接，并根据存储在F-PLUREG中的配置处理进入的信号(1722)。进入的信号包括ReConfig(重新配置)，普通的触发器信号，以及同步交换信号oRDY和rACK。根据配置情况，触发器逻辑电路(1707)继续把同步交换信号传送给Sync-Unit(1708)，后者又产生输入和输出寄存器以及计数器的启动信号。此外，Sync-Unit(1708)产生进入的同步交换信号oACK和rRDY，它又把这些信号在传送给触发器逻辑电路(1707)。根据配置情况，信号(1719)或计数器(1720)的触发器可以作为普通的触发器信号使用，并传送给触发器逻辑电路(1707)。从给触发器逻辑电路(1707)输出的是信号(1721)，ReConfig(重新配置)，同步交换oRDY和rACK，以及普通的触发器信号，这些信号重又输送给BM-Unit。
图18所示为与图17中所述阵列处理机具有同样功能范围的一个阵列处理机。这里同样没有表示出BM-Unit、电源装置、StateBack-Unit和M-PLUREF。它由三个输入寄存器oREG1(1801)、oREG2(1802)和oREG3(1803)，两个输出寄存器rREG1(1804)、oREG2(1818)，三个F-PLUREG(1813，1814，1815)，一个Sync-Unit(1805)的多路转换器(1818)和一个触发器逻辑电路(1806)组成。功能部件有一个除法器(1808)，一个乘法器(1817)，一个加法器/比较器(1809)，逻辑功能(1810)，一个移位寄存器(1811)和一个计数器(1812)。各个部件的功能与图17所述相对应。也可以设想在阵列处理机中集成其它一些功能，诸如三角函数，方根和指数函数。这当然也适用于图17所述的阵列处理机。每一个功能都是可作为整数和浮点部件实现的。与图17中的阵列处理机不同，每个功能部件都经过总线系统(1816)互连，因而各个功能都可以按任意的顺序互相连接。接线是由在F-PLUREG中所作的配置决定的。总线系统(1816)可以用不同的方式构成。可以是分成一个或多个分段的总线，它的各个分段各自连接两个相互接线的功能；或者是若干贯穿的总线，分别使两个功能部件互连。另外还有这样的可能，即每一功能部件和寄存器各分出一个目标地址，借助这些目标地址建立联系。
图19所示为一管理配置寄存器的配置状态机。开始时，配置状态机处于IDLE(“空闲”)状态(1901)。当出现一个由配置寄存器选定的配置阵列处理机的rRDY信号后，才放弃这种状态。尔后，配置状态机过渡到停止状态(1902)，并发送一个停止信号给阵列处理机的Sync-Unit(同步部件)。阵列处理机到下一个时间点结束其操作，并发送一个停止认收信号给配置状态机，过渡到Reload状态(1903)，并发送一个启动信号给配置阵列机的寄存器。配置状态机过渡到再启动状态(1904)，并发送一个启动信号给Sync-Unit，Sync-Unit再接受其处理。同时，它发出一个rACK信号给配置阵列处理机。最后，配置状态机再跳跃到“空闲”状态(1901)。
图20所示是自动运行阵列处理机不同配置的一状态机，下面简称为环路状态机。由于存在着多个F-PLUREG，因此，依次执行多个操作，接着再把数据以及触发器信号和同步交换信号送到后面的阵列处理机，也许是很有意义的。
每次操作的结果有阵列处理机的rREG经过已作过说明的反馈返回输入寄存器。这一过程可以经过一个部件由一外部停止环路信号或一内部寄存器进行控制。
开始时，环路状态机处在“空闲”状态(2001)。在“空闲”状态(2001)，环路状态机发一个复位信号给一计数器。该计数器的作用是选择F-PLUREG。根据前导阵列处理机的输出信号rRDY，环路状态机过渡到配置状态(2202)。这时，它产生同步信息交换信号给阵列处理机和控制信号给配置状态机。此外还为计数器产生启动信号，其值提高1。如果环路状态机没有得到停止环路信号，或者阵列处理机的内部计数器没有达到其最终值，则环路状态机仍停留在配置状态(2002)，并重复前面描述的过程。当出现一停止环路信号或当阵列处理机的计数器达到了其最终值时，环路状态机返回带“空闲”状态(2001)，rRDY信号传导给后面的阵列处理机。
图21表明顺序执行存储在F-PLUREG中配置所需要的阵列处理机部件。F-PLUREG(2104)从PLU(2107)它的数据，并且与前面所述的结构形式相比，作了某些改进。每一个F-PLUREG包括一个附加位，即所谓的环路位(2106)。该环路位通过连接线路(2112)返回到图20中所描述的环路状态机(2101)中。它在此处充当停止环路信号，就是说，当入环路位(2106)时，环路过程停止，否则它继续被引导，直到环路位被放入，或者图20中所描述的环路状态机(2101)的内部计数器达到了它的最终值。环路状态机(2101)控制计数器(2102)，它的值通过多路转换器(2105)控制F-PLUREG(2104)的选择。配置状态机的控制信号和阵列处理机的同步交换信号通过连接线路(2113)进行传输。F-PLUREG的配置数据经过连接线路(2108)继续发送到阵列处理机的功能部件。
计数器(2102)获得启动信号(2110)，因而计数器(2102)的值提高1。此外，一旦环路过程结束，环路状态机(2101)就发一个复位信号(2111)给计数器。经过多路转换器(2103)，可在阵列处理机中的环路模式与正常运行之间进行挑选。在正常运行时，多路转换器(2103)发送一挑选F-PLUREG(2104)的日期(2109)给多路转换器(2105)。
5定义AequalB-    由EALU产生的信号，在算术运算时，该信号显示结果为零。在比Odetect     较时显示运算数A等于运算数B。ALU         算术逻辑部件。数据处理基本部件。这个部件可进行算术运算，如
        加、减，有时也有乘、除、级数展开等。这个部件也可作为整数
        (integer)部件或作为浮点(floaring-point)部件接入。这个部件同样可进
        行逻辑运算，如“与”、“或”以及比较。BM-UNIT     把数据接通到阵列处理机外总线系统上的部件。接通是经过数据输
        出端的多路转换器或数据输入端的门电路实现的。oACK传导被作
        为集电极开路激励器执行。BM-UNIT通过M-PLUREG进行控制。广播通信    发送阵列处理机的数据给多个数据接收机。CarryOut-   由EALU产生的信号，在算术运算时，该信号显示一次进位。在比AlessB      较时显示运算数A小于运算数B。数据接收机  阵列处理机的结果继续被处理/继续工作的部件。数据发送机  提供数据供阵列处理机使用的部件。D触发器     存储元件，它储存时钟脉冲前沿上升的信号。EALU        扩充算术逻辑部件。被扩充特殊功能的算术逻辑部件ALU，被扩充
        的特殊功能是根据DE 441 16 881 A1运行数据处理装置所必需的或
        有意义的。这属于特殊计数器。FPGA        可编程逻辑部件。当前技术水平。F-PLUREG    放入阵列处理机功能的寄存器。同样还放入单冲和休眠模式。寄存
        器由PLU描述。门电路      执行逻辑基本功能的晶体管组。基本功能包括例如“与非”，“或
        非”，传输门。H电平       逻辑1电平，取决于所采用的技术。同步交换    信号协议，其中信号A显示一种状态，另一信号B证实它接受信号
        A，并作出反应。配置        规定一逻辑部件、一(FPGA)元件或一阵列处理机的功能和联网(比较
        “重新配置”)。锁存器      存储元件，一般它在H电平时透明传导信号，在L电平时存储信
        号。在阵列处理机中部分地使用锁存器，在这种锁存器中电平的功
        能恰好相反。所以在一普通锁存器的时钟脉冲前插入一反相器。L电平       逻辑0电平，取决于所采用的技术。M-PLUREG    放入阵列处理机功能的寄存器。寄存器由PLU描述。下一个邻点联总线系统与在边缘邻接的邻点的联网。网O-MUX       在BM-UNIT内选择运算数总线系统的多路转换器。单冲        阵列处理机以一个比处理机时钟脉冲小的时钟脉冲工作的模式。时
        钟脉冲与处理机时钟脉冲同步，并对应一个周期。不存在相位移。
        时钟脉冲经过信号Ordy(1/2)或rRDY中的一个信号释放。当数据发
        送或接收机发送或接收数据比处理机时钟脉冲慢时，这种模式用于
        省电。集电极开路  电路技术，采用这种电路时，一晶体管的集电极上是一个经过上拉
        上升到H电平的总线信号。晶体管的发射极接地。如果晶体管被接
        通，则总线信号被拉到L电平。这种方法的优点在于，多数这样的
        晶体管能够控制总线而不发生电碰撞。其中信号经过“或”操作，
        出现所谓的线“或”电路。O-REG       运算数寄存器，用来存储EALU的运算数。允许阵列处理机在时间
        和能上独立于数据发送机。这样，数据的传输得到简化，因为可实
        现同步或包定向。同时还提供了独立于阵列处理机重新配置数据发
        送机和独立于数据发送机重新配置阵列处理机的可能性。O-REGsft    带有受SM-UNIT控制的移位寄存器的O-REG。PA          处理阵列：阵列处理机中的阵列。PAE         阵列处理机：配有O-REG、R-REG、R2O-MUX、F-PLUREG、
        M-PLUREG、BM-UNIT、SM-UNIT、Sync-UNIT、StateBack和
        电源装置的EALU。PLU         阵列处理机的配置和重新配置部件。由特别适合其任务的微控制器
        构成。省电模式    单冲模式内的省电模式。在不执行操作时，除F-PLUREG、M-
        PLUREG和Sync-UNIT外，不向所有其它部件供电。电源装置    调整省电功能的部件。下拉电阻    把一总线拉到L电平的电阻。上拉电阻    把一总线拉到H电平的电阻。R-GATE      BM-UNIT内它把结果接通到相应的总线系统上的开关。运行时有几
        个信号经过例如集电极开路激励器接通。R-GATE作为总线激励器
        工作，可进入一总线中性模式。R2O-MUX     将R-REGsft中的结构接入O-REG于EALU之间的数据通路的多路
        转换器。R-REGsft    结果寄存器，用于存储EALU的结果。允许阵列处理机在时间和能
        上独立于数据接收机。这样，数据的传输得到简化，因为可实现同
        步或包定向。同时还提供了独立于阵列处理机重新配置数据接收机
        和独立于数据发送机重新配置阵列处理机的可能性。寄存器设有移
        位功能，移位功能由SM-UNIT控制。串行操作    通过串行处理数据字或算法执行的操作。串行乘法，串行除法，级
        数展开。休眠模式    除F-PLUREG外阵列处理机不供电的省电模式。SM-UNIT     状态机部件。控制EALU的状态机。StateBack-  控制状态信号返回到PLU的部件。由一个多路转换器和一个集电极UNIT        开路总线激励级构成。Sync-UNIT   使阵列处理机的整步与数据发送和接收机同步，并监视阵列处理机
        的重新配置的部件。同时接受单冲功能。门电路      继续传导或阻止信号的开关。简单比较：继电器。重新配置    当任意数量的阵列处理机继续其持有的功能时，对其余任意数量的
        阵列处理机进行新的配置(比较“配置”)。状态机      可以接受各种不同状态的逻辑电路。状态之间的过渡取决于不同的
        输入参数。这种状态机用于控制复杂的功能和适应技术现状。
6约定
6.1名称约定
部件                     -UNIT
工作方式(模式)           -MODE
多路转换器               -MUX
反信号(否信号)           not-
可视PLU寄存器            -PLUREG
内部寄存器               -REG
移位寄存器               -sft
6.2功能约定移位寄存器    sft“与”功能    &
A  B  Q
 0  0  0
 0  1  0
 1  0  0
 1  1  1
“或”功能  #
A  B  Q
 0  0  0
 0  1  1
 1  0  1
 1  1  1
“非”功能  G
  A  Q
    0     1
    1     0
“门”功能  G
EN D Q
 0  0  -
 0  1  -
 1  0  0
 1  1  1

Claims (3)

1.在处理机(CPU)、多计算机系统、数据流处理机(DFP)、数字信号处理机(DSP)、脉动处理机和可编程逻辑部件(FPGA)中使用，由逻辑装入部件控制，对数字和逻辑运算进行处理，可配置并在运行时间可重新配置的阵列处理机(PAE)，其特征在于，
a)设有一个可编程计算装置(EALU扩充算术逻辑部件)，执行数学和逻辑基本功能，
b)计算装置的功能和联网在寄存器中编程，并能在无须对PAE重新编程的情况下处理大量数据，
c)为了控制计算部件装置(EALU)，有一状态机(SM-UNIT)存在，
d)分别为每一运算数和结果设有寄存器(分别是O-REG和R-REG)，这些寄存器可部分地充当移位寄存器使用，
e)结果寄存器的数据经过一多路转换器(R2O-MUX)反馈到一EALU的输入端，
f)一总线部件(BM-UNIT)允许总线系统的数据拾取，或结果向总线系统的馈送，同时，总线部件可将数据发送给多个接收机，并且，多个接收机自动实现同步，
g)总线访问经过寄存器与EALU中的数据处理脱开，每个PAE可视为独立的部件，特别是，一PAE的配置和重新配置对数据发送和接收机以及独立的PAE没有干扰性的影响，
h)数据传输过程经过一状态机(SYNC-UNIT)自动控制，为此有同步交换传输线路oRDY，oACK，rRDY和rACK提供使用，
i)信号返回到PLU，以识别PAE的处理和重新配置状态(StateBack-UNIT)，
2.根据权利要求1的装置，其特征在于，一PAE的数据处理可被停止(装入STOP于F-PLUREG内)，PAE在完成直接运行的数据处理后紧接着显示它准备进行重新配置的准备状态(ReConfig)。
3.根据权利要求1的装置，其特征在于有一省电模式存在，
a)在省电模式下，始终是只有当数据发送机的运算数已达到输入端，并且结果已被接收机接受时，PAE才工作；否则，PAE在没有时钟脉冲的情况下保持静态，
b)在PAE的某些与执行瞬时数据处理无关的子区间，与电源实行分离，
c)在PAE的某些子区间，PAE与电源实行分离。
总结
联系到在处理机(CPU)、多计算机系统、数据流处理机(DFP)、数字信号处理机(DSP)、脉动处理机和可编程逻辑部件(FPGA)中使用，由逻辑装入部件控制，对数字和逻辑运算进行处理，可配置并在运行时间可重新配置的阵列处理机(PAE)，提出以下配置建议：
提供一可编程的计算部件(EALU)执行数学和逻辑基本功能，其功能和联网在寄存器内编程，在寄存器内可处理大量数据，无须对PAE重新编程。
为了控制计算部件(EALU)，提供一状态机(SM-UNIT)；此外，分别为每一运算数和结果提供寄存器(分别为O-REG和R-REG)，这些寄存器可部分地充当移位寄存器使用。结果寄存器的数据经过一多路转换器(R2O-MUX)反馈到EALU的输入端。一总线部件(BM-UNIT)允许总线系统的数据拾取，或结果向总线系统的馈送，同时，总线部件可以向多个接收机发送数据，而多个接收机自动进行同步。
总线访问经过寄存器与EALU中的数据处理脱开，这样，每一个PAE可视为独立的部件，因此，一个PAE的配置和重新配置对数据发送和接收机以及独立的PAE不发生干扰性的影响。
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CN113986817B (zh) * 2021-12-30 2022-03-18 中科声龙科技发展（北京）有限公司 运算芯片访问片内存储区域的方法和运算芯片

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