CN1223465A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN1223465A
CN1223465A CN98108911A CN98108911A CN1223465A CN 1223465 A CN1223465 A CN 1223465A CN 98108911 A CN98108911 A CN 98108911A CN 98108911 A CN98108911 A CN 98108911A CN 1223465 A CN1223465 A CN 1223465A
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film
gate electrode
oxide
mask
gate insulating
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CN1173388C (zh
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小沼利光
张宏勇
菅原彰
铃木敦则
上原由起子
大沼英人
山口直明
须泽英臣
鱼地秀贵
竹村保彦
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Abstract

一种在绝缘衬底上形成的TFT,具有源、漏和沟道区,至少在沟道区上形成栅绝缘膜,并在栅绝缘膜上形成栅电极。在沟道区和漏区间设有电阻率较高的区,以降低截止电流。形成这种结构的方法包括:阳极氧化栅电极以在栅电极侧形成多孔阳极氧化膜;用多孔阳极氧化膜为掩模除去一部分栅绝缘膜,使栅绝缘膜伸出栅电极但不全盖住源和漏区。此后,进行一种导电型元素的离子掺杂。在栅绝缘膜下限定高电阻率区。

Description

半导体器件及其制造方法
本发明涉及一种半导体器件及其制造方法，特别是，本发明旨在解决形成在绝缘表面上的薄膜型绝缘栅场效应晶体管，该绝缘表面既可以是如玻璃的绝缘衬底的表面，也可以是如形成在硅圆片上的氧化硅的绝缘薄膜。具体地说，本发明可用于制造在玻璃衬底上形成的TFT(薄膜晶体管)，该玻璃的转变温度(也称为畸变点或畸变温度)为750℃或更低。
这种根据本发明制造的半导体器件可用于有源阵列器件，例如液晶显示或图象传感器的驱动电路，或用于三维集成电路。
众所周知，TFT用以驱动有源阵列型液晶器件或图象传感器。具体地说，不用具有非晶硅的作为其有源层的非晶TFT，而用已研制出的结晶Si TFT以获得较高的场迁移率。图6A-6F是横截面图，说明按先有技术的TFT的制造方法。
参看图6A，在衬底601上形成结晶硅的基底602和有源层603。并在该有源层上用氧化硅或其他同类物形成绝缘膜604。
然后由掺磷多晶硅、钽、钛、铝等形成栅电极605。用此栅电极作为掩模，通过适宜的方法，例如自对准方法中的离子注入将杂质元素掺入该有源层603，从而形成含有浓度比较低的该杂质、因而具有比较高的电阻率的杂质区606和607。此后本发明将这些区域606和607称为高电阻率区(HRD：高电阻率漏极)。位于不掺以杂质的栅电极之下的有源层区域是为沟道区。此后，用激光或例如闪光灯的热源将掺杂杂质激活。(图6B)
参看图6C，用等离子体CVD或APCVD(大气压CVD)形成氧化硅的绝缘膜608，继而进行各向异性腐蚀，在栅电极的侧表面毗连处留下绝缘材料609，如图6D所示。
然后用栅电极605和绝缘材料609作为掩模，用离子注入法或类似方法，以自对准方式再将杂质元素加入到一部分的有源层603中，形成一对杂质区610和611，其含有的杂质元素的浓度较高，并具有较低的电阻率。之后，再用激光或闪光灯(图6E)将杂质激活。
最后，在整个表面上形成层间绝缘体612，其中在源区和漏区610和611上形成接触孔。然后通过接触孔形成电极/布线613和614，和源区和漏区接触。(图6F)
上述制造过程是照抄常规半导体集成电路的老的LDD技术得到的，这种方法对于在玻璃衬底上的薄膜制造过程有一些缺点，讨论如下：
首先，需要用激光或闪光灯将加入的杂质元素激活二次。因此，生产率低。在常规半导体电路的情况下，可在杂质引进全部完成后用一次加热退火来激活杂质。
但在玻璃衬底上形成TFT的情况下，加热退火的高温，容易损伤玻璃衬底。因此需要使用激光退火或闪光灯退火。但这种退火对有源层的影响是有选择的。例如在绝缘材料609下面的有源层部分就未受到退火作用。于是，每次完成掺杂后应进行退火的步骤。
还有，形成绝缘材料609也是困难的。一般说来，绝缘膜厚0.5-2μm，而衬底上的基底膜602厚1000-3000。因此，存在着这样的危险，即在刻蚀绝缘膜608时，会无意地刻蚀基底膜602而使衬底需出。因为TFT的衬底含有许多对硅半导体有害的元素，故不能提高质量。
此外，也很难精确地控制绝缘材料609的厚度。各向异性刻蚀是由例如反应离子刻蚀(RIE)这样一种等离子体干式刻蚀完成的。然而由于使用了具有绝缘表面的衬底(这和半导体集成电路中的硅衬底不同)，因而难以精确控制等离子体，故绝缘材料609的形成是困难的。
因上述HRD必须做得尽可能薄，精确控制绝缘材料制造既有上述困难，也就难以批量生产质量均匀的TFT。而且需要二次进行离子掺杂，使生产过程变得复杂。
本发明的一个目的是要解决上述问题，并用简化的生产过程提供高电阻率区(HRD)的TFTb此处HRD不仅包括含有浓度较低和电阻率较高的杂质区，也包含电阻率较低的区域，这是因为，虽然掺杂的杂质浓度较高，但添加的元素可用以防止激活掺杂的杂质。作为这种元素的例子为碳、氧和氮。
根据本发明，栅电极的表面被氧化，且此氧化物层用以确定高电阻率区。该氧化物层由阳极氧化而成。和上述各向异性刻蚀比较起来，使用阳极氧化以形成氧化层有其优点，因为阳极氧化物层的厚度可以精确控制，而且可以形成薄至1000或更薄、厚至5000或更厚的均匀性极为优越的阳极氧化物层。
再者，本发明的另外特点是上述阳氧化层中有两类阳极氧化物，一类是势垒型阳极氧化物，另一类是多孔型阳极氧化物。使用酸性电解液时，可以形成多孔型阳极氧化物层。电解液的pH值低于2.0，例如在使用草酸水溶液时，pH值为0.8-1.1。由于是强酸性，金属膜在氧化期间溶解，生成的阳极氧化物呈多孔性。这种薄膜的电阻很低，致使膜的厚度得以较易增加。另一方面，使用弱酸或接近中性的电解液时，形成势垒型阳极氧化物。由于不溶解金属，生成的阳极氧化物致密且高度绝缘。形成势垒型阳极氧化物的电解液的pH值约高于2.0，最好高于3.0，例如在6.8和7.1之间。除了用含有刻蚀剂的氢氟酸外，势垒型阳极氧化物是不能被刻蚀的，而多孔型阳极氧化物可以用磷酸刻蚀剂，使用磷酸刻蚀剂不会损伤构成TFT的其他材料，例如硅、氧化硅。此外，势垒型阳极氧化物和多孔型阳极氧化物二者都很难用干式刻蚀剂刻蚀。特别是，这两种阳极氧化物相对于氧化硅来说都有足够高的刻蚀选择率。
本发明的上述特点使有HRD的TFT的制造变得容易。
图1A-1F是横截面视图，说明本发明实施例1的TFT的制造方法；
图2A-2F是横截面视图，说明本发明实施例2的TFT的制造方法；
图3A-3F是横截面视图，说明本发明实施例3的TTFT的制造方法；
图4A-4D是本发明的TFT的一部分的放大视图；
图5A和5B是使用本发明的TFT的有源阵列器件的电路衬底；
图6A-6F是横截面视图，说明先有技术的TFT的制造方法；
图7A-7F是横截面视图，说明本发明实施例4的TFT的制造方法；
图8A-8F是横截面视图，说明本发明实施例5的TFT的制造方法；
图9A-9F是横截面视图，说明本发明实施例6的TFT的制造方法；
图10A-10F是横截面视图，说明本发明实施例7的TFT的制造方法；
图11A-11F是横截面视图，说明本发明实施例8的TFT的制造方法；
图12A-12F是横截面视图，说明本发明实施例9的TFT的制造方法；以及
图13A-13D是横截面视图，说明本发明的阳极氧化生产过程。
参看图1A，在衬底101上制备基底绝缘膜102。在该基底绝缘膜102上形成包括结晶硅半导体的有源层103。本发明的“结晶半导体”包括单晶、多晶或半非晶半导体，其中至少部分含有晶体成分。此外，包括氧化硅或之类的绝缘膜104覆盖着有源层103。
再在绝缘膜104上，形成包括可阳极氧化材料的薄膜。可阳极氧化材料的例子为铝、钽、钛、硅等。这些材料可单独使用，或者使用它们中二或多个，以多层形式出现。例如，可以使用一种双层结构，其中硅化钛形成在铝上，或铝形成在氮化钛上。各层的厚度可按所需器件的性质确定。随后，将薄膜构图或刻蚀形成电极105。
然后参见图1B，在电解液中将电流加到栅电极105上，使之阳极氧化以在其上表面和侧表面形多孔的阳极氧化物106。就以本阳极氧化用的电解液而言，使用的是含3-20％的柠檬酸、草酸、磷酸、铬酸或硫酸的水溶液。所加的电压为10-30V，厚度为0.5μm或更厚。由于使用酸性溶液，如铝的金属在阳极化时被溶解，而生成的阳极氧化膜呈多孔性。又因为是多孔性结构，氧化膜的阻值是很低的，因此其厚度可用较低电压增加。当金属是两性金属时，在使用碱性溶液下，也可用相同的做法。
参看图1D，以阳极氧化膜106作为掩模，用干式或湿式刻蚀法刻蚀绝缘膜104。刻蚀作用可以继续到暴露出有源层的表面为止，或在有源层的表面暴露出之前就停止刻蚀。但鉴于生产率、产额和均匀性，最好将刻蚀继续到暴露出有源层的表面为止。在栅电极15和阳极氧化膜106下面的绝缘膜104的部分留下来作为绝缘膜104。在使用铝、钽或钛作为栅电极的主要组成，而栅绝缘膜104包含氧化硅时，使用含氟的刻蚀剂例如NF3和SF6作干式刻蚀是可能的。在这种情况下，绝缘膜104被快速刻蚀，而对氧化铝、氧化钽和氧化钛的刻蚀率足够小，以致可做到选择性地刻蚀绝缘膜104。
还有，在使用显式刻蚀的情况下，使用含氢氟酸的刻剂，例如1/100的氢氟酸是可能的。此时，因铝、钽和钛的氧化物的刻蚀率足够小，故也可以选择性地刻蚀氧化硅绝缘膜104。
刻蚀绝缘膜104后，除去阳极氧化膜106。作为刻蚀剂，可使用含磷酸的溶液。例如，一种由磷酸、醋酸和硝酸的混合酸是理想的。但在使用铝作为栅电极时，栅电极也被刻蚀剂刻蚀。根据本发明，如图IC所示，在栅电极和阳极氧化物106之间设置势垒型阳极氧化膜107，这个问题就可以解决。
在含有3-10％酒石酸、硼酸或硝酸的乙二醇中形成阳极氧化物106后，将电流加到栅电极可形成阳极氧化膜107。阳极氧化物107的厚度可由栅电极和反电极之间的电压大小决定。应注意，这种阳极氧化中所用的电解液是比较中性的，以致和使用酸性溶液相反，也可增加阳极氧化物的密度。这样，就可以形成势垒型阳极氧化物。多孔型阳极氧化物的刻蚀率比势垒型阳极氧化物的高10倍。
于是，可由含刻蚀剂的磷酸将多孔型阳极氧化物106除去而不会损伤栅电极。
由于栅绝缘膜104′以自对准方式相对于多孔性阳极氧化物106形成，栅绝缘膜104′的外边缘离开势垒型阳极氧化物107的外边缘“y”，如图1D所示。使用阳极氧化物的一个好处在于，距离“y”可以以自对准方式由阳极氧化物的厚度决定。
参看图1E,N型或P型的杂质离子被加速注入有源层103以在栅绝缘膜104′已除去(或减薄)的部分形成高杂质浓度区108和111，并在栅绝缘膜留下来的地方形成低杂质浓度区109和110。由于杂质离子通过栅绝缘膜104′进入区109和110，故这些区的杂质离子浓度较区108和111的低。因为加有较高的杂质浓度，杂质区108和111的电阻较杂质区109和110的电阻低。杂质离子浓度的差别依赖于栅绝缘膜104′的厚度。正常情况下，区109和110的浓度小于区108和111的0.5至3位数。
在栅电极下的有源层部分不掺以杂质，且可保留为本征的或基本上是本征的。因而限定出沟道区。杂质引进后，用激光或强度等效于该激光的光照射杂质区，将杂质激活。这步骤一步就可完成。结果如图1E和1F所示，栅绝缘膜104′的边缘112大致与高阻区(HRD)的边缘113相对准。
如以上解释，通过阳极氧化物106的厚度“y”以自对准方式可确定高电阻率区109和119，而厚度“y”反过来是由阳极氧化步骤期间施加到栅电极的电流量决定的。这样做较图6A-6F所示的使用与栅电极毗连的绝缘材料要优越得多。
此外，由于低电阻率区和高电阻率区可用单一的杂质掺杂步骤形成，上述方法是有优点的。在先有技术中尽管HRD有一好处，即它可以避免出现热载流子并增加器件的可靠性。但存在一个问题，即因HRD的阻率高，它难以和电极成欧姆接触，又因此电阻率使漏电压不合要求地降低。本发明解决了这些理解不深的问题，同时可以自对准方式形成具有0.1至1μm宽度的HRD，并能使电极和源和漏区间呈欧姆接触。
再者，相对于栅电极的沟道区和HRD(109和110)之间的边界位置关系，参看图4A-4D和下列解释，可通过改变势垒型阳极氧化物107的厚度加以控制。例如，使用离子掺杂法(亦称为等离子体掺杂)时，离子被引进时没有按质量分开，以致离子的注入角度不是均匀的。因而引入到有源层的离子容易在横方向上分开。
图4A说明图1E所示的部分放大视图。编号401指栅电极。402指势垒型阳极氧化物，它与图1E的势垒型阳极氧化物107相对应。404指有源层，其厚度例如约800。当阳极氧化物402的厚度大约和有源层404的厚度相等时，栅电极的边缘405基本上和HRD407的边缘406相对准。
当阳极氧化层402厚于有源层，例如，3000时，栅电极的边缘405，如图4B所示，偏离HRD的边缘406。另一方面，与有源层比较起来阳极氧化物402为比较薄时，栅电极叠置HRD，如图4C所示。当没有阳极氧化物围绕在栅电极401，如图4D所示，这种叠置变得最大。
一般情况下，偏离结构可降低反向漏电流(截止电流)并增加ON/OFF(导通/截止)比。偏离结构适用于TFT，以在驱动漏电流要尽可能避免的液晶器件中驱动象素。然而，由于在HRD的边缘处出现并会被氧化物俘获的热电子，阳极氧化物容易变质。
在栅电极叠置HRD时，可以减轻变质的缺点，并使ON电流增加。但有漏电流增加的缺点。为此，叠置结构适用于单片有源阵列器件的周围电路中的TFT。于是，根据应用情况，可选用图4A至4E的适用结构。
例1
再参看图1A-1F，将更详细地讨论制造TFT的方法。将一块尺寸为300mm×400mm或100mm×100mm的Corning玻璃衬底用作衬底101。通过例如在氧气中的溅射，在衬底上形成厚度为100-300nm的氧化硅作为基底膜102。但为改进生产率可以使用TEOS作为起始材料的等离子体CVD。
通过等离子体CVD或LPCVD将非晶硅沉积至厚度为300-5000最好为500-1000，然后在一减压气氛中将其在550-600℃下加热24小时，并将其构图，可形成岛状的结晶硅膜103。可以采用激光退火以代替加热退火。此外，用溅射法形成厚度为70-150nm的氧化硅膜104。
然后用电子束蒸发或溅射法形成含1％重量Si或0.1-0.3％重量Sc(钪)厚为1000至3μm的铝膜。如图1A所示，将铝膜构图，形成栅电极105。
再参看图1B，通过将电流施加到一电极上使栅电极105阳极氧化，以形成厚度为3000-6000，例如为5000的阳极氧化膜106。使用3-20％的柠檬酸、草酸、磷酸、铬酸或硫酸的酸性水溶液。所加电压为10-30V，而所加电流保持恒定。此例用的是草酸。电解液的温度为30℃。施加10V电压20-40分钟。阳极氧化膜的厚度由阳极氧化时间控制。
随后，在另一含3-10％草酸、硼酸或硝酸的乙二醇溶液的电解液中再对栅电极阳极氧化，以形成围绕栅电极的势垒型阳极氧化膜107。电解液的温度最好保持在较室温低，例如10℃，以便改进氧化膜的质量。阳极氧化膜107的厚度与所加电压的大小成比例。所加电压选自80-150V的范围。当所加电压为150V时，厚度为2000。阳极氧化膜107的厚度是根据TFT所需结构(参见图4A-4D的讨论)决定的，但需将电压提高到250V或更高，以获得厚度为3000或更厚的阳极氧化膜。
由于这样大的电压对TFT存在危险，最好选择阳极氧化物107的厚度为3000或更小。
参看图1D，用干式刻蚀法部分除去氧化硅膜104。这种刻蚀可以呈各向同性刻蚀的等离子体模式或是各向异性刻蚀的反应离子刻蚀模式。但硅和氧化硅的选择比应足够大。使得不应太多刻蚀有源硅层。还有，阳极氧化物106和107不被CF4刻蚀，而氧化硅膜则被选择性地刻蚀。由于多孔型阳极氧化物106下面的氧化硅膜104不被刻蚀，栅绝缘膜104′不被刻蚀地保留下来。
然后参看图1E，采用磷酸、醋酸或硝酸的混合酸，以例如6000/分的刻蚀率，只将多孔型阳极氧化膜106刻蚀。栅绝缘膜104′保留下来。
除去多孔型阳极氧化膜106后，以栅电极、势垒型阳极氧化膜107和栅绝缘膜104′为掩模，用离子掺杂法以自对准方式加入杂质元素，使半导体层形成一种导电类型。结果形成高电阻率杂质区109和110，低电阻率区(源和漏区)108和111。形成P型区时，使用乙硼烷(B2H6)作为掺杂气体。剂量为5×1014至5×1015原子/cm2。加速能量为10-30KV。在该引进后，用KrF激发物激光(波长248nm，脉冲宽度20ns)激活所加杂质。
用SIMS(二次电子质普仪)测量有源层中的杂质浓度，源和漏区108和111的杂质浓度为1×1020至2×1021原子/cm3，而高电阻率区109和110中的杂质浓度为1017至2×1018原子/cm3。这对应于前一种情况的剂量5×1014-5×1015原子/cm2和后一种情况的剂量2×1013-5×1014原子/cm2。这种差别是由于有栅绝缘膜104′引起的。一般而言，低电阻率杂质区的浓度比高电阻率区的浓度高0.5-3倍。
然后在整个结构上用CVD形成厚度为3000A的氧化硅的层间绝缘膜114，随后，通过绝缘膜和在其中形成的铝电极形成接触孔，以接触图1F所示的源和漏区。最后，进行氢气退火，以完成TFT的制造。
参看图5A，以下将解释本发明的TFT应用于有源阵列器件，例如液晶器件的电路衬底。图5A中，衬底上形成了三个TFT。TFT1和TFT2在周围电路中用作驱动器TFT。TFT1和TFT2中的势垒型阳极氧化物501和502厚200-1000，例如500。因此，栅电极叠置高电阻率区。TFT1的漏极和TFT2的源极彼此连接，TFT1的源板接地，TFT2的漏板连接到电源。这样就形成CMOS倒相器。这自然不局限于本结构，因而可以形成任一种其他电路。
另一方面，TFT3用作象素TFT，用以驱动象素。阳极氧化物503厚2000，以便形成偏离区。本结构对应于图4B所示结构。于是，可以降低漏电流。TFT3源和漏中的一个连接到由氧化铟锡(ITO)制成的象素电极504。同时，TFT1和3为N沟道TFT，而TFT2为P沟道TFT。
例2
本例是例1的改进，其中的源和漏区设有硅化物层。参看图2A，201为Corning7059玻璃衬底，202为基底膜，203为硅岛，204为绝缘膜，205为A1栅电极(厚200nm-1μm)，以及206为多孔型阳极氧化膜(厚3000-1μm例如5000)。这些是使用例1所解释的相同方法来形成的，这里不赘述。
参看图2B，在形成多孔型阳极氧化物206后，以和例1相同的方式形成厚1000-2500的势垒型阳极氧化膜207。然后，用多孔型阳极氧化物206为掩模，以自对准方式通过刻蚀绝缘膜204形成栅绝缘膜204′。
然后，用势垒型阳极氧化物207作为掩模，通过刻蚀将多孔型阳极氧化物206除去。此外，用栅电极205和阳极氧化物207作为掩模，以自对准方式进行杂质元素(磷)的离子掺杂，以便形成如图2C所示的低电阻率杂质区208和211以及高电阻率杂质区209和210。所用剂量为1×1014-5×1014原子/cm2，加速电压为30-90KV。
参看图2D，用溅射法在整个表面上形成金属膜212，例如钛膜，其厚度为50-5000。低电阻率区208和211直接和金属膜接触。除了钛外，也可用其他金属，例如镍、钼、钨、铂或钯。
之后，将KrF激发物激光(波长248nm，脉冲宽度20)照射到表面上，以激活所加杂质，并通过和有源层中的金属膜和硅起反应，形成金属硅化物区213和214。激光束的能量密度为200-400MJ/cm2，最好为250-300MJ/cm2。而且，在激光照射期间，要求衬底维持在200-500℃，以避免剥落钛层。
当然，使用其他不是激发物激光的光源也是可以的。但因CW激光的照射时间较长，被照射膜有热膨胀和剥落的危险，故最好使用脉冲激光束。
至于脉冲激光的例子，有IR(红外)光激光，例如Na:YAG激光(最好用Q开关脉冲振荡)、Na:YAG的二次谐波(可见光)以及UV(紫外)光(例如KrF、Xe Cl和ArF的激发物激光)。激光束由金属膜上侧发射时，需要选择激光的波长，以便不在金属上反射。再者，也可从衬底侧发射激光。此时，需选择了可透射硅的激光。
用激光退火之外，也可用可见光或近红外光的灯光退火。此时，进行退火，将衬底加热至600-1000℃，例如在600℃下数分钟，或在1000℃下数十秒。用近红外线退火时，不要过甚加热玻璃衬底。因近红外线被硅半导体有选择地吸收。此外，缩短照射时间，可以防止加热玻璃。
此后，参看图2E，在例如栅电极或栅绝缘膜上只有保持不变而不转变为硅化物的钛膜，才被含5:2:2的过氧化氢、氨和水的刻蚀剂刻蚀掉。结果硅化钛213和214保持不变。
参看图2F，在整个表面上用CVD沉积2000-1μm例如3000的氧化硅而形成层绝缘膜217。通过绝缘膜217，在源和漏区213和214上形成接触孔，继之在其中形成厚度为2000-1μm例如为5000的铝电极或引线218和219。和使用硅半导体相比，使用金属硅化物可提供与铝的稳定界面，并提供与铝电极的良好接触。通过在铝电极218和219及金属硅化物区213和214之间形成势垒金属，可以进一步改进接触。硅化物区的薄层电阻可做成10-50Ω/□，而HRD209和210的为10-100KΩ/□。
借助上述工序，可以改进TFT的频率特性，而且在较高的漏电压下也可以抑制热载流子的损伤。
在本例中，低电阻率杂质区和金属硅化物区大约彼此重合。特别是栅绝缘膜204′的边缘215大致与高电阻率杂质区210和低电阻率杂质区211之间的边界216共同延伸，也与金属硅化物区214的内边缘共同延伸。显然，以金属硅化物区代替低电阻率区，参考图4A-4D的解释可应用到本例中。
图5B示出本例在有源阵列器件中的应用。在图5B中，衬底上形成了三个TFT。TFT1和TFT2在周围电路中用作驱动器TFT。TFT1和TFT2中的势垒型阳极氧化物505和506厚200-1000，例如厚500。因此，栅电极叠置高电阻率区。TFT1的漏极和TFT2的源极彼此互连，TFT1的源极接地，TFT2的漏极则连接到电源。因而，形成了CMOS倒相器。因为还可以形成任一种其他电路，因而不应只局限于本结构。
另一方面，TFT3用作象素TFT驱动象素。阳极氧化物507厚为2000，以便可以形成偏离区。这种结构相应于图4B所示的结构。因此，可降低漏电流。TFT3的源和漏极中的一个极连接到由铟锡氧化物(ITO)制成的象素电极508。
为了独立地控制各个TFT的阳极氧化物的厚度，各IFT的栅电极最好彼此独立制成。同时，TFT1和3是N沟道型TFT，而TFT2为P沟道型TFT。
此外，可在杂质的离子掺杂前形成钛膜。在这情况下，其好处是钛膜可在离子掺杂期间防止表面充电。再者，在钛形成步骤前、离子掺杂步骤后，可用激光进行退火。在钛形成后，硅化钛可用光照射或热退火形成。
例3
本例是例2的进一步变化结果，其中改变了金属硅化物的形成步骤和离子掺杂的秩序。参看图3A，在Corning7059衬底301上形成了基底氧化膜302、岛状结晶半导体(例如硅)区303、氧化硅膜304、2000至1μm的铝栅电极以及在栅电极侧上的6000的多孔型阳极氧化膜306。这些都和参看图1A和1B讨论的例1一样的方式形成的。
此外，以和例1一样的方式形成1000-2500的势垒型阳极氧化膜307。接着，以图3B所示的自对准方式将氧化硅膜304构图成栅绝缘膜304′。
参看图3C，将多孔型阳极氧化物306除去，以便露出一部分的栅绝缘膜304′。接着，用溅射法在整个表面上形成厚50-500的例如为钛膜308的金属层。
然后用KrF激发物激光照射以便形成硅化物区309和310。激光的能量密度为200-400mJ/cm2，最好为250-300mJ/cm2。此外，也希望保持衬底在200-500℃，以在激光照射期间防止钛膜剥落。这一步骤可用可见光或远红外光的灯光退火进行。
参看图3D，采用含5:2:2的过氧化氢、氨和水的刻蚀剂，将例如在栅电极或栅绝缘膜上只留下的钛膜剥去。结果将硅化钛309和310保留下来。
参看图3E，使用栅电极305、阳极氧化物307和栅绝缘膜304′作为掩模，剂量为1-5×1014原子/cm2，加速电压为30-90KV，完成磷的离子掺杂，以使形成低电阻率区311和314以及高电阻率区312和313。硅化钛区309和310大致和低电阻率区311和314重合，它同样也和源和漏区重合。
然后再用KrF激发物激光(波长248nm，脉中宽度20ns)激活所加磷。这可如上述使用可见光或远红外线的灯光退火来进行。之后，如图3F所示，以栅电极和阳极氧化物307为掩模刻蚀栅绝缘膜304′，形成栅绝缘膜304′。这是因为加入到栅绝缘膜304′的杂质使器件性质不稳定。
图3F中，通过CVD在整个表面上沉积6000厚的氧化硅以形成层间绝缘体315。接触孔通过绝缘体开出，以在源和漏区上形成铝电极316和317。这样就完成了TFT。
根据本发明，掺杂或退火步骤的次数可以减少。再者，除了P型或n型杂质离子外，还可加入如碳、氧或氮的杂质，以便进一步降低反向漏电流，并提高介质强度。这一点在有源阵列电路中的象素TFT是特别有用的。在这情况下，图5A和5B是TFT3具有的阳极氧化膜做得与TFT1和TFT2的一样厚。
例4
现参看图7A-7F来解释本发明的第四个例子。本例与例1比较，相同标号表示相同的元件。本质上本例中的各步骤几乎和前例相同，因此这里不再赘述。
在栅绝缘膜104上形成导电膜后，就在导电膜的整个表面上形成例如为光刻胶、光敏的聚酰亚胺掩模材料或聚酰亚胺。例如，旋涂光刻胶(由东京Oka公司制造的OFPR800/30cp)。最好是在导电膜和光刻胶之间形成阳极氧化膜(图中未示出)，然后将这些膜构图成图7A所示的栅电极105和掩模117。然后，以和例1相同的方式，在栅电极105的表面上(除了图7B所示的形成掩模117的部分外)形成多孔型阳极氧化膜106。
然后参看图7C，通过干式刻蚀将氧化硅膜104构图，以便露出部分硅膜103，从而形成栅绝缘膜104′。这里也采用了与例1中所做的相同的刻蚀方法。此外，在这个刻蚀步骤之前和之后，都通过常规的光刻技术除去光刻胶掩模。
参看图7D，以和例1相同的方式形成厚度为2000的势垒型阳极氧化膜107。使用这种势垒型阳极氧化膜作为掩模，通过用以前解释过的磷酸刻蚀剂除去多孔型阳极氧化物。于是获得图7E所示的结构。接下去的步骤和参考图1E和1F的解释的步骤相同。
由于在第一次阳极氧化中栅电极的上表面不被氧化，因而可在第一次阳极氧化期间防止栅电极厚度减薄太多。即在例1中，因为栅电极的整个表面受到阳极氧化，栅电极厚度被减薄，引起布线电阻不希望有的增加。本例可避免这样的问题。
例5
本例是例2和例4的组合，并示于图8A-8F。图8A-8B所示的步骤和例4的图7A-7C所叙述的完全一样。亦即，仅在栅电极的侧表面上形成多孔型阳极氧化物，而栅电极的上部则覆以掩模。此外，出现在图8B所示的暴露硅层部分的步骤后，即图8C-8C所示的步骤，是和参考图2C-2F的例2中解释的那些步骤完全相同。
例6
本例也是关注例3和例5的组合，并示于图9A-9F。亦即本例和例5不同之处，仅在于金属硅化物区的形成和离子注入步骤的秩序。因此，图9A-9B所示的步骤和例4参考图7A-7C所述的步骤完全相同，而且也对应于例5的图8A和8B所示的步骤。图9C-9F所示的随后步骤完全对应于例3的图3C-3F所示的步骤。
例7
参看图10A-10F，本例可和示于图7A-7F的例4相比较。唯一不同处是图10C和10D所示的步骤秩序。亦即，在图10C中，势垒型阳极氧化膜107是在刻蚀绝缘膜104之前形成的。在势垒型阳极氧化物107形成后，将绝缘膜104构图成栅绝缘膜104′。另一方面，在例4中，绝缘膜104的构图是在如图7C所示的势垒型阳极氧化物形成前进行的。因此，在例7中，势垒型阳极氧化物在刻蚀绝缘膜104期间保护铝栅电极105。
例8
本例除了栅绝缘膜的构图步骤和势垒型阳极氧化膜207的形成步骤之间的秩序外，完全和图8A-8F的例5相同。亦即，参看图11A-11B，和例5相反，势垒型阳极氧化膜207是在刻蚀绝缘膜204之前形成的。之后，将绝缘膜构图成栅绝缘膜204′。图11C-11F中所示的随后步骤完全和例5中的相同。
例9
本例除在栅绝缘膜304的构图步骤和势垒型阳极氧化膜307的形成步骤之间的秩序外，也和图9A-9F的例6完全相同。亦即，参看图12A-12B，势垒型阳极氧化膜307是在刻蚀绝缘膜304部分之前形成的。此后，将绝缘膜构图成栅绝缘膜304′。图12C-12F中所示的随后步骤完全和例6中的相同。
参考例6-9，虽则没有在示图中显示出来，仅在栅电极的侧表面上形成阳极氧化膜时，最好在栅电极和掩模之间设置阳极氧化膜。下面将参看图13A-13D更详细地叙述这个特点。
图13A-13D是使用可阳极化的材料的布线细致过程。在例如形成在半导体上的氧化膜衬底701上，形成例如厚2μm的铝膜702。为避免在顺序阳极氧化步骤期间产生铝的异常生长(小丘)，铝可含0.2％重量的Sc(钪)，或为避免在高温生产过程产生铝的异常生长，铝可含其他添加剂，例如钇(Y)。
然后在含3％酒石酸的乙二醇溶液中，对铝膜施加10-30V的电压将其阳极氧化。从而在铝膜上形成厚200的致密阳极氧化膜703。然后用光刻胶掩模704，根据预定的图形将铝膜702和氧化膜703构图。由于氧化膜很薄，故易以在同时将其刻蚀。
上述情况下的构图是通过各向同性刻蚀进行的。经构图的铝膜边缘具有如图13B标号707所示的形状。此外，氧化物703和铝702之间的不同刻蚀率也进一步增强了结构707。
然后在含10％草酸的水溶液中，通过施加10-30V的电压，形成多孔型阳极氧化膜705。氧化过程主要是在铝膜内侧进行的。
已证实氧化生长的顶端，即在阳极氧化物和铝之间的边界，大致垂直于衬底表面。另一方面，在势垒型阳极氧化的情况下，势垒型阳极氧化物的形状几乎保持了起始金属的形状。
本例中铝膜厚度为2μm，而多孔型阳极氧化膜705生长到5000。透过电子显微照片观察到生长的顶端大致是垂直的。
形成多孔型阳极氧化膜后，用常规的脱模剂除去光刻胶掩模704。因掩模阳极氧化物703很落，可与光刻胶掩模704同时剥除，或者使用加有缓冲剂的氟化氢酸在较后的步骤中除去。
此外，如图13D所示，通过在不同条件下进行另一阳极氧化，进一步形成2000厚的势垒型阳极氧化膜706。就是说，电解液是含3％酒石酸的乙二醇溶液，所加电压约150V。该氧化膜从多孔型阳极氧化物705和铝702之间的边界开始在内侧方向围绕铝膜均匀地生长。
因此，形成一种结构，其中势垒型阳极氧化膜围绕铝膜形成，还有的多孔型阳极氧化膜则在铝膜侧边上形成。
用磷酸H3PO4可容易地和选性性地将多孔型阳极氧化物705除去，而不会损伤铝膜。
不用说，上述工序可用在前述例4-9的阳极氧化工序中。
尽管在前述例子中使用了玻璃衬底，本发明的TFT也可形成在任何绝缘表面上，例如有机树脂或形成在单晶硅的绝缘表面上。还有，它也可形成在三维集成电路的器件中。特别是本发明用在电光器件，例如在同一衬底上形成有周围电路的单片型有源阵列电路时，是特别有利的。
此外，例子中虽然使用结晶硅，本发明也可用于非晶硅或其他类型的半导体。
尽管本发明是参考最佳实施例加以叙述的，但精通本邻域的人士显然可以理解实施例的各种变型。本发明要包括所有在所附权利要求书范围内的变型。

Claims (12)

1．一种制造半导体器件的方法，其特征在于，包括下列步骤：
在绝缘表面上形成半导体膜；
在所说半导体膜上形成绝缘膜；
在所说绝缘膜上形成栅电极；
首先阳极氧化所说栅电极，以便在所说栅电极的至少一侧面上形成第一阳极氧化膜；
用所说第一阳极氧化膜作为掩模，通过刻蚀将一部分的所说绝缘膜除去或减薄，以便形成栅绝缘膜；
除去所说第一阳极氧化膜；以及
用至少所说栅电极作为掩模并通过一部分所说栅绝缘膜将其中一种导电型杂质引进所说半导体膜。
2．权利要求1的方法，其特征在于，它还包括将所说半导体膜的部分转变为金属和所说半导体的化合物，所说部分伸出所说栅绝缘膜的侧边。
3．根据权利要求1的方法，其特征在于，它还包括在所说第一阳极氧化步骤后第二阳极氧化所说栅电极的步骤，以便形成第二阳极氧化膜。
4．权利要求3的方法，其特征在于，其中所说第一阳极氧化膜与所说第二阳极氧化膜相比是较多孔性的。
5．根据权利要求1的方法，其特征在于，它还包括在所说引进步骤后通过在其上照射光激活所说杂质。
6．权利要求1的方法，其特征在于，所说半导体膜包括结晶硅。
7．权利要求1的方法，其特征在于，所说栅电极含有选自铝、钽、钛和硅的元素。
8．权利要求1的方法，其特征在于，它还包括下列步骤：
在所说绝缘膜上形成导电材料以形成栅电极；
在所说导电材料的所选部分上形成掩模；以及
根据所说掩模将所说导电材料刻图以成栅电极；
其中所说掩模覆盖所说栅电极的上部，且在形成所说第一阳极氧化膜期间所说掩模留下来保持不变。
9．权利要求8的方法，其特征在于，它还包括：在所说第一阳极氧化膜形成后形成第二阳极氧化模。
10．权利要求8的方法，其特征在于，所说导电材料包括选自铝、钽、钛和硅的元素。
11．权利要求9的方法，其特征在于，所说第二阳极氧化膜是在所说除去或减薄步骤前形成的。
12．权利要求9的方法，其特征在于，该第一阳极氧化膜与所说第二阳极氧化膜相比是较多孔性的。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100523966C (zh) * 2001-02-06 2009-08-05 株式会社日立制作所 显示装置及其制造方法
CN113430615A (zh) * 2021-06-09 2021-09-24 华南理工大学 一种阳极氧化铝膜及其制备方法和应用
CN113529150A (zh) * 2021-06-23 2021-10-22 华南理工大学 一种亚微米氧化铝管及其制备方法和应用

Families Citing this family (81)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3437863B2 (ja) 1993-01-18 2003-08-18 株式会社半導体エネルギー研究所 Ｍｉｓ型半導体装置の作製方法
TW297142B (zh) 1993-09-20 1997-02-01 Handotai Energy Kenkyusho Kk
US5719065A (en) 1993-10-01 1998-02-17 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device with removable spacers
US6777763B1 (en) 1993-10-01 2004-08-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for fabricating the same
TW299897U (en) 1993-11-05 1997-03-01 Semiconductor Energy Lab A semiconductor integrated circuit
JPH09146108A (ja) 1995-11-17 1997-06-06 Semiconductor Energy Lab Co Ltd 液晶表示装置およびその駆動方法
JP3963974B2 (ja) 1995-12-20 2007-08-22 株式会社半導体エネルギー研究所 液晶電気光学装置
TW374196B (en) 1996-02-23 1999-11-11 Semiconductor Energy Lab Co Ltd Semiconductor thin film and method for manufacturing the same and semiconductor device and method for manufacturing the same
JPH10135475A (ja) * 1996-10-31 1998-05-22 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP3788649B2 (ja) * 1996-11-22 2006-06-21 株式会社半導体エネルギー研究所 液晶表示装置
JPH10228248A (ja) * 1996-12-09 1998-08-25 Semiconductor Energy Lab Co Ltd アクティブマトリクス表示装置およびその作製方法
JP4318768B2 (ja) 1997-07-23 2009-08-26 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6686623B2 (en) 1997-11-18 2004-02-03 Semiconductor Energy Laboratory Co., Ltd. Nonvolatile memory and electronic apparatus
US20080042554A1 (en) * 1998-05-18 2008-02-21 Kabushiki Kaisha Toshiba Image display device and light emission device
JP2000012864A (ja) 1998-06-22 2000-01-14 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP4324259B2 (ja) * 1998-07-07 2009-09-02 シャープ株式会社 液晶表示装置の製造方法
JP3592535B2 (ja) * 1998-07-16 2004-11-24 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6271101B1 (en) * 1998-07-29 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Process for production of SOI substrate and process for production of semiconductor device
US6559036B1 (en) * 1998-08-07 2003-05-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
JP4476390B2 (ja) 1998-09-04 2010-06-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6617644B1 (en) 1998-11-09 2003-09-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
US6909114B1 (en) 1998-11-17 2005-06-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having LDD regions
US6501098B2 (en) * 1998-11-25 2002-12-31 Semiconductor Energy Laboratory Co, Ltd. Semiconductor device
US6365917B1 (en) * 1998-11-25 2002-04-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US6777716B1 (en) 1999-02-12 2004-08-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor display device and method of manufacturing therefor
US6576924B1 (en) * 1999-02-12 2003-06-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having at least a pixel unit and a driver circuit unit over a same substrate
EP1031873A3 (en) * 1999-02-23 2005-02-23 Sel Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and fabrication method thereof
US7821065B2 (en) 1999-03-02 2010-10-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising a thin film transistor comprising a semiconductor thin film and method of manufacturing the same
US6674136B1 (en) * 1999-03-04 2004-01-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having driver circuit and pixel section provided over same substrate
US6531713B1 (en) 1999-03-19 2003-03-11 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and manufacturing method thereof
TW469484B (en) 1999-03-26 2001-12-21 Semiconductor Energy Lab A method for manufacturing an electrooptical device
US7145536B1 (en) * 1999-03-26 2006-12-05 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device
TW444257B (en) 1999-04-12 2001-07-01 Semiconductor Energy Lab Semiconductor device and method for fabricating the same
TW518637B (en) * 1999-04-15 2003-01-21 Semiconductor Energy Lab Electro-optical device and electronic equipment
US6512504B1 (en) * 1999-04-27 2003-01-28 Semiconductor Energy Laborayory Co., Ltd. Electronic device and electronic apparatus
EP2256808A2 (en) 1999-04-30 2010-12-01 Semiconductor Energy Laboratory Co, Ltd. Semiconductor device and manufacturing method therof
US6370502B1 (en) * 1999-05-27 2002-04-09 America Online, Inc. Method and system for reduction of quantization-induced block-discontinuities and general purpose audio codec
JP2000340794A (ja) * 1999-06-01 2000-12-08 Mitsubishi Electric Corp 半導体装置およびその製造方法
US7245018B1 (en) * 1999-06-22 2007-07-17 Semiconductor Energy Laboratory Co., Ltd. Wiring material, semiconductor device provided with a wiring using the wiring material and method of manufacturing thereof
US6952020B1 (en) 1999-07-06 2005-10-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US6515648B1 (en) * 1999-08-31 2003-02-04 Semiconductor Energy Laboratory Co., Ltd. Shift register circuit, driving circuit of display device, and display device using the driving circuit
US6645837B2 (en) * 2000-05-31 2003-11-11 Sony Corporation Method of manufacturing semiconductor device
JP5038560B2 (ja) 2001-08-01 2012-10-03 ゲットナー・ファンデーション・エルエルシー 電界効果型トランジスタ及びその製造方法並びに該トランジスタを使った液晶表示装置及びその製造方法
JP4308496B2 (ja) * 2002-03-01 2009-08-05 株式会社ルネサステクノロジ 半導体装置およびその製造方法
JP2004134687A (ja) * 2002-10-15 2004-04-30 Toshiba Corp 半導体装置及びその製造方法
TW582099B (en) * 2003-03-13 2004-04-01 Ind Tech Res Inst Method of adhering material layer on transparent substrate and method of forming single crystal silicon on transparent substrate
JP4537029B2 (ja) * 2003-09-30 2010-09-01 シャープ株式会社 薄膜トランジスタ装置及びその製造方法、並びにそれを備えた薄膜トランジスタ基板及び表示装置
US6852584B1 (en) * 2004-01-14 2005-02-08 Tokyo Electron Limited Method of trimming a gate electrode structure
KR101155943B1 (ko) * 2004-04-28 2012-06-18 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Ｍｏｓ 캐패시터 및 반도체 장치
JP4321486B2 (ja) * 2004-07-12 2009-08-26 セイコーエプソン株式会社 半導体装置及び半導体装置の製造方法
US7939873B2 (en) * 2004-07-30 2011-05-10 Semiconductor Energy Laboratory Co., Ltd. Capacitor element and semiconductor device
US7575959B2 (en) * 2004-11-26 2009-08-18 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
US20060197088A1 (en) * 2005-03-07 2006-09-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method of the same
CN100362355C (zh) * 2005-05-27 2008-01-16 东南大学 微型抗辐射电场传感器
US20070054442A1 (en) * 2005-09-08 2007-03-08 Po-Chih Liu Method for manufacturing thin film transistor, thin film transistor and pixel structure
US7659580B2 (en) * 2005-12-02 2010-02-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US7790527B2 (en) * 2006-02-03 2010-09-07 International Business Machines Corporation High-voltage silicon-on-insulator transistors and methods of manufacturing the same
ES2535232T3 (es) * 2006-03-27 2015-05-06 The Lubrizol Corporation Polímeros y composiciones lubricantes de los mismos
US7696024B2 (en) * 2006-03-31 2010-04-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
EP1863090A1 (en) * 2006-06-01 2007-12-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
JP5352081B2 (ja) * 2006-12-20 2013-11-27 株式会社半導体エネルギー研究所 半導体装置の作製方法
TWI345318B (en) * 2007-07-20 2011-07-11 Chimei Innolux Corp Light emitting diode
JP5393058B2 (ja) * 2007-09-05 2014-01-22 キヤノン株式会社 電界効果型トランジスタ
JP5219529B2 (ja) * 2008-01-23 2013-06-26 キヤノン株式会社 電界効果型トランジスタ及び、該電界効果型トランジスタを備えた表示装置
JP5234333B2 (ja) * 2008-05-28 2013-07-10 Ｎｌｔテクノロジー株式会社 ゲート線駆動回路、アクティブマトリクス基板及び液晶表示装置
US8314765B2 (en) 2008-06-17 2012-11-20 Semiconductor Energy Laboratory Co., Ltd. Driver circuit, display device, and electronic device
WO2011074407A1 (en) 2009-12-18 2011-06-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US8791546B2 (en) * 2010-10-21 2014-07-29 Freescale Semiconductor, Inc. Bipolar transistors having emitter-base junctions of varying depths and/or doping concentrations
US20120319113A1 (en) * 2011-06-17 2012-12-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
TWI556319B (zh) 2011-11-30 2016-11-01 半導體能源研究所股份有限公司 半導體裝置的製造方法
US9099489B2 (en) 2012-07-10 2015-08-04 Freescale Semiconductor Inc. Bipolar transistor with high breakdown voltage
US9368360B2 (en) 2013-04-28 2016-06-14 Boe Technology Group Co., Ltd Anti-diffusion layer, preparation method thereof, thin-film transistor (TFT), array substrate, display device
US9449827B2 (en) 2014-02-04 2016-09-20 International Business Machines Corporation Metal semiconductor alloy contact resistance improvement
US9087689B1 (en) * 2014-07-11 2015-07-21 Inoso, Llc Method of forming a stacked low temperature transistor and related devices
US10580708B2 (en) * 2017-02-17 2020-03-03 Ablic Inc. Method of manufacturing a semiconductor device and semiconductor device
CN109637932B (zh) * 2018-11-30 2020-11-10 武汉华星光电技术有限公司 薄膜晶体管及其制备方法
CN110223990B (zh) * 2019-06-18 2022-03-08 京东方科技集团股份有限公司 顶栅结构及其制备方法、阵列基板、显示设备
CN112928153B (zh) * 2019-12-05 2023-07-04 中芯国际集成电路制造（天津）有限公司 半导体结构及其形成方法
CN113140637A (zh) * 2020-01-20 2021-07-20 京东方科技集团股份有限公司 显示装置、阵列基板、薄膜晶体管及其制造方法
CN112103245B (zh) * 2020-09-22 2023-08-11 成都京东方显示科技有限公司 阵列基板的制造方法、阵列基板及显示面板
CN112114460B (zh) * 2020-09-23 2022-12-23 北海惠科光电技术有限公司 基于阵列基板的绝缘单元及其制备方法、阵列基板及其制备方法、显示机构

Family Cites Families (172)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL161617C (nl) 1968-06-17 1980-02-15 Nippon Electric Co Halfgeleiderinrichting met vlak oppervlak en werkwijze voor het vervaardigen daarvan.
JPS5124341B2 (zh) 1971-12-24 1976-07-23
US3775262A (en) 1972-02-09 1973-11-27 Ncr Method of making insulated gate field effect transistor
JPS4995591A (zh) 1973-01-12 1974-09-10
JPS5423345B2 (zh) 1974-02-02 1979-08-13
US4065781A (en) 1974-06-21 1977-12-27 Westinghouse Electric Corporation Insulated-gate thin film transistor with low leakage current
US4040073A (en) 1975-08-29 1977-08-02 Westinghouse Electric Corporation Thin film transistor and display panel using the transistor
US3997367A (en) 1975-11-20 1976-12-14 Bell Telephone Laboratories, Incorporated Method for making transistors
JPS5470762A (en) * 1977-11-16 1979-06-06 Seiko Instr & Electronics Ltd Semiconductor device
US4236167A (en) 1978-02-06 1980-11-25 Rca Corporation Stepped oxide, high voltage MOS transistor with near intrinsic channel regions of different doping levels
JPS54161282A (en) * 1978-06-12 1979-12-20 Toshiba Corp Manufacture of mos semiconductor device
US4232327A (en) * 1978-11-13 1980-11-04 Rca Corporation Extended drain self-aligned silicon gate MOSFET
US4319395A (en) * 1979-06-28 1982-03-16 Motorola, Inc. Method of making self-aligned device
US4336550A (en) 1980-03-20 1982-06-22 Rca Corporation CMOS Device with silicided sources and drains and method
US4622735A (en) * 1980-12-12 1986-11-18 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing a semiconductor device utilizing self-aligned silicide regions
DE3272410D1 (en) 1981-02-16 1986-09-11 Fujitsu Ltd Method of producing mosfet type semiconductor device
JPS5823479A (ja) 1981-08-05 1983-02-12 Fujitsu Ltd 半導体装置の製造方法
JPS5837967A (ja) * 1981-08-31 1983-03-05 Toshiba Corp Ｍｉｓ型半導体装置の製造方法
JPS5895814A (ja) 1981-11-30 1983-06-07 Mitsubishi Electric Corp 半導体装置の製造方法
JPS58105574A (ja) * 1981-12-17 1983-06-23 Seiko Epson Corp 液晶表示装置
JPS58118154A (ja) 1982-01-07 1983-07-14 Seiko Epson Corp 半導体集積回路装置
JPS58142566A (ja) * 1982-02-19 1983-08-24 Seiko Epson Corp 薄膜半導体装置
US4557036A (en) 1982-03-31 1985-12-10 Nippon Telegraph & Telephone Public Corp. Semiconductor device and process for manufacturing the same
JPS59188974A (ja) 1983-04-11 1984-10-26 Nec Corp 半導体装置の製造方法
US4503601A (en) 1983-04-18 1985-03-12 Ncr Corporation Oxide trench structure for polysilicon gates and interconnects
JPS59220971A (ja) 1983-05-31 1984-12-12 Toshiba Corp 半導体装置の製造方法
JPH0693509B2 (ja) 1983-08-26 1994-11-16 シャープ株式会社 薄膜トランジスタ
JPS6055665A (ja) * 1983-09-06 1985-03-30 Toshiba Corp 半導体装置の製造方法
US4727044A (en) 1984-05-18 1988-02-23 Semiconductor Energy Laboratory Co., Ltd. Method of making a thin film transistor with laser recrystallized source and drain
US4727038A (en) 1984-08-22 1988-02-23 Mitsubishi Denki Kabushiki Kaisha Method of fabricating semiconductor device
JPS61224360A (ja) * 1985-03-28 1986-10-06 Sony Corp 電界効果トランジスタの製造方法
JPS61224459A (ja) 1985-03-29 1986-10-06 Toshiba Corp 半導体装置およびその製造方法
JPS6232653A (ja) 1985-08-05 1987-02-12 Nippon Telegr & Teleph Corp <Ntt> 薄膜トランジスタの製造方法
EP0222215B1 (en) * 1985-10-23 1991-10-16 Hitachi, Ltd. Polysilicon mos transistor and method of manufacturing the same
US4727004A (en) 1985-11-21 1988-02-23 Sharp Kabushiki Kaisha Thin film electroluminescent device
US4701423A (en) 1985-12-20 1987-10-20 Ncr Corporation Totally self-aligned CMOS process
US4755865A (en) 1986-01-21 1988-07-05 Motorola Inc. Means for stabilizing polycrystalline semiconductor layers
US4690730A (en) 1986-03-07 1987-09-01 Texas Instruments Incorporated Oxide-capped titanium silicide formation
JPS62229873A (ja) 1986-03-29 1987-10-08 Hitachi Ltd 薄膜半導体装置の製造方法
JPH0777264B2 (ja) 1986-04-02 1995-08-16 三菱電機株式会社 薄膜トランジスタの製造方法
JPS6366969A (ja) 1986-09-08 1988-03-25 Nippon Telegr & Teleph Corp <Ntt> 高耐圧多結晶シリコン薄膜トランジスタ
US4728617A (en) * 1986-11-04 1988-03-01 Intel Corporation Method of fabricating a MOSFET with graded source and drain regions
US4753896A (en) 1986-11-21 1988-06-28 Texas Instruments Incorporated Sidewall channel stop process
JPH0828510B2 (ja) 1987-01-20 1996-03-21 富士通株式会社 薄膜トランジスタの形成方法
JPH0687503B2 (ja) 1987-03-11 1994-11-02 株式会社日立製作所 薄膜半導体装置
US5024960A (en) 1987-06-16 1991-06-18 Texas Instruments Incorporated Dual LDD submicron CMOS process for making low and high voltage transistors with common gate
JPS647567A (en) 1987-06-29 1989-01-11 Ricoh Kk Mos transistor
US4818715A (en) * 1987-07-09 1989-04-04 Industrial Technology Research Institute Method of fabricating a LDDFET with self-aligned silicide
JPS6421919A (en) 1987-07-16 1989-01-25 Nec Corp Manufacture of semiconductor device
JPH01114070A (ja) 1987-10-28 1989-05-02 Hitachi Ltd 半導体装置の製造方法
US5075674A (en) 1987-11-19 1991-12-24 Sharp Kabushiki Kaisha Active matrix substrate for liquid crystal display
US4855247A (en) * 1988-01-19 1989-08-08 Standard Microsystems Corporation Process for fabricating self-aligned silicide lightly doped drain MOS devices
JPH01183853A (ja) 1988-01-19 1989-07-21 Toshiba Corp 薄膜電界効果トランジスタとその製造方法
US4908326A (en) * 1988-01-19 1990-03-13 Standard Microsystems Corporation Process for fabricating self-aligned silicide lightly doped drain MOS devices
NL8800222A (nl) 1988-01-29 1989-08-16 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij op zelfregistrerende wijze metaalsilicide wordt aangebracht.
US5258319A (en) * 1988-02-19 1993-11-02 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a MOS type field effect transistor using an oblique ion implantation step
US5238859A (en) 1988-04-26 1993-08-24 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
JP2653099B2 (ja) * 1988-05-17 1997-09-10 セイコーエプソン株式会社 アクティブマトリクスパネル，投写型表示装置及びビューファインダー
US5274279A (en) * 1988-05-17 1993-12-28 Seiko Epson Corporation Thin film CMOS inverter
JPH01291467A (ja) 1988-05-19 1989-11-24 Toshiba Corp 薄膜トランジスタ
JP2752991B2 (ja) 1988-07-14 1998-05-18 株式会社東芝 半導体装置
JPH0242419A (ja) 1988-08-02 1990-02-13 Hitachi Ltd 半導体装置およびその製造方法
US5146291A (en) 1988-08-31 1992-09-08 Mitsubishi Denki Kabushiki Kaisha MIS device having lightly doped drain structure
US4978626A (en) 1988-09-02 1990-12-18 Motorola, Inc. LDD transistor process having doping sensitive endpoint etching
JP2934445B2 (ja) * 1988-12-14 1999-08-16 ソニー株式会社 薄膜トランジスタの形成方法
JPH02162738A (ja) * 1988-12-15 1990-06-22 Nec Corp Ｍｏｓ　ｆｅｔ　の製造方法
JPH02246277A (ja) * 1989-03-20 1990-10-02 Matsushita Electron Corp Ｍｏｓトランジスタおよびその製造方法
US5231038A (en) * 1989-04-04 1993-07-27 Mitsubishi Denki Kabushiki Kaisha Method of producing field effect transistor
JPH0783127B2 (ja) * 1989-04-20 1995-09-06 三菱電機株式会社 半導体装置
JPH0338755A (ja) * 1989-07-05 1991-02-19 Nec Corp ファイル転送システム
JPH03142418A (ja) * 1989-10-30 1991-06-18 Matsushita Electron Corp 画像表示装置およびその製造方法
JP2921889B2 (ja) * 1989-11-27 1999-07-19 株式会社東芝 半導体装置の製造方法
JP2890584B2 (ja) * 1989-12-29 1999-05-17 ソニー株式会社 半導体装置の製造方法
JPH0787189B2 (ja) 1990-01-19 1995-09-20 松下電器産業株式会社 半導体装置の製造方法
JPH03227068A (ja) * 1990-02-01 1991-10-08 Casio Comput Co Ltd 薄膜トランジスタおよびその製造方法
KR950000141B1 (ko) * 1990-04-03 1995-01-10 미쓰비시 뎅끼 가부시끼가이샤 반도체 장치 및 그 제조방법
DE69127395T2 (de) * 1990-05-11 1998-01-02 Asahi Glass Co Ltd Verfahren zum Herstellen eines Dünnfilm-Transistors mit polykristallinem Halbleiter
US5126283A (en) 1990-05-21 1992-06-30 Motorola, Inc. Process for the selective encapsulation of an electrically conductive structure in a semiconductor device
US5227321A (en) 1990-07-05 1993-07-13 Micron Technology, Inc. Method for forming MOS transistors
JP3163092B2 (ja) * 1990-08-09 2001-05-08 株式会社東芝 半導体装置の製造方法
JPH04121914A (ja) * 1990-09-11 1992-04-22 Nippon Light Metal Co Ltd 絶縁アルミニウム線材及びその製造方法
JP2940880B2 (ja) * 1990-10-09 1999-08-25 三菱電機株式会社 半導体装置およびその製造方法
JP2947654B2 (ja) * 1990-10-31 1999-09-13 キヤノン株式会社 Ｍｉｓ型トランジスタ
SG63578A1 (en) * 1990-11-16 1999-03-30 Seiko Epson Corp Thin film semiconductor device process for fabricating the same and silicon film
JP2660451B2 (ja) * 1990-11-19 1997-10-08 三菱電機株式会社 半導体装置およびその製造方法
US5514879A (en) 1990-11-20 1996-05-07 Semiconductor Energy Laboratory Co., Ltd. Gate insulated field effect transistors and method of manufacturing the same
JPH04196328A (ja) * 1990-11-28 1992-07-16 Casio Comput Co Ltd 電界効果型トランジスタ
JP2999271B2 (ja) 1990-12-10 2000-01-17 株式会社半導体エネルギー研究所 表示装置
US5097301A (en) 1990-12-19 1992-03-17 Intel Corporation Composite inverse T-gate metal oxide semiconductor device and method of fabrication
JPH0817236B2 (ja) * 1990-12-25 1996-02-21 株式会社半導体エネルギー研究所 半導体装置
DE69125260T2 (de) * 1990-12-28 1997-10-02 Sharp Kk Ein Verfahren zum Herstellen eines Dünnfilm-Transistors und eines Aktive-Matrix-Substrates für Flüssig-Kristall-Anzeige-Anordnungen
US5236865A (en) * 1991-01-16 1993-08-17 Micron Technology, Inc. Method for simultaneously forming silicide and effecting dopant activation on a semiconductor wafer
JP2717234B2 (ja) * 1991-05-11 1998-02-18 株式会社 半導体エネルギー研究所 絶縁ゲイト型電界効果半導体装置およびその作製方法
US5289030A (en) * 1991-03-06 1994-02-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device with oxide layer
EP0499979A3 (en) 1991-02-16 1993-06-09 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device
US5521107A (en) 1991-02-16 1996-05-28 Semiconductor Energy Laboratory Co., Ltd. Method for forming a field-effect transistor including anodic oxidation of the gate
NL9100334A (nl) * 1991-02-26 1992-09-16 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij een zelfregistrerend kobalt- of nikkel-silicide gevormd wordt.
USRE36314E (en) 1991-03-06 1999-09-28 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect semiconductor devices having a LDD region and an anodic oxide film of a gate electrode
JP2794678B2 (ja) * 1991-08-26 1998-09-10 株式会社 半導体エネルギー研究所 絶縁ゲイト型半導体装置およびその作製方法
US5468987A (en) 1991-03-06 1995-11-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
JPH04287025A (ja) * 1991-03-15 1992-10-12 Hitachi Ltd 薄膜トランジスタ基板およびその製造方法ならびに液晶表示パネルおよび液晶表示装置
JP2794499B2 (ja) 1991-03-26 1998-09-03 株式会社半導体エネルギー研究所 半導体装置の作製方法
JPH04305939A (ja) * 1991-04-02 1992-10-28 Seiko Epson Corp 薄膜トランジスタの製造方法
JP3277548B2 (ja) 1991-05-08 2002-04-22 セイコーエプソン株式会社 ディスプレイ基板
JP2717237B2 (ja) * 1991-05-16 1998-02-18 株式会社 半導体エネルギー研究所 絶縁ゲイト型半導体装置およびその作製方法
US5151374A (en) 1991-07-24 1992-09-29 Industrial Technology Research Institute Method of forming a thin film field effect transistor having a drain channel junction that is spaced from the gate electrode
TW476451U (en) 1991-08-23 2002-02-11 Semiconductor Energy Lab Semiconductor device
JP2845303B2 (ja) 1991-08-23 1999-01-13 株式会社 半導体エネルギー研究所 半導体装置とその作製方法
US5545571A (en) 1991-08-26 1996-08-13 Semiconductor Energy Laboratory Co., Ltd. Method of making TFT with anodic oxidation process using positive and negative voltages
US5650338A (en) 1991-08-26 1997-07-22 Semiconductor Energy Laboratory Co., Ltd. Method for forming thin film transistor
JP3345756B2 (ja) * 1991-08-28 2002-11-18 セイコーエプソン株式会社 半導体装置の製造方法
US5182619A (en) * 1991-09-03 1993-01-26 Motorola, Inc. Semiconductor device having an MOS transistor with overlapped and elevated source and drain
JPH0793363B2 (ja) * 1991-09-25 1995-10-09 株式会社半導体エネルギー研究所 半導体集積回路およびその作製方法
US5495121A (en) 1991-09-30 1996-02-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2650543B2 (ja) * 1991-11-25 1997-09-03 カシオ計算機株式会社 マトリクス回路駆動装置
JP3092634B2 (ja) * 1991-11-29 2000-09-25 カシオ計算機株式会社 薄膜トランジスタの製造方法
JPH05152326A (ja) * 1991-12-02 1993-06-18 Matsushita Electric Ind Co Ltd 薄膜トランジスタの製造方法
JP2750380B2 (ja) * 1991-12-03 1998-05-13 株式会社 半導体エネルギー研究所 半導体装置の作製方法
JPH05175230A (ja) * 1991-12-20 1993-07-13 Toshiba Corp 薄膜トランジスタの製造方法
JP2564725B2 (ja) * 1991-12-24 1996-12-18 株式会社半導体エネルギー研究所 Ｍｏｓ型トランジスタの作製方法
JP3313432B2 (ja) 1991-12-27 2002-08-12 株式会社東芝 半導体装置及びその製造方法
US5485019A (en) 1992-02-05 1996-01-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
JPH05226364A (ja) * 1992-02-14 1993-09-03 Fujitsu Ltd Ｍｉｓ型電界効果トランジスタの製造方法
JP3186182B2 (ja) * 1992-03-25 2001-07-11 セイコーエプソン株式会社 薄膜半導体装置及びその製造方法
JPH05275449A (ja) * 1992-03-26 1993-10-22 Seiko Epson Corp 薄膜半導体装置及びその製造方法
JP3506445B2 (ja) * 1992-05-12 2004-03-15 沖電気工業株式会社 半導体装置の製造方法
US5241193A (en) 1992-05-19 1993-08-31 Motorola, Inc. Semiconductor device having a thin-film transistor and process
JPH06124962A (ja) * 1992-10-09 1994-05-06 Semiconductor Energy Lab Co Ltd 薄膜状半導体装置およびその作製方法
JP3252290B2 (ja) * 1992-06-26 2002-02-04 カシオ計算機株式会社 薄膜バイポーラトランジスタおよびそれを用いた薄膜半導体装置
US5252502A (en) * 1992-08-03 1993-10-12 Texas Instruments Incorporated Method of making MOS VLSI semiconductor device with metal gate
US5407837A (en) * 1992-08-31 1995-04-18 Texas Instruments Incorporated Method of making a thin film transistor
EP0589478B1 (en) * 1992-09-25 1999-11-17 Sony Corporation Liquid crystal display device
TW232751B (en) 1992-10-09 1994-10-21 Semiconductor Energy Res Co Ltd Semiconductor device and method for forming the same
US5576556A (en) 1993-08-20 1996-11-19 Semiconductor Energy Laboratory Co., Ltd. Thin film semiconductor device with gate metal oxide and sidewall spacer
US5403762A (en) 1993-06-30 1995-04-04 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a TFT
JP3587537B2 (ja) 1992-12-09 2004-11-10 株式会社半導体エネルギー研究所 半導体装置
JP3437863B2 (ja) 1993-01-18 2003-08-18 株式会社半導体エネルギー研究所 Ｍｉｓ型半導体装置の作製方法
US5985741A (en) * 1993-02-15 1999-11-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating the same
CN1542929B (zh) * 1993-03-12 2012-05-30 株式会社半导体能源研究所 半导体器件的制造方法
US5747355A (en) 1993-03-30 1998-05-05 Semiconductor Energy Laboratory Co., Ltd. Method for producing a transistor using anodic oxidation
JP3367618B2 (ja) * 1993-03-30 2003-01-14 株式会社半導体エネルギー研究所 薄膜トランジスタおよびその作製方法
US5572040A (en) 1993-07-12 1996-11-05 Peregrine Semiconductor Corporation High-frequency wireless communication system on a single ultrathin silicon on sapphire chip
JP2789293B2 (ja) * 1993-07-14 1998-08-20 株式会社半導体エネルギー研究所 半導体装置作製方法
US5492843A (en) 1993-07-31 1996-02-20 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating semiconductor device and method of processing substrate
JP2002033329A (ja) 1993-09-20 2002-01-31 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP2002033328A (ja) 1993-09-20 2002-01-31 Semiconductor Energy Lab Co Ltd 半導体装置
TW297142B (zh) 1993-09-20 1997-02-01 Handotai Energy Kenkyusho Kk
JP3212060B2 (ja) * 1993-09-20 2001-09-25 株式会社半導体エネルギー研究所 半導体装置およびその作製方法
JP2805590B2 (ja) * 1993-09-20 1998-09-30 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6777763B1 (en) * 1993-10-01 2004-08-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for fabricating the same
US5719065A (en) 1993-10-01 1998-02-17 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device with removable spacers
JP3030368B2 (ja) 1993-10-01 2000-04-10 株式会社半導体エネルギー研究所 半導体装置およびその作製方法
JPH07135323A (ja) 1993-10-20 1995-05-23 Semiconductor Energy Lab Co Ltd 薄膜状半導体集積回路およびその作製方法
KR970010685B1 (ko) 1993-10-30 1997-06-30 삼성전자 주식회사 누설전류가 감소된 박막 트랜지스터 및 그 제조방법
US5576231A (en) 1993-11-05 1996-11-19 Semiconductor Energy Laboratory Co., Ltd. Process for fabricating an insulated gate field effect transistor with an anodic oxidized gate electrode
TW299897U (en) 1993-11-05 1997-03-01 Semiconductor Energy Lab A semiconductor integrated circuit
KR100275717B1 (ko) * 1993-12-28 2000-12-15 윤종용 다결정 실리콘 박막 트랜지스터 제조 방법
JP2873660B2 (ja) 1994-01-08 1999-03-24 株式会社半導体エネルギー研究所 半導体集積回路の作製方法
HU214588B (hu) 1994-07-01 1998-04-28 EGIS Gyógyszergyár Rt. Eljárás bicikloheptán-származékot tartalmazó, CCK-rendszer gátló hatású gyógyászati készítmények előállítására
JP3330736B2 (ja) 1994-07-14 2002-09-30 株式会社半導体エネルギー研究所 半導体装置の作製方法
US5789762A (en) 1994-09-14 1998-08-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor active matrix circuit
JPH10135475A (ja) * 1996-10-31 1998-05-22 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
US5888888A (en) * 1997-01-29 1999-03-30 Ultratech Stepper, Inc. Method for forming a silicide region on a silicon body
US6255214B1 (en) * 1999-02-24 2001-07-03 Advanced Micro Devices, Inc. Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of source and drain regions
US6572900B1 (en) * 2000-06-09 2003-06-03 Wm. Wrigley, Jr. Company Method for making coated chewing gum products including a high-intensity sweetener
KR100491141B1 (ko) * 2001-03-02 2005-05-24 삼성에스디아이 주식회사 박막 트랜지스터 및 그의 제조방법과 이를 이용한 액티브매트릭스형 표시소자 및 그의 제조방법
US6566213B2 (en) * 2001-04-02 2003-05-20 Advanced Micro Devices, Inc. Method of fabricating multi-thickness silicide device formed by disposable spacers
US6441433B1 (en) * 2001-04-02 2002-08-27 Advanced Micro Devices, Inc. Method of making a multi-thickness silicide SOI device
TW480735B (en) * 2001-04-24 2002-03-21 United Microelectronics Corp Structure and manufacturing method of polysilicon thin film transistor
US7112495B2 (en) * 2003-08-15 2006-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit
JP2006012991A (ja) * 2004-06-23 2006-01-12 Toshiba Corp 半導体記憶装置
US7575959B2 (en) * 2004-11-26 2009-08-18 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device

Cited By (5)

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Publication number Priority date Publication date Assignee Title
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