CN1212786A - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
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Abstract
通过使半导体元件(1)上形成的凸起电极(4)的高度发生塑性变形,以便使该凸起电极(4)的前端面与电路基板(5)一侧的电极端子(7)面的距离变得均匀,从而提供半导体元件与电路基板的导电性连接是可靠的半导体装置。另外,提供下述的半导体装置的制造方法:在将半导体元件(1)配置在电路基板(5)的预定的位置上后,从半导体元件(1)的背面加压,促使凸起电极(4)发生塑性变形,使凸起电极(4)的高度变得适当,由此,即使连接半导体元件(1)的相对一侧、即电路基板(5)上形成的电极端子(7)面的高度尺寸存在偏差,也能可靠地进行半导体元件(1)与电路基板(5)的导电性连接。
Description
技术领域
本发明涉及半导体装置,特别是涉及使用了倒装芯片(flipchip)安装技术的半导体装置及其制造方法。
背景技术
近年来,半导体元件的集成度提高,正朝着半导体装置的小型化和连接端子的窄间距化的方向发展。因此,使用了倒装芯片安装技术的半导体装置的开发正在活跃地进行。以下,一边参照附图,一边说明现有的使用了倒装芯片安装技术的半导体装置的一例。
在图9中示出现有的使用了倒装芯片安装技术的半导体装置的剖面图。在半导体元件101的元件形成面上形成铝电极端子102,用由氧化硅膜或氮化硅膜等构成的绝缘膜103覆盖除铝电极端子102以外的部分。在铝电极端子102面上形成由Au、Cu等导电性金属材料构成的凸起电极104。另一方面,在由树脂、陶瓷、玻璃等绝缘物构成的电路基板105的主面上形成所希望的电路图形106和电极端子107。
将电极端子107连接到电路图形106,在倒装芯片安装时进行与半导体元件101的导电性连接。由导电性粘接剂108进行凸起电极104与电极端子107的导电性连接。导电性粘接剂108是在树脂中包含Ag、Cu、Ni等导电性金属材料的粉体的粘接剂。将绝缘树脂109充填到半导体元件101与电路基板105之间的间隙部中。如果绝缘树脂109硬化,则利用其硬化收缩应力粘接了半导体元件101和电路基板105后,将两者牢固地固定在一起。因此,可提高半导体装置中的半导体元件101与电路基板105的连接的机械强度,可保持稳定的固定状态。
使用图10的示出制造工艺的工序图说明如以上那样构成的现有的半导体装置制造方法。首先,用通常的半导体制造工艺制造形成了多个半导体元件101的半导体晶片,在上述半导体元件101中形成了所希望的元件、布线和绝缘膜103。
其次,使探针接触铝电极端子102,进行电检查,判定半导体元件101是否合格,在此之后形成凸起电极104。再者,将半导体晶片切割成各个半导体元件101。
另一方面,使用Au、Cu等导电性金属材料,在由绝缘物构成的电路基板105上预先形成所希望的电路图形106及电极端子107,以倒装方式将半导体元件101配置在该电路基板105上,以便能通过导电性粘接剂108进行规定的电极端子107与凸起电极104的导电性连接。
其后,进行加热处理,使导电性粘接剂108硬化,进行电检查,确认工作状态。然后,在确认了正常的工作后,利用毛细管现象将液状的环氧系列等的具有绝缘性的树脂109充填到半导体元件101与电路基板105之间。在充填结束后,进行加热处理等,使绝缘树脂109硬化,进行倒装芯片安装。
经过以上那样的制造工艺,制造了使用了倒装芯片安装技术的半导体装置。
但是,在上述的现有的半导体装置及其制造方法中,如图11所示,主要由于电路基板105的局部的翘曲及波纹等,在电路基板105的平坦精度方面存在偏差,此外,在电极端子107部的膜厚精度方面也存在偏差,因此,位于一个半导体元件区域内的电路基板一侧的电极端子107的前端面不在一定的水平面上,而是在高度方向上存在偏差。
因此,在以倒装方式安装半导体元件101时,由于在电路基板105的凹部处半导体元件101与电路基板105之间的间隙部的尺寸比其它部分大,故导电性粘接剂108不能到达位于该凹部的电极端子107的前端面,存在有时发生导电性连接不良的情况。
发明的公开
本发明的目的在于,为了解决上述的现有问题,通过更可靠地并且稳定地将半导体元件与电路基板导电性地连接起来,提供质量极为稳定的、生产性良好的半导体装置及其制造方法。
为了达到上述目的,本发明的半导体装置是使用了倒装芯片(flipchip)安装技术的半导体装置,在该倒装芯片安装技术中通过在半导体元件的元件形成面上的电极端子部上形成的导电性金属材料的凸起电极、导电性粘接剂和电路基板上的电极端子来进行上述半导体元件与上述电路基板的导电性连接,其特征在于:使上述各凸起电极在高度方向上产生塑性变形,以便使上述各凸起电极的前端面与通过上述导电性粘接剂而相对的各电极端子面之间的距离分别变得均匀。
按照上述那样的半导体装置,由于对凸起电极的高度适当地进行加工,以便使各凸起电极的前端面与通过上述导电性粘接剂而相对的各电极端子面之间的距离分别变得均匀,故可使半导体元件与电路基板的导电性连接变得可靠。
在上述半导体装置中,上述凸起电极的材料最好是从Au和Cu中选出的至少一种金属材料。
此外,上述各凸起电极的前端面与通过上述导电性粘接剂而相对的各电极端子面之间的距离最好是1μm~10μm的范围。
此外,最好使用下述倒装芯片安装技术,在该倒装芯片安装技术中,通过在半导体元件的元件形成面上的电极端子、导电性粘接剂和电路基板上的电极端子部上部上形成的导电性金属材料的凸起电极来进行上述半导体元件与上述电路基板的导电性连接。
在上述的电路基板一侧形成了凸起电极的较为理想的半导体装置中,在半导体元件的元件形成面上的电极端子上最好形成了由导电性金属材料的层叠膜构成的阻挡层。
按照形成了上述阻挡层的较为理想的半导体装置,可防止半导体元件的元件形成面上的电极端子的腐蚀。
此外,在上述半导体装置中,凸起电极的凸出高度最好实际上相同。
在上述的凸起电极的凸出高度实际上相同的较为理想的半导体装置中,在进行导电性粘接剂的粘接前,最好预先将凸起电极压到硬质材料的平面部分上,使各凸起电极的前端面的高度变得均匀。
此外,在上述的将凸起电极压到硬质材料的平面部分上使各凸起电极的前端面的高度变得均匀的较为理想的半导体装置中,通过将上述凸起电极压到硬质材料的平面部分上,最好使上述凸起电极的前端面的压力在1.5×108~5.0×108N/m2的范围内。
此外,上述硬质材料的平面性在距离20mm间最好在4μm以内。
其次,本发明的第1种半导体装置的制造方法的特征在于:在半导体元件的元件形成面上形成了凸起电极之后,在使导电性粘接剂转移到凸起电极的顶部上,用倒装(face down)方式将半导体元件安装到电路基板上时,通过从半导体元件的背面加压,使半导体元件的凸起电极发生塑性变形,以便使半导体元件的各凸起电极的前端面和与其相对的电路基板一侧的电极端子面之间的距离分别变得均匀。
按照上述第1种半导体装置的制造方法,由于通过从半导体元件的背面加压,能对凸起电极的高度适当地进行加工,以便使各凸起电极的前端面与通过上述导电性粘接剂而相对的各电极端子面之间的距离分别变得均匀,故可容易并廉价地制造可靠性极高的半导体装置。
在上述第1种半导体装置的制造方法中,通过从上述半导体元件的背面加压,使凸起电极的前端面的压力最好在1.5×108~5.0×108N/m2的范围内。
此外,最好在使半导体元件的凸起电极发生塑性变形后,使导电性粘接剂转移到半导体元件的各凸起电极的顶部上,再用倒装方式将半导体元件安装到电路基板上。
在使上述的凸起电极发生塑性变形后再用倒装方式将半导体元件安装到电路基板上的较为理想的半导体装置的制造方法中,在用倒装方式将半导体元件安装到电路基板上时,由于几乎不对半导体元件加压,故可防止半导体元件与电路基板之间的位置偏移。
其次,本发明的第2种半导体装置的制造方法的特征在于:在电路基板的电极端子上形成了凸起电极后,将该凸起电极压到硬质材料的平面部分上,使各凸起电极的前端面的高度变得均匀,其后在使导电性粘接剂转移到上述各凸起电极的顶部上之后,用倒装方式将上述半导体元件安装到电路基板上。
按照上述第2种半导体装置的制造方法,由于没有对半导体元件加压的工序,故可减小施加到半导体元件上的损伤。
在上述第2种半导体装置的制造方法中,通过将上述凸起电极压到硬质材料的平面部分上,使上述凸起电极的前端面的压力最好在1.5×108~5.0×108N/m2的范围内。
此外,上述硬质材料的平面性在距离20mm间最好在4μm以内。
附图的简单说明
图1是与本发明的实施例1有关的半导体装置的剖面图。
图2是示出与本发明的实施例1有关的半导体装置的制造工艺的工序图。
图3A是在图2的制造工艺中,导电性粘接剂转移工序中的半导体装置的剖面图,图3B是从安装工序至半导体元件加压工序中的半导体装置的剖面图。
图4是示出与本发明的实施例2有关的半导体装置的制造工艺的工序图。
图5A是在图4的制造工艺中,从安装工序至半导体元件加压工序中的半导体装置的剖面图,图3B是导电性粘接剂转移工序中的半导体装置的剖面图。
图6是与本发明的实施例3有关的半导体装置的剖面图。
图7是示出与本发明的实施例3有关的半导体装置的制造工艺的工序图。
图8A是示出了在图7的电路基板加压工序中,电路基板加压前的状态的半导体装置的剖面图,图8B是示出了电路基板加压后的状态的半导体装置的剖面图。
图9是使用了现有的倒装芯片安装技术的半导体装置的一例的剖面图。
图10是示出使用了现有的倒装芯片安装技术的半导体装置的制造工艺的一例的工序图。
图11是现有的半导体装置的一例的剖面图。
用于实施发明的最佳形态
以下,使用附图就本发明的半导体装置及其制造方法的实施例进行说明。
(实施例1)
图1是与实施例1有关的半导体装置的剖面图。如图1中所示,在半导体元件1的元件形成面上形成铝电极端子2,用由氧化硅膜或氮化硅膜等构成的绝缘膜3覆盖除铝电极端子2以外的部分。
在铝电极端子2上形成由Au、Cu等导电性金属材料构成的凸起电极4。另一方面,在由树脂、陶瓷、玻璃等绝缘物构成的电路基板5上形成所希望的电路图形6和电极端子7。将电极端子7连接到电路图形6,在倒装芯片安装时进行与半导体元件1的导电性连接。导电性粘接剂8是在树脂中包含Ag、Cu、Ni等导电性金属材料的粉体的粘接剂。将绝缘树脂9充填到半导体元件1与电路基板5之间的间隙部中。
如果绝缘树脂9硬化,则利用其硬化收缩应力粘接了半导体元件1和电路基板5后,将半导体元件1和电路基板5牢固地固定在一起。因此,可提高半导体装置中的半导体元件1与电路基板5的连接的机械强度,可保持稳定的固定状态。
如图1中所示,根据电路基板5上的电极端子7的高度,对凸起电极4的高度进行加工。即,主要起因于在电路基板5的主面上的平坦精度的偏差以及在电极端子7的膜厚精度的偏差,电极端子7的前端面的高度方向的位置方面存在偏差,但可根据该偏差,利用塑性变形来降低凸起电极4的高度。此时,由于塑性变形前的凸起电极4的高度的偏差比电极端子7的前端面的高度方向的位置的偏差小,该高度大致是一定的,故根据电极端子7的前端面的高度方向的位置,因塑性变形引起的凸起电极4的高度的变化量不同。具体地说,电极端子7的前端面与半导体元件1的距离越短,凸起电极4的高度的变化量越大。
因此,半导体元件1一侧的凸起电极4的前端面与电路基板5一侧的电极端子7面之间的距离变得均匀。该距离是1μm~10μm的范围是较为理想的。该距离约为5μm则更为理想。结果,由转移到凸起电极4的顶部的导电性粘接剂8构成的接合层能可靠地到达电路基板5一侧的电极端子7面并附着于其上,可防止导电性连接不良的发生。
其次,参照图2、3说明与实施例1有关的半导体装置的制造方法。图2是示出与实施例1有关的半导体装置的制造工艺的工序图。如图2中所示,首先,与现有工艺相同,在半导体元件1的元件形成面上形成元件。
其次,使用球键合法在铝电极端子2面上形成了Au的凸起电极4后,将半导体晶片切割成各个半导体元件1。其后,只在凸起电极4的顶部转移了必要量的导电性粘接剂8后,预先配置在形成了所希望的电路图形6及电极端子7的电路基板5上的规定位置上之后,从半导体元件1的背面加压,促使凸起电极4发生塑性变形,进行使凸起电极4的高度变得适当的加工。
最后,进行加热处理使导电性粘接剂8硬化,通过电检查确认了正常的工作后,在半导体元件1与电路基板5之间充填液状的环氧系列等的绝缘性树脂9,使其硬化,作成半导体装置。
图3是说明在图2中所示的制造工艺中从导电性粘接剂转移至半导体元件加压工序为止的图。在图3中,图中示出的号码与图1相同。
图3A示出了在图2的制造工艺中,导电性粘接剂转移工序中的半导体装置的剖面图,图3B示出了从安装工序至半导体元件加压工序中的半导体装置的剖面图。
如图3A所示,只在凸起电极4的顶部附近转移必要量的导电性粘接剂8。其次,如图3B所示,在以倒装方式将半导体元件1配置在电路基板5上的规定位置上后,进行到从半导体元件1的背面施加压力P,促使凸起电极4发生塑性变形以便使凸起电极4的高度变得适当为止的加工,同时结束以倒装方式的安装。
从半导体元件1的背面施加的压力,在上述凸起电极4的前端面内最好在1.5×108~5.0×108N/m2的范围内。如果是这样的压力范围,则能将凸起电极4的前端面与电极端子7面之间的距离均匀地形成为1μm~10μm。
再有,在形成凸起电极4时,也可使用转移凸点法,将预先在其它地方制造的Au、Cu等导电性金属材料块压到铝电极端子2面上,施加压力、热和超声波振动等,使导电性金属材料块附着于铝电极端子2面上,作成凸起电极4。
此外,也可使用无电解或电解的电镀法,在铝电极端子2面上析出导电性金属材料,作成凸起电极4。
如上所述,按照与实施例1有关的半导体装置的制造方法,与现有的工艺比较,由于可同时进行对凸起电极加压的工序和安装半导体元件的工序,故也同时具有可谋求工序的简化的效果。
(实施例2)
其次,参照图4、5说明有关本发明的制造方法的半导体装置的实施例2。图4是示出与实施例2有关的半导体装置的制造工艺的工序图。在与上述实施例1有关的半导体装置的制造方法中,先将转移了导电性粘接剂的半导体元件以倒装方式配置在电路基板上后,进行加压,同时进行凸起电极的塑性变形和安装。
在与上述实施例2有关的半导体装置的制造方法中,预先对以倒装方式配置在电路基板上的半导体元件加压,进行了凸起电极的塑性变形后,一旦在将半导体元件从电路基板取下,进行了导电性粘接剂的转移后,再实施倒装方式的安装。
图5是说明在图4中示出的制造工艺中从倒装方式的安装(1)到导电性粘接剂转移为止的图。在图5中,图中示出的号码与图1相同。图5A示出了在图4的制造工艺中,从安装工序至半导体元件加压工序中的半导体装置的剖面图,图5B示出了导电性粘接剂转移工序中的半导体装置的剖面图。
如图5A中所示,从背面对以倒装方式配置在电路基板5上的规定位置上的半导体元件1施加压力P,进行适当的凸起电极4的塑性变形。
其次,一旦在将半导体元件1从电路基板5取下后,如图5B中所示,只在凸起电极4的顶部转移了必要量的导电性粘接剂8。其后,再以倒装方式安装到电路基板5的规定位置上。通过这样做,可制造具有与图1中示出的结构实际上相同的结构的半导体装置。
在与上述实施例1有关的半导体装置的制造方法中,由于在半导体元件的安装时加压,故存在半导体元件与电路基板的位置关系偏离预定的位置的可能性,但按照与实施例2有关的半导体装置的制造方法,由于在安装时几乎不进行加压,故半导体元件与电路基板的位置关系偏离预定的位置的可能性小。因此,适合于具有微细间距的连接结构那样的安装精度的半导体装置的制造。
(实施例3)
其次,一边参照图6至图8,一边说明与实施例3有关的半导体装置及其制造方法。图6是示出与实施例3有关的半导体装置的剖面图。在图6中,12是由在铝电极端子面上形成的Cr和Au的层叠膜构成的阻档层,14是在电路基板一侧的电极端子面上形成的凸起电极。其它与图1相同。
与图1中示出的与实施例1有关的半导体装置的结构不同之点在于下述两点,第1点是由于如果导电性粘接剂直接与铝电极端子2面接触,则存在铝受到腐蚀的可能性,故形成了阻档层12,第2点是在电路基板5一侧的电极端子7面上形成由Au、Cu等导电性金属材料构成的凸起电极14。
在与本实施例有关的半导体装置中,也与实施例1有关的半导体装置相同,如图6中所示,根据电路基板5上的电极端子7的高度方向的位置,对凸起电极14的高度进行加工。即,主要起因于在电路基板5的主面上的平坦精度的偏差以及在电极端子7的膜厚精度的偏差,电极端子7的高度方向的位置方面存在偏差,但可根据该偏差,利用塑性变形来降低凸起电极14的高度。此时,由于塑性变形前的凸起电极14的高度的偏差比电极端子7的高度方向的位置的偏差小,该高度大致是一定的,故根据电极端子7的前端面的高度方向的位置,因塑性变形引起的凸起电极14的高度的变化量不同。具体地说,电极端子7的前端面与半导体元件1的距离越短,凸起电极14的高度的变化量越大。
因此,半导体元件1一侧的阻档层12的表面与凸起电极14的前端面之间的距离变得均匀。与实施例相同,该距离是1μm~10μm的范围是较为理想的。该距离约为5μm则更为理想。结果,由转移到凸起电极14的顶部的导电性粘接剂8构成的接合层能可靠地到达半导体元件1一侧的阻档层12的面上并附着于其上,不发生导电性连接不良。
其次,参照图7、8说明与实施例3有关的半导体装置的制造方法。图7是示出与实施例3有关的半导体装置的制造工艺的工序图。如图7中所示,在半导体元件1的元件形成面上形成元件后,在铝电极端子2面上用电镀法形成层叠了Cr和Au的阻档层12。其后,在进行了检查后,将半导体晶片切割成各个半导体元件1。
另一方面,在电路基板5的主面上形成了所希望的电路图形6及电极端子7后,用球键合法在电极端子7的面上形成Au的凸起电极14。
其次,通过将该凸起电极14压到具有所希望的平坦精度并由硬质材料构成的平面板上,促使凸起电极14发生适当的塑性变形,使凸起电极14前端面的高度变得均匀。
其后,在将必要量的导电性粘接剂8糊剂只转移到凸起电极14的顶部上之后,在将半导体元件1以倒装方式安装到电路基板5上的规定位置上后,进行加热处理使导电性粘接剂8硬化,通过电检查确认了正常的工作,最后在半导体元件1与电路基板5之间充填液状的环氧系列等的具有绝缘性的树脂9,使其硬化,作成半导体装置。
图8是说明在图7中示出的制造工艺中,从电路基板加压至导电性粘接剂转移工序为止的图。在图7中,图中示出的号码与图6相同。图8A是示出了在图7的电路基板加压工序中,电路基板加压前的状态的半导体装置的剖面图,图8B是示出了电路基板加压后的状态的半导体装置的剖面图。
如图8A中所示,通过将在电路基板5的主面上形成的凸起电极14压到具有所希望的平坦精度并由硬质材料构成的平面板上,促使凸起电极14发生适当的塑性变形,使凸起电极14前端面的高度变得均匀。关于上述硬质材料的平面性,在距离20mm之间最好在4μm以内。压到由硬质材料构成的平面板上的压力,在上述凸起电极4的前端面内最好在1.5×108~5.0×108N/m2的范围内。其后,如图8B中所示,在使导电性粘接剂8糊剂只转移到凸起电极14的顶部上之后,进行半导体元件1的安装。
再有,在形成凸起电极14时,也可使用转移凸点法,将预先在其它地方制造的Au、Cu等导电性金属材料块压到电极端子7的面上,施加压力、热和超声波振动等,使导电性金属材料块附着于电极端子7面上,作成凸起电极14。
此外,也可使用无电解或电解的电镀法,在电极端子7面上析出导电性金属材料,作成凸起电极14。
此外,也可采用使用了糊剂的厚膜制膜技术。关于阻档层12,也可使用Cr-Au膜以外的材料。
此外,在用除铝以外的Au、Pt等难以被侵蚀的材料形成铝电极端子2的情况下,阻档层不是特别需要。
如上所述,按照与实施例3有关的半导体装置的制造方法,由于没有对半导体元件加压的工序,故具有施加到半导体元件上的损伤少的优点。特别是在用Ga-As等化合物半导体等脆性材料制造半导体元件的情况下,是有效的。
如上所述,按照本发明的半导体装置,由于对凸起电极的高度进行适当的加工,以便使各凸起电极的前端面与通过上述导电性粘接剂相对的各电极端子面之间的距离分别变得均匀,故可使半导体元件与电路基板的导电性连接变得可靠。
此外,按照本发明的半导体装置的制造方法,由于能通过从半导体元件的背面加压,对凸起电极的高度进行适当的加工,以便使各凸起电极的前端面与通过上述导电性粘接剂相对的各电极端子面之间的距离分别变得均匀,故可容易且廉价地制造半导体元件与电路基板的导电性连接的可靠性极高的半导体装置。
产业上利用的可能性
如上所述,由于本发明的半导体装置中,半导体元件与电路基板的导电性连接的可靠性极高,故可作为对半导体元件与电路基板进行导电性连接的半导体装置来利用。
此外,按照本发明的半导体装置的制造方法,由于能通过使各凸起电极发生塑性变形,使半导体元件与电路基板的导电性连接变得可靠,故可作为使用了倒装芯片安装技术的半导体装置的制造方法来利用。
Claims (12)
1.一种半导体装置,该半导体装置使用了倒装芯片安装技术,在该倒装芯片安装技术中,通过在半导体元件的元件形成面上的电极端子部上形成的导电性金属材料的凸起电极、导电性粘接剂和电路基板上的电极端子来进行所述半导体元件与所述电路基板的导电性连接,其特征在于:使所述各凸起电极在高度方向上产生塑性变形,以便使所述各凸起电极的前端面与通过所述导电性粘接剂而相对的各电极端子面之间的距离分别变得均匀。
2.如权利要求1中所述的半导体装置,其特征在于:所述凸起电极的材料是从Au和Cu中选出的至少一种金属材料。
3.如权利要求1中所述的半导体装置,其特征在于:所述各凸起电极的前端面与通过所述导电性粘接剂而相对的各电极端子面之间的距离是1μm~10μm的范围。
4.如权利要求1中所述的半导体装置,其特征在于:使用下述倒装芯片安装技术,在该倒装芯片安装技术中,通过在半导体元件的元件形成面上的电极端子、导电性粘接剂和电路基板上的电极端子部上形成的导电性金属材料的凸起电极来进行所述半导体元件与所述电路基板的导电性连接。
5.如权利要求4中所述的半导体装置,其特征在于:在所述半导体元件的元件形成面上的电极端子上形成了由导电性金属材料的层叠膜构成的阻挡层。
6.如权利要求1中所述的半导体装置,其特征在于:所述凸起电极的凸出高度实际上相同。
7.如权利要求6中所述的半导体装置,其特征在于:在进行导电性粘接剂的粘接前,预先将所述凸起电极压到硬质材料的平面部分上,使各凸起电极的前端面的高度变得均匀。
8.如权利要求7中所述的半导装置,其特征在于:通过将所述凸起电极压到硬质材料的平面部分上,使所述凸起电极的前端面的压力在1.5×108~5.0×108N/m2的范围内。
9.如权利要求7中所述的半导装置,其特征在于:所述硬质材料的平面性在距离20mm间在4μm以内。
10.一种半导体装置的制造方法,其特征在于:在半导体元件的元件形成面上形成了凸起电极之后,在使导电性粘接剂转移到凸起电极的顶部上,用倒装方式将半导体元件安装到电路基板上时,通过从半导体元件的背面加压,使半导体元件的凸起电极发生塑性变形,以便使半导体元件的各凸起电极的前端面和与其相对的电路基板一侧的电极端子面之间的距离分别变得均匀。
11.如权利要求10中所述的半导装置的制造方法,其特征在于:通过从半导体元件的背面加压,使所述凸起电极的前端面内的压力在1.5×108~5.0×108N/m2的范围内。
12.如权利要求10中所述的半导体装置的制造方法,其特征在于:在使半导体元件的凸起电极发生塑性变形后,使导电性粘接剂转移到半导体元件的各凸起电极的顶部上,再用倒装方式将半导体元件安装到电路基板上。
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JP49065/96 | 1996-03-06 | ||
JP8049065A JP2951882B2 (ja) | 1996-03-06 | 1996-03-06 | 半導体装置の製造方法及びこれを用いて製造した半導体装置 |
JP49065/1996 | 1996-03-06 |
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CN1212786A true CN1212786A (zh) | 1999-03-31 |
CN1175480C CN1175480C (zh) | 2004-11-10 |
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US (1) | US6452280B1 (zh) |
EP (2) | EP1191578A3 (zh) |
JP (1) | JP2951882B2 (zh) |
KR (1) | KR100300758B1 (zh) |
CN (1) | CN1175480C (zh) |
DE (1) | DE69722661T2 (zh) |
WO (1) | WO1997033313A1 (zh) |
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CN105739198A (zh) * | 2014-12-24 | 2016-07-06 | 乐金显示有限公司 | 用于显示装置的阵列基板及显示装置 |
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- 1997-03-05 KR KR1019980707001A patent/KR100300758B1/ko not_active IP Right Cessation
- 1997-03-05 CN CNB971927987A patent/CN1175480C/zh not_active Expired - Fee Related
- 1997-03-05 US US09/117,695 patent/US6452280B1/en not_active Expired - Lifetime
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100356559C (zh) * | 2003-09-24 | 2007-12-19 | 财团法人工业技术研究院 | 倒装芯片封装结构及其制造方法 |
CN100421244C (zh) * | 2005-02-28 | 2008-09-24 | 株式会社日立制作所 | 电子装置 |
CN101197338B (zh) * | 2006-10-31 | 2011-06-08 | 三洋电机株式会社 | 半导体模块、半导体模块的制造方法及便携式设备 |
CN105739198A (zh) * | 2014-12-24 | 2016-07-06 | 乐金显示有限公司 | 用于显示装置的阵列基板及显示装置 |
Also Published As
Publication number | Publication date |
---|---|
DE69722661T2 (de) | 2004-05-13 |
US6452280B1 (en) | 2002-09-17 |
JP2951882B2 (ja) | 1999-09-20 |
WO1997033313A1 (fr) | 1997-09-12 |
EP1191578A2 (en) | 2002-03-27 |
KR100300758B1 (ko) | 2001-11-02 |
KR19990087563A (ko) | 1999-12-27 |
CN1175480C (zh) | 2004-11-10 |
JPH09246320A (ja) | 1997-09-19 |
EP1191578A3 (en) | 2002-05-08 |
EP0951063A4 (zh) | 1999-10-20 |
DE69722661D1 (de) | 2003-07-10 |
EP0951063A1 (en) | 1999-10-20 |
EP0951063B1 (en) | 2003-06-04 |
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