CN1198337C - 具有可熔焊区和可细丝压焊区的金属再分布层 - Google Patents

具有可熔焊区和可细丝压焊区的金属再分布层 Download PDF

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CN1198337C
CN1198337C CNB00815449XA CN00815449A CN1198337C CN 1198337 C CN1198337 C CN 1198337C CN B00815449X A CNB00815449X A CN B00815449XA CN 00815449 A CN00815449 A CN 00815449A CN 1198337 C CN1198337 C CN 1198337C
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layer
pressure welding
filament
metal
nickel dam
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CN1387681A (zh
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K·M·兰
J·A·科瓦茨
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Atmel Corp
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Atmel Corp
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Abstract

本发明提供一种再分布金属化方案，除现有压焊区(102)外，还组合焊块(122)和细丝压焊区(132)，以强化半导体器件的连接性，尤其是倒装芯片应用中的连接性。其制作方法包括在再分布淀积步骤期间形成附加压焊区。再分布层用的金属(204、206、208)提供形成焊块用的可熔焊表面和细丝压焊用的可压焊表面。

Description

具有可熔焊区和可细丝压焊区的金属再分布层
技术领域
本发明一般涉及半导体器件，尤其涉及金属再分布层。
背景技术
现代IC应用通常对I/O引出线要求高。然而，引出线高要求给传统细丝压焊或TAB IC组件提出问题。细丝压焊和TAB封装要求在半导体芯片外围配置芯片压焊区。由于处理工艺的改进不断减小器件几何尺寸，尽管I/O总数一直升高以适应功能的增多，芯片尺寸却某种程度上保持不变。因此，细丝压焊(以下简称丝焊)技术存在最小压焊间距的极限。
焊块阵的开发通过利用芯片本身的表面积提供接点区，显著提高半导体器件的引出线性能。此引出线方案的关键要素是采用金属再分布层。这是配置在已完工半导体芯片顶上的连接层。形成从该连接层到配置在芯片外围附近的底下芯片压焊区的电连接。该连接用于从外围在整个芯片表面区再分布压焊区，因而可增多芯片外的I/O引出线。
随着引出线要求继续增多，需要组合焊块形成法与丝焊法，以提供更高的引出线性能。然而，各法所用材料不兼容。焊块适用的材料机械粘着性差，不适合用于丝焊。例如铜是高级可熔焊材料，但选作丝焊则欠妥。其原因在于铜容易形成氧化层，呈现压焊性能差。虽然能在其中提供进行适当压焊的环境，但其费用昂贵得付不起，因而从未开发此工艺。
同样，展现丝焊性能好的材料一般在熔焊时欠佳。例如，铝是压焊的好材料。然而，为了达到熔焊接点牢固，必须去除铝上形成的氧化层。去除氧化层用的腐蚀剂激烈侵蚀，除氧化层外，还会腐蚀底铝部分。虽然采用块铝时可容许这种过腐蚀，但对薄膜铝结构则因开始铝就很少，存在问题。
因此，需要一种能适应焊块形成和丝焊的再分布金属化。希望有一种方法，妥善综合现有再分布金属化法，而且提供焊块和丝焊结构。
发明内容
本发明的再分布金属化方案除提供可用于重新定位半导体芯片上存在的压焊区的新细丝压焊区，还包含常规焊块。此方案改善器件的连接性选择，尤其是倒装芯片的应用中。
根据本发明的再分布金属化的制作包括淀积钝化层和按需形成底压焊区开口。然后，在钝化层顶上淀积了金属层加以覆盖，并进行蚀刻，以形成需要的再分布线迹。同时，还对附加细丝压焊区制作图案。淀积第2钝化层，并且在要形成焊块的位置和附加细丝压焊区对应的部位进行蚀刻，以暴露底金属化顶上的区域。接着，形成焊块。一实施例中，接着进行蚀刻步骤，在附加细丝压焊区的位置暴露了三金属层的底金属层。
附图说明
图1是典型IC器件俯视图，示出底细丝压焊区和金属再分布层。
图2A～2I示出按照本发明产生再分布层的处理步骤。
图3A～3C示出处理阶段中间结果的立体图，以便更好理解本发明的上述各方面。
具体实施方式
参考图1，本发明针对一种包含在其再分布层组合焊块和细丝压焊区的再分布金属化的方案。半导体器件100包含底基片，该基片具有其上形成的多个细丝压焊区102(用虚线表示)。金属层承载具有与底细丝压焊区102电接触的第1端的多条线迹142～148。沿这些线迹配置焊块122和附加细丝压焊区132～138。焊块和附加细丝压焊区借助这些线迹在半导体器件表面上有效“再分布”，因而提供较多的引出线总数。通过在再分布层将焊块安排成焊块阵达到较高的I/O引脚组装密度。附加细丝压焊区132～138允许在原压焊区102的位置以外的位置进行基片与IC组件之间的丝焊。下文将讨论，这在堆叠芯片配置中特别有利。
图2A～2I示出本发明的处理步骤。这些图从图1中线2-2剖切而得，示出如何形成再分布金属化。图2A以基本完工的半导体晶片104开始。会理解，该晶片包含所需结构基片层以及充分规定其谋求功能的电路的关联金属和绝缘层，其中包括连接IC组件需要的丝焊I/O焊区102。
图2A中，在晶片104的上表面淀积介电材料的钝化层202。可用任何一种绝缘材料，例如，层202采用光可限定的苯并环丁烷(BCB)。
采用公知的光刻制版和蚀刻技术形成下降到底细丝压焊区102的通路孔212(图2C)。接着，在蚀刻的钝化层202上淀积3层金属结构240加以覆盖。通常用每次喷镀一层的喷镀法达到这点。首先，喷镀铝层204。其次，用镍靶在铝层上喷镀淀积镍层206。最后，提供铜靶，在镍层上淀积铜层208。铝层用作粘着层，而镍层用作铜层和铝层之间的阻档层。
然后，对3金属层240进行光刻制版处理和蚀刻，以规定包含再分布层的线迹。又，根据本发明，在3金属层规定附加细丝压焊区132～138。图2D中，用虚线指示线迹142和附加焊区132。图3A的立体图较清楚地说明本发明的这点。图3A中的说明示出在钝化层202的顶上形成线迹142，其第1端通过通路孔212与底焊区102电接触。线迹142的另一端终接也形成在钝化层上的新细丝压焊区132。
然后，在蚀刻的3金属层240上淀积第2钝化层222(图2E)，以提供对水分和污染物的防护密封，并用作防擦伤保护层。然后，蚀刻掉第2钝化层222，以开放通过钝化层到3金属层的焊块点214。此外，通过钝化层到3金属层还形成焊区开口216。该焊区开口与3金属层上形成的细丝压焊区132重合。此步骤形成的开口214和216(由图2F所示)使3金属层的最上层(即铜层208)表面暴露。图3B的立体图更清楚地示出此处理阶段的晶片。图中，用虚线示出线迹142和附加细丝压焊区132，指明它们在绝缘层222下方。还示出开口21和216，使底铜层208暴露。
再参考图2G，焊块点214用焊料和适合的阻挡金属填充，用公知的受控塌片构造法(C4法)或其他球栅阵处理法形成可靠的焊块122。回想铜很适合用于形成焊块，因而焊块122具有对底再分布金属化的强机械结合。
再回想由于铜的高氧化率，铜用作压焊欠佳，而铝是可压焊金属。因此，根据本发明，形成焊块的晶片受到后续蚀刻步骤的处理，去除通过开口216暴露的铜层和镍层。用公知的任何一种化学湿蚀刻法去除铝层和镍层，能达到这点。图2H中示出该蚀刻步骤的结果，其中细丝压焊区132目前由单一铝层组成。在后续的丝焊操作中对铝层的表面压焊细丝(例如图2I中的细丝230)。
以上较佳实施例讨论铜-镍-铝3金属层的使用。可用铝以外的金属，包括钯和铂，作为可压焊层。如果金属的最上层为金，也可达到本发明焊块和细丝压焊区布局。因此，本发明的另一实施例中，采用金。于是，对图2D而言，能在钝化层202上喷镀最底下的导电金属粘着层204，该导电金属粘着层204可包含铝、钛、钛钨合金或其它导电金属材料。典型的粘着金属包括铝和钛钨合金(TiW)。如上文那样，蚀刻金属层，形成包含再分布层和附加细丝压焊区132～138的期望线迹142～148。
接着，淀积镍层206后，淀积金层208。然后，如图2E和2F所示，淀积第2钝化层222并加以蚀刻，以形成开口214和216。最后，形成焊块122(图2G)。不需要图2H所示的后续金属蚀刻步骤。其原因在于金展现适合用于丝焊的压焊性能。因此，保持金的最上层。然而，要注意，金熔焊欠佳，因为熔焊操作中金滤入焊料。本发明的此实施例中，3金属层为金-镍-粘着金属(Al或TiW)，熔焊操作中金滤入焊料时，焊料会遇到镍层。由于镍是可熔焊金属，焊块会可靠地附着在焊块焊区区域。因此，金-镍层的使用同时提供可压焊和可熔焊的层。
返回参考图1，可有各种附加细丝压焊区的应用。附加细丝压焊区可仅配置在其相应底细丝压焊区的上方。因而，细丝压焊区134位于细丝压焊区102A上方。底细丝压焊区102A不需要重新定位时，用此结构，倒装芯片结构中，出现另一种应用。可形成从上芯片到下芯片上细丝压焊区的连接，使信号输出到外引脚。因此，焊块126连到上芯片上重合的导电通路孔，借助线迹140提供对底芯片上细丝压焊区136的连接。又一种应用出现在高密度电路的高度复杂的用途中。可设想期望将底细丝压焊区102B转接到诸如焊区136的新位置。然而，由于电路的密度，不存在这种直接路由。不过，本发明提供一种布局，从而细丝压焊区102B经线迹144和焊块124在倒装芯片设计中转接到上芯片。上芯片将信号载送到焊块126，该焊块又经线迹146继续将其送到焊区136。从这些例子可看出设计再分布局的许多应用，仅受技术人员想像力的限制。本发明不依赖再分布金属化可能的特定模式，而在于能组合焊块和细丝压焊区提供半导体器件内和2个倒装连接芯片之间的连接性方面的附加灵活性，并且其方法形成再分布金属化，以首先顾及焊块和细丝压焊区。

Claims (13)

1.一种集成电路，其特征在于包含：
具有第1表面和配置在第1表面周围的第1组细丝压焊区的半导体芯片；
配置在第1表面上的金属化层，该金属化层具有多条导电再分布迹线，至少一些所述迹线具有与第1组细丝压焊区电相通的第1端；所述再分布迹线包含配置在第1表面上的底金属层、配置在底金属层上的中间金属层和配置在中间金属层上的上金属层；
按至少一些再分布线迹制作图案的第2组细丝压焊区；
配置在金属化层顶上的钝化层，该钝化层具有沿再分布线迹穿通到连接位置的第1开口和穿通到第2组细丝压焊区的第2开口；
沿再分布线迹通过第1开口配置到连接位置的多个焊块，其中焊块直接连到上金属层；
通过第2开口压焊到第2组细丝压焊区的多条压焊细丝，其中再分布线迹在第2细丝压焊区内蚀刻到底金属层，从而细丝直接连到底金属层。
2.如权利要求1所述的集成电路，其特征在于，所述底金属层是铝、钯和铂中的一种。
3.如权利要求1所述的集成电路，其特征在于，所述再分布线迹包含最底下的铝层、配置在铝层顶上的镍层和配置在镍层顶上的铜层；其中焊块直接连到铜层，暴露第2细丝压焊区的铝层，从而压焊细丝直接连到铝层。
4.如权利要求1所述的集成电路，其特征在于，所述再分布线迹包含多金属膜层，最顶上的第1层为金，第2层为镍，最底下的第3粘着金属层选自铝、钛和钛钨合金之一。
5.一种在具有配置在第1表面的第1组细丝压焊区的半导体器件中产生焊块区和第2组细丝压焊区的方法，其特征在于包含以下步骤：
在第1表面上淀积钝化层；
形成通过钝化层到达第1组细丝压焊区的通路孔；
在钝化层上淀积包含多层不同金属的金属层的覆盖层，从而提供通过通路孔到第1组细丝压焊区的电通道；
金属层上制作图案，形成再分布线迹和第2组细丝压焊区，至少有些再分布线迹具有借助通路孔到第1组细丝压焊区的电通道；
在金属层上淀积介电材料覆盖层；
形成通过该覆盖层到金属层的第1和第2开口，第1开口与再分布线迹重合，第2开口与第2组细丝压焊区重合；
通过第1开口在再分布线迹中形成焊块；
至少去除经所述第2开口暴露的金属层部分的最上层。
6.如权利要求5所述的方法，其特征在于，淀积金属的步骤是淀积多个不同金属层的步骤；形成焊块后，接着对通过第2开口暴露的金属层部分的至少最上层进行蚀刻。
7.如权利要求5所述的方法，其特征在于，所述金属层是3层叠置的金属层；淀积金属层的步骤包括在钝化层上淀积铝层，在铝层上淀积镍层，并且在镍层上淀积铜层；该步骤还包括从通过第2开口暴露的3层叠置金属层部分去除铜层和镍层。
8.如权利要求5所述的方法，其特征在于，所述金属层是3层叠层的金属层；金属层淀积步骤包含在钝化层上淀积钯或铂层，在钯或铂层上淀积镍层，并且在镍层上淀积铜层；该步骤还包含从通过第2开口暴露的3层叠置金属层部分去除铜层和镍层。
9.如权利要求5所述的方法，其特征在于，淀积金属层的步骤是在钝化层上淀积粘着金属层，在粘着金属层上淀积镍层，并且在镍层上淀积金层的步骤。
10.如权利要求9所述的方法，其特征在于，所述粘着层选自铝、钛和钛钨合金之一。
11.如权利要求5所述的方法，其特征在于，淀积金属层覆盖的步骤包括首先在钝化层上喷镀粘着金属层后，在粘着金属层上喷镀镍层，又在镍层上喷镀金层；形成焊块的步骤包含在金层涂敷焊料，从而金滤入焊料，并且焊料接触下面的镍；还包括向金属层压焊细丝的步骤，该压焊细丝的步骤是直接压焊到金层的步骤。
12.如权利要求11所述的方法，其特征在于，所述粘着金属是铝、钛和钛钨合金中的一种。
13.如权利要求5所述的方法，其特征在于，所述淀积金属层覆盖的步骤包括首先在绝缘层顶上喷镀铝、钯或铂的底金属层后，在底金属层上喷镀镍层，又在镍层上喷镀铜层；还包括向金属层压焊细丝的步骤，在该压焊细丝步骤前，从通过第2开口暴露的金属层去除铜层和镍层，从而把细丝压焊到通过第2开口暴露的底金属层部分。
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US6511901B1 (en) 2003-01-28
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US6762117B2 (en) 2004-07-13
KR100643065B1 (ko) 2006-11-10
CA2388926A1 (en) 2001-05-17
NO20022134D0 (no) 2002-05-03
CN1387681A (zh) 2002-12-25
TW477051B (en) 2002-02-21
US6577008B2 (en) 2003-06-10
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US20020025585A1 (en) 2002-02-28
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HK1049913B (zh) 2005-08-05
HK1049913A1 (en) 2003-05-30

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