CN1187037A - 半导体封装及其制造方法 - Google Patents

半导体封装及其制造方法 Download PDF

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CN1187037A
CN1187037A CN97115025A CN97115025A CN1187037A CN 1187037 A CN1187037 A CN 1187037A CN 97115025 A CN97115025 A CN 97115025A CN 97115025 A CN97115025 A CN 97115025A CN 1187037 A CN1187037 A CN 1187037A
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lead
semiconductor chip
semiconductor
wires
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CN1104741C (zh
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全东锡
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SK Hynix Inc
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LG Semicon Co Ltd
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Abstract

一种半导体封装包括基本为平板形的第一散热片和与第一散热片耦合的第二散热片。半导体芯片安装在第一散热片的内表面上,第三散热片固定于半导体芯片的中央部分上。多根内引线固定于半导体芯片的侧边,外引线从内引线延伸,并相对于内引线向外弯曲。导线连接内引线与半导体芯片。模制部件密封半导体芯片、内引线、部分外引线及导线。

Description

半导体封装及其制造方法
本发明涉及一种半导体封装，特别涉及一种具有散热片的半导体封装及其制造方法。尽管本发明广泛适用于各种半导体芯片，但尤其适用于大功率芯片。
图1是展示常规底部引线半导体封装的剖面图。参见图1，常规底部引线封装包括与印刷电路板(PCB)(未示出)电连接的多根底部引线2a，从每根底部引线2a向上弯曲的内引线2b，借助粘结材料3安装在每根底部引线2a上表面上的的半导体芯片1，电连接半导体芯片1的芯片焊盘(未示出)与内引线2b的导线4，及模制部件5。模制部件包封半导体芯片1、底部引线2a、内引线2b及导线4，但暴露出底部引线2a的下表面，以便能够安装到PCB上并与之连接。
然而，上述常规底部引线半导体封装有以下缺点，即，由于模制部件5的热传导率低，半导体芯片1产生的热不能有效地辐射到芯片外部。具体地，这种封装对于要求高热传导率的大功率芯片来说是不适用的。
因此，本发明的目的是提供一种半导体封装及其制造方法，基本上能够解决现有技术的局限和缺点造成的一个或多个问题。
本发明的目的是提供一种能增大热传导效率的改进的半导体封装。
本发明的其它特点和优点如以下的说明书所述，部分可从说明书中显现，或可以实施本发明获知。特别是书面说明和权利要求书及附图中指出的结构将会实现和获得本发明的目的和优点。
为了获得这些和其它优点，根据本发明的目的，正如所概述和具体说明的那样，本发明的半导体封装包括：平板形第一散热片；垂直于第一散热片的侧面并与之成一体的第二散热片；借助粘结材料安装在第一散热片上表面上的半导体芯片；借助粘结材料固定在半导体芯片上部中央部分的第三散热片；借助粘结材料固定于半导体芯片上表面两侧的多根内引线；由内引线向上弯曲的多根底部引线；连接内引线与芯片焊盘的导线；及模制部件，模制树脂填充由第一至第三散热片限定的部分形成该部件，该部件用于密封半导体芯片、内引线、底部引线、及导线，并使底部所述引线部分暴露于外。
按本发明的另一方案，一种半导体封装包括：第一散热片；与第一散热片耦合的第二散热片；安装在第一散热片表面上的半导体芯片；安装在半导体芯片上的多根引线；连接多根引线与半导体芯片的导线；及密封半导体芯片、多根引线及导线的模制部件。
按本发明的再一方案，一种制造半导体封装的方法包括以下步骤：形成第一散热片；形成与第一散热片耦合的第二散热片；把半导体芯片安装到第一散热片上；将多根引线安装在半导体芯片上；用导线连接引线与半导体芯片；及模制半导体芯片、引线及导线，构成封装。
按本发明的又一方案，一种半导体封装包括：第一散热片；与第一散热片耦合的第二散热片；安装在第一散热片表面上的半导体芯片；安装在半导体芯片上的多根引线；连接该多根引线与半导体芯片的多根导线；连接于半导体芯片上的第三散热片；及密封半导体芯片、多根引线及导线的模制部件。
应该明白，上述的概括说明和以下的详细说明皆是例证性和说明性的，旨在对所申请的发明作进一步地说明。
用于进一步理解发明的各附图与说明书结合，并构成说明书的一部分，它们展示了本发明的实施例，与说明书一起说明本发明的原理。
各附图中：
图1是展示常规底部引线半导体封装的剖面图；
图2是展示本发明实施例的底部引线半导体封装的剖面图；
图3是展示本发明底部引线半导体封装的底视图；
图4是图2中“A”部分的放大剖面图；
图5是展示安装于印刷电路板(PCB)上的本发明底部引线半导体封装的剖面图；及
图6A-6H是展示本发明的制造底部引线半导体封装的方法的剖面图。
下面结合示于附图中的实例对本发明的优选实施例作详细说明。
图2是展示本发明的底部引线半导体封装的剖面图。参见图2，在第一散热片(第一热沉)6的侧面部分垂直地形成第二散热片7。第二散热片可以附着在第一散热片6上，或可以与散热片6成为一体。第一和第二散热片6和7最好由具有高热传导率和良好机械强度的金属和陶瓷材料制备。半导体芯片1借助第一粘结材料3安装在第一散热片6上。第一粘结材料最好是由具有良好热传导率的材料制成。引线框2的内引线2b借助粘结材料固定到半导体芯片1的两侧，且第三散热片8借助第二粘结材料3a固定于半导体芯片1上表面的中央部分上。引线框2最好形成为使其底部引线2a从内引线2b向上弯曲，且最好由铜合金或镍合金制成。
与第一和第二散热片类似，第三散热片8最好也由具有高热传导率和良好机械强度的金属或陶瓷材料制成。另外，第三散热片8最好包括形成于第三散热片8的两侧边缘部分的凸缘11。突起部分11a从每个凸缘11延伸，如图4所示。具体地，突起部分11a形成为圆形或多边形，用以增强第三散热片8与模制部件5的粘结强度。内引线2b和半导体芯片的芯片焊盘(未示出)由导电材料制的导线4连接。第一至第三散热片6、7和8限定的部分中填充模制树脂，以密封半导体芯片1、内引线2b、底部引线2a和导线4。如图3所示，模制部件5形成，使底部引线2a部分外露。
如图3所示，底部引线2a可以电连接PCB(未示出)，且不包括底部引线2a在内的底部引线半导体封装的底部最好大多被第三散热片8所覆盖。
图5是展示本发明的底部引线半导体封装安装在PCB(印刷电路板)上的状况的剖面图。参见图5，只有底部引线2a借助于焊料9与PCB10连接。
图6A-6H是展示本发明的制造底部引线半导体封装的方法的剖面图。虽然这里运用了元件的“上”侧这一术语，但应该理解，该术语和其它术语只是对附图作的描绘。
图6A是展示第二散热片7垂直地与平板形第一散热片6的侧面边缘部分联接的步骤的剖面图。第一和第二散热片6和7最好形成为一体，且由具有高热传导率和机械强度的金属和陶瓷材料制成。图6B是展示在第一散热片6的上表面上均匀涂敷第一粘结材料3的步骤的剖面图。第一粘结材料3由具有良好热传导效率的材料制成。
图6C是展示利用第一粘结材料3在第一散热片6的上表面上固定半导体芯片1的步骤的剖面图。图6D是展示利用粘结材料在半导体芯片1的上表面两侧边上固定内引线2b的步骤的剖面图。引线框2从内引线2b向上弯曲，用以形成底部引线结构。
图6E中展示利用导线4连接内引线2b与半导体芯片1的芯片焊盘的步骤的剖面图。导线4由合适的导电材料制成。图6F是展示在半导体芯片1的上部中央部分上均匀涂敷第二粘结材料3a的步骤的剖面图。第二粘结部件3a由具有良好热传导率的材料制成。
图6G是展示利用第二粘结材料3a在半导体芯片1的上部中央部分固定第三散热片8的步骤的剖面图。第三散热片8由具有良好热传导率和机械强度的金属或陶瓷材料制成。图6H是展示用模制树脂填充由第一至第三散热片6、7、和8限定的部分、并使底部引线2a暴露于外的步骤的剖面图，该步骤用于密封半导体芯片1、内引线2b、底部引线2a和导线4，从而形成模制部件5。
如上所述，根据本发明的底部引线半导体封装旨在利用固定半导体芯片1上下表面及侧面的散热片6、7、和8更有效地辐射半导体芯片1产生的热。所以，本发明的底部引线半导体封装特别适用于需要高热传导效率以散发芯片工作期间产生的大量热量的大功率芯片。另外，通过由第三散热片8的凸缘11形成例如圆形或多边形的突起部分11a可以增强模制部件5的粘结强度。
显然，对于本领域的普通技术人员来说，在不脱离本发明精神或范围的情况下，可以做出各种改型和变化。但是，本发明将覆盖这些会落入所附权利要求书及其延伸的范围内的改型和变化。

Claims (20)

1.一种半导体封装，该封装包括：
第一散热片；
与第一散热片耦合的第二散热片；
安装在第一散热片表面上的半导体芯片；
安装在半导体芯片上的多根引线；
连接多根引线与半导体芯片的导线；及
密封半导体芯片、多根引线及导线的模制部件。
2.根据权利要求1的半导体封装，其特征在于，第二散热片与第一散热片成为一体。
3.根据权利要求1的半导体封装，还包括安装在半导体芯片上的第三散热片。
4.根据权利要求3的半导体封装，其特征在于，第三散热片包括至少在其一个边缘部分的凸缘。
5.根据权利要求4的半导体封装，其特征在于，凸缘包括从凸缘延伸的突起部分。
6.根据权利要求1的半导体封装，其特征在于，所述引线部分暴露于外侧。
7.根据权利要求1的半导体封装，其特征在于，多根引线利用凸点与半导体芯片连接。
8.根据权利要求1的半导体封装，其特征在于，第一、第二散热片为金属或陶瓷材料。
9.根据权利要求1的半导体封装，其特征在于，第二散热片与半导体芯片的上表面连接。
10.一种制造半导体封装的方法，该方法包括以下步骤：
形成第一散热片；
形成与第一散热片耦合的第二散热片；
把半导体芯片安装到第一散热片上；
把多根引线安装在半导体芯片上；
用导线连接引线与半导体芯片；及
模制半导体芯片、引线及导线，构成封装。
11.根据权利要求10的方法，其特征在于，第二散热片与第一散热片形成为一体。
12.根据权利要求10的方法，还包括在半导体芯片上安装第三散热片的步骤。
13.根据权利要求12的方法，其特征在于，第三散热片包括在其至少一个边缘部分的凸缘。
14.根据权利要求13的方法，其特征在于，凸缘包括从凸缘延伸的突起部分。
15.根据权利要求10的方法，其特征在于，所述引线部分暴露于外侧。
16.一种半导体封装包括：
第一散热片；
与第一散热片耦合的第二散热片；
安装在第一散热片上表面上的半导体芯片；
安装在半导体芯片上的多根引线；
连接多根引线与半导体芯片的多根导线；
安装在半导体芯片上的第三散热片；及
密封半导体芯片、多根引线及导线的模制部件。
17.根据权利要求16的半导体封装，其特征在于，第二散热片与第一散热片成为一体。
18.根据权利要求16的半导体封装，其特征在于，第三散热片包括在其至少一个边缘部分的凸缘。
19.根据权利要求18的半导体封装，其特征在于，凸缘包括从凸缘延伸的突起部分。
20.根据权利要求16的半导体封装，其特征在于，所述引线部分暴露于外侧。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1319138C (zh) * 2002-02-07 2007-05-30 自由度半导体公司 封装的半导体器件的形成方法
CN101009272B (zh) * 2006-01-25 2010-10-13 三星电子株式会社 用于存储器模块的冷却设备
CN103794575A (zh) * 2014-01-24 2014-05-14 清华大学 一种封装结构及封装方法
CN109411425A (zh) * 2018-11-14 2019-03-01 深圳市瓦智能科技有限公司 半导体元件

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3837215B2 (ja) * 1997-10-09 2006-10-25 三菱電機株式会社 個別半導体装置およびその製造方法
JPH11214638A (ja) 1998-01-29 1999-08-06 Mitsubishi Electric Corp 半導体記憶装置
US6190945B1 (en) * 1998-05-21 2001-02-20 Micron Technology, Inc. Integrated heat sink
KR100266693B1 (ko) 1998-05-30 2000-09-15 김영환 적층가능한 비지에이 반도체 칩 패키지 및 그 제조방법
US6420779B1 (en) 1999-09-14 2002-07-16 St Assembly Test Services Ltd. Leadframe based chip scale package and method of producing the same
KR100565962B1 (ko) * 2000-01-06 2006-03-30 삼성전자주식회사 플립 칩 기술을 이용한 피지에이 패키지
CN1184684C (zh) * 2000-10-05 2005-01-12 三洋电机株式会社 半导体装置和半导体模块
JP4003860B2 (ja) * 2000-11-02 2007-11-07 富士通株式会社 マイクロアクチュエータ及びその製造方法
JP2003014819A (ja) * 2001-07-03 2003-01-15 Matsushita Electric Ind Co Ltd 半導体配線基板，半導体デバイス，半導体デバイスのテスト方法及びその実装方法
US6633005B2 (en) 2001-10-22 2003-10-14 Micro Mobio Corporation Multilayer RF amplifier module
DE10201781B4 (de) * 2002-01-17 2007-06-06 Infineon Technologies Ag Hochfrequenz-Leistungsbauteil und Hochfrequenz-Leistungsmodul sowie Verfahren zur Herstellung derselben
US6737298B2 (en) * 2002-01-23 2004-05-18 St Assembly Test Services Ltd Heat spreader anchoring & grounding method & thermally enhanced PBGA package using the same
EP1504276B1 (en) 2002-05-03 2012-08-08 Donnelly Corporation Object detection system for vehicle
TW563232B (en) * 2002-08-23 2003-11-21 Via Tech Inc Chip scale package and method of fabricating the same
KR20050016087A (ko) * 2003-08-06 2005-02-21 로무 가부시키가이샤 반도체장치
SE529673C2 (sv) * 2004-09-20 2007-10-16 Danaher Motion Stockholm Ab Kretsarrangemang för kylning av ytmonterade halvledare
US20060060980A1 (en) * 2004-09-22 2006-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Ic package having ground ic chip and method of manufacturing same
DE102006000724A1 (de) * 2006-01-03 2007-07-12 Infineon Technologies Ag Halbleiterbauteil mit Durchgangskontakten und mit Kühlkörper sowie Verfahren zur Herstellung des Halbleiterbauteils
KR100947454B1 (ko) * 2006-12-19 2010-03-11 서울반도체 주식회사 다단 구조의 열전달 슬러그 및 이를 채용한 발광 다이오드패키지
US7800208B2 (en) 2007-10-26 2010-09-21 Infineon Technologies Ag Device with a plurality of semiconductor chips
JP4995764B2 (ja) * 2008-04-25 2012-08-08 力成科技股▲分▼有限公司 リード支持型半導体パッケージ
JP2012175070A (ja) * 2011-02-24 2012-09-10 Panasonic Corp 半導体パッケージ
TWI508238B (zh) * 2012-12-17 2015-11-11 Princo Corp 晶片散熱系統
CN111385917B (zh) * 2018-12-29 2022-07-15 中微半导体设备(上海)股份有限公司 一种用于组装esc的多平面多路可调节温度的加热器
KR20210017271A (ko) 2019-08-07 2021-02-17 삼성전기주식회사 반도체 패키지

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02306639A (ja) * 1989-05-22 1990-12-20 Toshiba Corp 半導体装置の樹脂封入方法
US5175612A (en) * 1989-12-19 1992-12-29 Lsi Logic Corporation Heat sink for semiconductor device assembly
JPH04192552A (ja) * 1990-11-27 1992-07-10 Nec Corp 半導体素子用パッケージ
US5293301A (en) * 1990-11-30 1994-03-08 Shinko Electric Industries Co., Ltd. Semiconductor device and lead frame used therein
US5552636A (en) * 1993-06-01 1996-09-03 Motorola, Inc. Discrete transitor assembly
JP2974552B2 (ja) * 1993-06-14 1999-11-10 株式会社東芝 半導体装置
US5362679A (en) * 1993-07-26 1994-11-08 Vlsi Packaging Corporation Plastic package with solder grid array
DE69330249T2 (de) * 1993-10-29 2001-12-06 St Microelectronics Srl Leistungsverpackung mit hoher Zuverlässigkeit für eine elektronische Halbleiterschaltung
JP3073644B2 (ja) * 1993-12-28 2000-08-07 株式会社東芝 半導体装置
CA2140311A1 (en) * 1994-01-14 1995-07-15 Joseph P. Mennucci Multilayer laminate product and process
JPH0846098A (ja) * 1994-07-22 1996-02-16 Internatl Business Mach Corp <Ibm> 直接的熱伝導路を形成する装置および方法
WO1996027903A1 (en) * 1995-03-06 1996-09-12 National Semiconductor Corporation Heat sink for integrated circuit packages
US5805427A (en) * 1996-02-14 1998-09-08 Olin Corporation Ball grid array electronic package standoff design

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1319138C (zh) * 2002-02-07 2007-05-30 自由度半导体公司 封装的半导体器件的形成方法
CN101150098B (zh) * 2002-02-07 2011-11-23 飞思卡尔半导体公司 半导体器件
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CN108615711A (zh) * 2014-01-24 2018-10-02 清华大学 一种基于模板的封装结构及封装方法
CN109411425A (zh) * 2018-11-14 2019-03-01 深圳市瓦智能科技有限公司 半导体元件

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