CN1168537A - 具有高输入/输出连接的半导体集成电路器件 - Google Patents

具有高输入/输出连接的半导体集成电路器件 Download PDF

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CN1168537A
CN1168537A CN96123430A CN96123430A CN1168537A CN 1168537 A CN1168537 A CN 1168537A CN 96123430 A CN96123430 A CN 96123430A CN 96123430 A CN96123430 A CN 96123430A CN 1168537 A CN1168537 A CN 1168537A
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electrode pressure
semiconductor chip
inner lead
pressure welding
district
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姜帝凤
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority claimed from KR1019960021244A external-priority patent/KR980006195A/ko
Priority claimed from KR1019960055751A external-priority patent/KR100210712B1/ko
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN1168537A publication Critical patent/CN1168537A/zh
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Abstract

一种需要高I/O连接的IC器件，其中许多电极压焊区以矩形形式排列用于方形表面装配式封装，拐角电极压焊区移向半导体芯片内部用于减小拐角键合线距离，或者拐角内部引线弯曲并进一步延伸向芯片使拐角键合线的跨度长度较短，从而使得在导线键合和模塑工序过程中避免导线摆动和拐角键合线的短路并且能够提高键合线的可靠性。

Description

具有高输入/输出连接的半导体集成电路器件
本发明涉及一种半导体集成电路器件。更详细地说，本发明涉及一种半导体芯片的电极键合压焊区的排列以及一种在需要高输入和输出连接的集成电路器件中用于增强键合线可靠性的引线框的内部引线的结构。
半导体芯片必须具有连接部分，例如电极压焊区(也称作键合压焊区)，用于与外界(例如引线框引线)进行电互连。为了进行电连接，广泛应用导线键合技术，芯片电极压焊区和引线框内部引线通过诸如金或铝金属键合线进行连接。
在导线键合设计中重要参数包括导线直径，电极压焊区间距，引线间距以及电极压焊区在芯片有源表面的排列。键合线的直径影响最大导线跨度(即通过导线实现电连接的电极压焊区和内部引线之间的距离)。例如，如果导线具有1.25mil(＝0.00125英寸或者32微米)的直径，导线跨度的长度通常应用100-D规则，即125mil是通常设计的最大导线跨度。最大可能的导线跨度也依赖于电极压焊区和引线框底座(或管芯底座)的边缘之间的距离。在决定最大导线跨度中一个最主要的因素是键合线是否能够承受模材流动(moldingflow)的压力以防止相邻导线的电短路。在目前的半导体组装产业中，最大的导线跨度约从180至200mil。
压焊区间距和引线间距基本上由集成电路器件中所需的到外部器件的电通路的多少决定。因此电极压焊区以及内部引线的数量越多，压焊区间距和引线间距就越小。压焊区间距也依赖于诸如电极压焊区尺寸、在电极压焊区上形成的导线焊球的尺寸、导线键合头的细柱(capillary)和相邻导线焊球之间的距离以及细柱(capillary)和相邻键合线之间的距离的因素。目前，压焊区间距的最小尺寸大约从80至100微米，而由引线框制作工艺极限决定的最小引线间距大约从180至200微米。
图1A示出了适用于需要高I/O的半导体芯片的封装的常规引线框的局部平面图，而图1B是图1A的放大视图。半导体芯片10安装到引线框的管芯底座12，而管芯底座通过4个拐角拉杆14连接到引线框的侧杆17。因此拉杆用于支撑管芯底座。引线框的内部引线16通过键合线18电连接到芯片10的电极压焊区20。内部引线16沿径向向内扩展到芯片10的四周，而这种类型的引线框被应用于方形表面装配封装中，例如QFP(方形扁平封装)，PLCC(有引线塑料芯片载体)，CLCC(有引线陶瓷芯片载体)和类似结构。这些方形封装能够提供超过200个I/O连接，并且具有形如鸥翼或J形的外部引线用于表面装配，这种装配允许有比管脚直插装配方法更高的装配密度。内部引线16具有内部引线端线13，它不是平行于芯片10的边缘，而是在中心边缘区域处略微向外倾斜。通过这样做，比起平行内部引线结构，能够制成更多的内部引线。
应用于方形封装的半导体芯片具有许多电极压焊区20，以矩形的形式沿芯片有源表面的周围排列，以容纳非常高的I/O连接。然而，在方形表面装配封装中，用于连接形成于芯片拐角的电极压焊区和邻近拉杆的内部引线的拐角导线不可避免地具有非常长的导线跨度。例如，如果芯片10的尺寸是4675μm2，压焊区间距是常数75μm并使用208个管脚(或引线数目)的引线框，其中引线间距‘1p’是200μm，在中心区域导线跨度S2为182mil而拐角导线跨度S1为218mil。在导线键合工艺或模塑工艺过程中，这种长拐角导线会造成相邻拐角导线之间的电短路。特别是相邻导线之间的距离在接近电极压焊区时变得较小。在上述例子中，d1是97.6μm而d2是136.5μm，其中d1在距电极压焊区四分之一S1的位置处而d2在距电极压焊区二分之一S1的位置处。
位于门G两侧的拐角引线，由于熔化的塑料通过该门G注入并垂直流过长拐角线，经受相当大的力，因此导线摆动和邻近导线短路都易于发生。
为了避免这个问题，如图2所示现有工艺中半导体芯片10具有扩大的拐角电极压焊区22的压焊区间距。采用这种结构，例如在上面举例中的芯片和引线框采用120μm的拐角压焊区间距，导线距离d3和d4分别增加到119.6μm和151.2μm。然而，拐角压焊区间距的增加导致了较大的芯片尺寸。这是与现代半导体工艺小型化趋势背道而驰的，因此是不可取的。
作为现有工艺的另一个例子，美国专利号5,466,968公开了一种引线框，其内部引线以如图1所示的典型排列为准转90度排列。具有这种内部引线的结构，引线在接近引线框的拉杆处逐渐靠近IC芯片，这就允许拉杆附近的拐角引线缩短。
另一方面，随着IC器件的集成度越来越高，在IC器件中所需的输入和输出连接数量显著增加。特别是用于逻辑和微处理器器件的I/O连接数量继续以正比于IC芯片上的门的数目的速度增加。因此，半导体工业需要克服如上所述的与长拐角导线有关的问题和不足。
本发明的一个目的就是提高在需要高输入和输出连接的IC器件中键合线的可靠性。
本发明的另一个目的就是避免相邻键合线，特别是位于需要高IO的半导体芯片的拐角区域的相邻键合线之间的电学短路失效。
本发明的再一个目的是提供更多的IO用于IC器件。
根据本发明的一个方面，将排列在芯片拐角区域的半导体芯片的电极压焊区从正常的余下电极压焊区的矩形布局移向中心芯片区域。除此之外，通过使拐角电极压焊区具有更大的压焊区间距，使得相邻键合线的距离能够更短。
根据本发明的另一个方面，提供具有高引线数目的方形引线框，其中使待被导线键合到半导体芯片的拐角电极压焊区的引线框的拐角内部引线弯曲并进一步伸向芯片。采用这种结构，就可能使拐角键合线变短，并因此保持键合线的稳定性以抵抗导线摆动和电短路作用。
已经叙述了本发明的一些目的和优点，其它的目的和优点将可通过以下的详细描述和参照附图获得更全面的理解：
图1A是安装有常规半导体芯片的引线框的平面图；
图1B是图1A的‘A’部分的详细视图；
图2是引线框和安装在其上的常规半导体芯片的局部平面图，该芯片上具有较大压焊区间距的拐角电极压焊区；
图3A是根据本发明的实施方案的引线框和具有向半导体芯片内部移动的拐角电极压焊区的半导体芯片的局部平面图；
图3B是图3A的‘B’部分的详细视图；
图4A是根据本发明的引线框和其中拐角电极压焊区移向芯片内部并具有较大压焊区间距的半导体芯片的局部平面图；
图4B是图4A的‘C’部分的详细视图；
图5是半导体芯片的视图；
图6A是根据本发明的安装半导体芯片的引线框的视图，其中拐角内部引线弯曲并且更伸向半导体芯片；以及
图6B是图6A的‘D’部分的详细视图。
图3A和3B示出了引线框和具有许多根据本发明排列的电极压焊区的半导体芯片。在芯片110的有源表面上电极压焊区120具有矩形布局。这种电极压焊区的排列在为容纳更多I/O连接的方形表面装配式封装中是很典型的。半导体芯片110安装到管芯底座112并由其支撑，而管芯底座112则通过拉杆114连接到引线框的侧杆区域(未示出)。拉杆114位于管芯底座112的四个拐角。内部引线框引线116沿径向向内伸向芯片110的四边。内部引线116通过键合线118电连接到电极压焊区120。
内部引线端线113不是平行于相对应的半导体芯片的边，而是中心的内部引线更远离芯片伸向芯片外部方向，这样可允许提供更多的引线。当然，当内部引线端线设计得更远离芯片的边，则拉杆114之间的内部引线116的数目能够增加。但不幸的是，间距的扩展受到最大导线跨度设计原则的限制。
根据本发明的实施方案，拐角电极压焊区按照如图3B所示的以固定距离‘ps’移向芯片的内部来排列。这些移动的拐角电极压焊区具有如其他电极压焊区一样的压焊区间距‘pd’。
采用这种电极压焊区的排列，就可增大芯片拐角区域的相邻键合线之间的距离，而不增加芯片尺寸。例如，当这个实施方案应用于上面半导体芯片和引线框示例时(即，芯片尺寸为4675μm2，引线框为208个管脚，其中引线间距‘1p’为200μm)在拐角压焊区移动‘ps’是固定的70μm的范围的情况下，导线距离d1和d2为130.8μm和160.2μm，分别比现有工艺情况增加了33.2μm和23.7μm。其结果是，相邻导线的电短路较少，并因此获得较稳定的键合线。
图4A和4B示出了本发明的另一个实施方案。在这个实施方案中电极压焊区的间距是不均匀的，拐角压焊区具有较大的压焊区间距。采用这种实施方式，就可以通过比图3的实施方案较少地移动拐角压焊区来增大所需的拐角导线距离(d1和d2)。例如，如果压焊区只移动35μm的‘ps’而拐角压焊区间距‘pd1’是120μm，比其它压焊区75μm的间距‘pd2’大。则导线距离d1和d2分别变为141.7μm和166.2μm，分别增大了44.1μm和29.7μm。
在拐角压焊区所移向的半导体芯片的内部，如图5所示有源电路图形形成于中心区域130，同时用于诸如为有源电路提供正和负电源电压信号和有源电路内部电互连的控制电路形成于周边区域140 。由于有源器件尺寸缩小技术比电极压焊区间距减小技术发展更快，所以它可以提供足够的空间用于移动拐角电极压焊区。为了在封装装配获得高的产量，必须在芯片布局开始之前决定诸如电极压焊区间距和拐角压焊区间距的移动的设计规则。在决定规则时，所要考虑的是，例如，用于拐角压焊区移动的空间和拐角压焊区间距能够增加的极限。在这样的决定的基础上，选择图3实施方案或图4实施方案。
图6A和6B还示出了本发明的另一个实施方案。半导体芯片210的电极压焊区220具有固定的压焊区间距，而拐角压焊区220a沿其它电极压焊区220所排列的直线排列。内部引线沿径向向内延伸，但是与管芯底座保持一定空间。引线具有沿直线230排列的各自的端部，直线230比与相应的管芯底座的边平行的直线略微倾斜。另一方面，邻近拉杆214的拐角内部引线216a弯曲并相对于由其它内部引线216界定的内部引线端部直线230进一步延伸朝向半导体芯片拐角区域。邻近拉杆214处延伸量增加。最好是使拐角内部引线216a延伸部分平行以便使拐角键合线之间的距离保持固定。
当这种引线框结构应用于上面所举芯片和引线框示例时，中心内部引线216b的导线跨度S2为不变的182mil，但是拐角内部引线216a的导线跨度S1很显著地减少到160mil，与现有工艺结构相比能够节约58mil的导线跨度长度。这种较短的导线键合能够减少模塑过程中导线摆动的可能性，也能够降低两个拐角导线的电短路或导线与不合适的引线的短路的可能性。因此，键合线的可靠性提高了。
而且由于拐角导线跨度变得较短，内部引线的端线能够更进一步远离芯片的边，在相同最大拐角键合线跨度情况下能够允许提供更多的内部引线。因此能够提供更多的I/O连接。
下面的表格说明了本发明相对现有工艺结构的改进。在现有工艺1中使用了具有4675μm2尺寸的半导体芯片，具有固定压焊区间距75μm的电极压焊区，以及具有208个引线数目和200μm内部引线间距的引线框。相对于这个现有工艺1，在表格中示出了导线距离的增加程度。在现有工艺2中，如图2所示两个拐角电极压焊区具有较大的120μm压焊区间距。而现有工艺3使拐角压焊区间距为150μm。实施方案1到4给出了应用本发明的实验结果。在实施方案1和实施方案2中，如图3所示，两个拐角电极压焊区分别向半导体芯片内部移35μm和70μm，同时保持压焊区间距为固定值。另一方面，如图4所示，实施方案3是拐角电极压焊区向内移35μm并具有较大的120μm压焊区间距。最后，实施方案4是拐角内部引线如图6所示进一步延伸向芯片的情况。
<表格>
S1(mil) S2(mil) d2(μm) d1(μm)     增加量
d2(μm) d1(μm)
现有工艺1     218     182     137     98     -     -
现有工艺2      -      -     151     120     14     22
现有工艺3      -      -     163     138     26     40
实施方案1      -      -     152     118     15     20
实施方案2      -      -     160     131     23     33
实施方案3      -      -     166     142     29     44
实施方案4     160     182      -      -      -     -
如前面所说明的，本发明使得在需要高I/O的IC的器件中拐角键合线的导线间距增大和拐角键合线的导线跨度减小成为可能。本发明能够提高键合线的可靠性，并且为IC器件提供更多的输入输出连接。
本发明已参照所说明的实施方案进行了描述，但是这个描述不能被认为只局限于此。对于本领域的专业人员参考本叙述作出的各种不同的变型和所说明的实施方案的结合以及其它本发明的实施方案都是显而易见的。因此附加的权利要求包括任何这样的变型或实施方案。

Claims (10)

1.一种半导体集成电路器件，包括：
(A)具有有源表面的半导体芯片，其上形成有许多电极压焊区，所述的有源表面具有四个边和在相邻所述边之间界定的四个拐角，许多电极压焊区沿有源表面的四个边按矩形形状排列；
(B)引线框，具有管芯底座，用于支撑半导体芯片和电连接到半导体芯片的内部引线，所述的内部引线径向延伸向有源表面的四个边同时离开半导体芯片一定距离；并且
(C)在许多电极压焊区和内部引线之间连接有许多键合线，其中位于拐角处的拐角电极压焊区移向半导体芯片内部。
2.如权利要求1所述的半导体集成电路器件，其中所述的拐角电极压焊区具有与其它电极压焊区一样的压焊区间距。
3.如权利要求1所述的半导体集成电路器件，其中所述的拐角电极压焊区具有比其它电极压焊区较大的压焊区间距。
4.如权利要求1所述的半导体集成电路器件，其中所述的内部引线具有内部引线端线，其在拐角处比相应的有源表面的边的平行线向内倾斜。
5.一种半导体集成电路器件，包括：
(A)具有有源表面的半导体芯片，其上形成有许多电极压焊区，所述有源表面具有四个边和在相邻的边之间界定的四个拐角，许多电极压焊区沿有源表面的四个边按照矩形形状排列；
(B)引线框，具有管芯底座，用于支撑半导体芯片和电连接到半导体芯片的内部引线，所述内部引线径向延伸向有源表面的四个边并与半导体芯片离开一定距离；并且
(C)在许多电极压焊区和内部引线之间连接有许多键合线，其中连接到拐角处的电极压焊区的拐角内部引线进一步延伸向半导体芯片。
6.如权利要求5所述的半导体集成电路器件，其中引线框还包括四个连接到管芯底座拐角的四个拉杆，并且拐角内部引线平行于拉杆。
7.如权利要求5所述的半导体集成电路器件，其中连接在拐角内部引线和拐角电极压焊区之间的拐角键合线比连接在内部引线和放置在有源表面的边的中心区域的电极压焊区之间的中心连接线具有较短的长度。
8.如权利要求5所述的半导体集成电路器件，其中内部引线具有的内部引线端线在拐角处比相应的有源表面的边的平行线向内倾斜。
9.一种引线框，包括管芯底座，用于支撑具有许多电极压焊区的半导体芯片和电互连到许多电极压焊区的内部引线，所述的许多电极压焊区沿半导体芯片的四个边按照矩形形状排列，位于半导体芯片拐角区域的内部引线进一步延伸向半导体芯片。
10.如权利要求9所述的引线框，其中半导体芯片的电极压焊区和引线框的内部引线通过金属键合线进行电连接。
CN96123430A 1996-06-13 1996-12-30 具有高输入/输出连接的半导体集成电路器件 Pending CN1168537A (zh)

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KR1019960021244A KR980006195A (ko) 1996-06-13 1996-06-13 와이어 본딩의 안정성을 위한 반도체 칩 패키지의 리드 프레임과 그를 이용한 반도체 칩 패키지
KR21244/96 1996-06-13
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KR1019960055751A KR100210712B1 (ko) 1996-11-20 1996-11-20 와이어 본딩 안정성을 위한 전극 패드 배열을 갖는 반도체 칩을 이용한 반도체 집적회로 소자

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DE19652395A1 (de) 1997-12-18
TW368737B (en) 1999-09-01

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