CN1104045C - 利用偏离连线和支撑块空腔制造双面连线集成电路封装 - Google Patents
利用偏离连线和支撑块空腔制造双面连线集成电路封装 Download PDFInfo
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Abstract
本文提出了一种方法,利用该方法可以在一个引线框(20)上制造双面集成电路封装,该引线框具有基座(25)和与该基座对应的引脚(40、42)。引线框放在支撑块(118、122)上,集成电路芯片(50、90)被放在基座的两个表面上,该支撑块具有空腔(120、320)以放置集成电路芯片并且用来支撑引脚,而且该支撑块还为已尼形成的连线(56、58、94、96)提供针脚接合的空间。然后在每个组件的周围形成单步塑模(66),该组件包括双面集成电路芯片、基座和连线。
Description
发明背景
1发明领域:
本发明涉及集成电路芯片封装,更具体地,本发明涉及利用偏离连线(offset wire bonds)和支撑块制造双面连线集成电路封装,支持块中含有用于针脚接合法支撑的空腔。
2技术背景:
集成电路芯片通常采用塑模封装。当前典型的塑模封装构造在金属引线框上。每一个引线框块具有一个基座用来放置集成电路芯片。每一个引线框块还有一组引线,为相应的集成电路芯片和外部电路提供电学联接。上述塑模封装为集成电路芯片提供了保护,并且通过从封装延伸的引脚为集成电路芯片提供了电学联接。
当前塑模封装中通常每个封装只有一块集成电路芯片。集成电路芯片通常放置在基座的一面。集成电路芯片放置在基座的上表面或下表面。通常,附着于基座的集成电路芯片引线连接到相应的引脚。基座、集成电路芯片和引线通过塑胶注入与模制化合物封装在一起、或倒扣封装(glob top)。
集成电路芯片的封装的实用性可以通过将两片或更多片的集成电路芯片封装在一起而得到改进。例如,一块封装内可以有两片存储器芯片,这样,存储系统的密度就可以增加一倍,而不会增加含有此存储器芯片的印刷电路板的面积。再如,一块封装内的一面有一个微控制器或处理器,另一面则是一块存储器芯片。
目前,双面集成电路封装的生产主要采用自动载带焊接(TAB)技术 但是,TAB技术需要在集成电路芯片上形成镀金压点结构。镀金压点结构的形成将要增加双面集成电路封装的费用。并且,TAB技术的制造工艺需要成套的压焊设备。压焊设备提高了双面集成电路封装的制造成本。并且,目前的TAB技术还不如常规的引线连接技术稳定。
发明综述
本发明的目的之一是提供一种双面集成电路封装,其中有两片或更多的集成电路芯片。芯片有相似或不同的尺寸,有相似或不同的功能。
本发明的另一个目的是提供一种双面集成电路封装的制造方法,对每一个封装只包括单步塑料封装。
本发明的另一个目的是提供一种双面集成电路封装,其在引线框相反的两面采用了偏离针脚接合连接。
本发明的另一个目的是提供一种双面集成电路封装的制造方法,其采用了具有空腔的支撑块,该空腔在贴片和引线连接过程中容纳集成电路芯片。
本发明的另一个目的是提供一种双面集成电路封装的制造方法,该方法采用了支撑块和夹具,该支撑块和夹具具有空腔,在形成新的针脚接合时,为已经形成的针脚接合提供空间。
本发明的另一个目的是提供一种双面集成电路封装的制造方法,该方法减少了连接过程中的振动,因而防止和或减少了缺陷,如压焊点的弧坑和芯片破裂。
本发明的另一个目的是提高生产设备的效率和利用率,使每台设备发挥更多的功能和提高最终封装的可靠性。
本发明的上述目的和其他目的是通过提供一种双面集成电路封装的制造方法实现的。在实施例之一中,引线框包含至少一个基座和与该基座相对应的引脚。一块集成电路芯片放在基座的第一面并且粘附在第一面上。然后,一块集成电路芯片放在基座的第二面上,而引线框放在支撑块上,该支撑块与芯片表面没有接触,并且该支撑块具有空腔可以容纳第二面的集成电路芯片,并且第二块集成电路芯片粘附在第二面上。引线框在支撑块和夹具的固定下,第二面的集成电路芯片被连接到相应的引脚上。支撑块和夹具具有空腔以容纳第一面集成电路芯片和支撑引脚的末端。这样第一面的集成电路芯片被连接到相应的引脚上,基座放在支撑块上,该支撑块与芯片表面没有接触,并且该支撑块具有空腔可以容纳第二面的集成电路芯片和相应的引线,每条引脚都被支撑并且为每条引脚在引线框的第二面上的针脚接合留出了空间。连接的次序可以相反,即先连接第二面,再连接第一面。然后在组件的周围形成单步塑模,该组件包括第一块和第二块集成电路芯片、基座和连线。
另一实施例是先制备引线框,然后将第一块集成电路芯片放在基座的第一面。引线框用平面支撑块或带有空腔的支撑块支撑,第一块集成电路芯片被连接到相应引线的第一面上。引线框在支撑块和夹具的固定下,第二块集成电路芯片被放在基座的第二面。支撑块和夹具具有空腔以容纳第一面集成电路芯片和相应的引线。第二面的集成电路芯片被连接到相应引线的第二面上。此时,引线框被带有空腔的支撑块所支撑。然后在组件的周围形成塑模,其组件包括第一块和第二块集成电路芯片、基座和连线。引线连接的次序可以相反。
本发明的其它目的、特点和优点从随后的附图和发明详述中将变得很明显。
附图简述
本发明通过实施例说明,并不局限于附图,其中相似的标号说明相似的部件,其中:
图1是在一实施例中引线框一面的顶视图,引线框包括了一组基座,基座为集成电路芯片提供了安装平台;
图2是引线框上基座和相应引脚的顶视图,该引脚为安装在基座上的集成电路芯片提供了电连接;
图3是在一实施例中一系列工艺步骤的流程图,采用该工艺可以在引线框每一个基座上制造双面集成电路芯片塑模封装;
图4是引线框沿4-4面的剖面图,图中显示了利用粘附层将集成电路芯片粘到基座的第一面上;
图5a是引线框沿4-4面的剖面图,图中显示了支撑块的空腔,该空腔在第二面的集成电路芯片粘附时为第一面的集成电路芯片提供了空间;
图5b是引线沿4-4面的剖面图,图中显示了支撑块的空腔和夹具,在第二面的集成电路芯片连接时该空腔为第一面的集成电路芯片提供了空间;
图6是引线框沿6-6面的剖面图,图中显示了第二面的集成电路芯片到引脚的连接;
图7是引线框沿6-6面的剖面图,图中显示了第一面的集成电路芯片到引脚的连接;
图8是双面集成电路组件的底视图,该组件包括第一面的集成电路芯片、第二面的集成电路芯片和基座上相应的连线,图中示出了支撑块的空腔,其中每个集成电路芯片仅示出了一端的连线;
图9是单步注模工艺中双面集成电路芯片组件的剖面图,组件位于引线框上,引线框放在模具中;
图10是双面集成电路芯片塑模封装的剖面图,其中包括位于基座相反两面的第一面集成电路芯片和第二面集成电路芯片,芯片被塑模包围;
图11是在另一实施例中一系列工艺步骤的流程图,采用该工艺可以在引线框的每一个基座上制造双面集成电路芯片塑模封装;
图12是引线框沿6-6面的剖面图,图中显示了引线框放置在平面支撑块上。
详细描述
图1是引线框20一面的顶视图。引线框20的一面即下文中的第一面,引线框20相反的一面即下文中的第二面。引线框上有一系列基座22-29。基座22-29为集成电路芯片提供了安装平台。引线框上还有与每个基座22-29相对应的引线。
在引线框的形成过程中,基座22-29和相对应的引脚可以通过刻蚀在引线框20上形成。或者,基座22-29和相对应的引脚可以通过冲压在引线框20上形成。
引线框20优选地由钢或铜制成。之所以选择钢和铜是因为它们和硅与塑料的交互特性(interactive properties)。对于一实施例,引线框20的典型厚度为5密耳(mil)。
在芯片封装工艺中,采用一组对准孔如对准孔21以精确定位引线框20。
图2是引线框20的顶视图。图中显示了基座24和25以及相应的引脚。引脚组28和引脚组30对应于基座24。引脚组28和引脚组30为安装于基座24上的集成电路芯片提供了电学连接。引脚组40和引脚组42为安装于基座25上的集成电路芯片提供了电学连接。
在引线框电镀的过程中,一层银淀积到基座22-29的两面。电镀银点也淀积到与基座22-29相对应的引脚顶端的两面。
例如,电镀银点淀积到引脚28的区域32中和引脚30的区域34中。与此相似,电镀银点淀积到引脚40的区域33中和引脚42的区域35中。
可以先在引线框20的第一面镀银,然后在引线框20的第二面镀银。或者,可以在引线框20的第一面和第二面同时镀银。
在基座22-29上镀银可以提高集成电路芯片和基座22-29之间的热传导和电传导特性。在引脚顶端镀银可以在引线框20上进行金丝连接。或者,在基座22-29上的镀银工艺以省略,以提高引线框和塑模的粘附性。
引线框镀银工艺可以简化,在基座22-29上镀银或在引脚上镀银。如果不需要沿引脚向基座22-29镀银,则基座需要另外的掩模。
作为镀银工艺的替代,可以在基座22-29上和相应引脚的顶端镀金或镀钯。
一实施例是,延伸引线框上的每个基座22-29,并且在每个基座22-29上形成定位孔。这些定位孔在贴片和引线连接到引线框20的工艺中为基座22-29提供了支撑结构。例如,在基座25上有一组定位孔300-305。这样,在基座25上制备双面集成电路封装过程中,在贴片和引线连接工艺中定位孔300-305可以容纳支撑块上相应的定位针,以提供支撑结构。
定位孔300-305可以在引线连接过程中减小基座25的振动,并且防止在封装大集成电路芯片的过程中可能出现的连接破裂。定位孔300-305和定位针对于封装某些集成电路芯片不是必需的。
图3是一实施例的流程图,图中包括在引线框20上的进行的一系列工艺步骤200-214。采用工艺步骤200-214在引线框20上进行,以在每个基座22-29上形成双面连接的芯片封装。
在工艺步骤200中,集成电路芯片被贴到引线框20的每个基座22-29的第一面。一实施例是采用粘附树脂2100用载带工艺进行贴片,如有需要再进行适当的处理。
图4是在工艺步骤200中,引线框20沿基座25的4-4面的剖面图。利用粘附层52,集成电路芯片50粘附到基座25的第一面。在工艺步骤200中,支撑块118支撑着基座25。另一实施例是,支撑块118有一组定位针(未画出),在贴片过程200中,定位针插入定位孔300-305中。
从基座25的边86到边87测量的基座25的尺寸大于普通集成电路芯片的容积。扩展的基座25容纳定位孔300-305的位置。一实施例是,集成电路芯片50的一边84和基座25的一边86之间的距离以及集成电路芯片50的另一边85和基座25的另一边87之间的距离在10到30密耳之间。
基座25超过集成电路芯片边界84和85的部分决定于包含基座25的最后的塑封的总尺寸。在边86与边87之间的基座25的延伸部分是有限的,在塑模注入工艺210中,应允许塑胶在引线框20的第一面和第二面之间流动为宜。
一实施例是采用贴片机将集成电路芯片贴到基座22-29上。首先贴片机在芯片上涂上粘附剂以形成粘附层52,然后将集成电路芯片50放在引线框20上并校准芯片。贴片机在将芯片放置到基座25之前应从硅片上拿取芯片。
一实施例是粘附层52采用环氧树脂,环氧树脂经过180摄氏度的高温处理以牢固支撑集成电路芯片50。
在工艺步骤202中,集成电路芯片被贴到引线框20第二面的每一个基座22-29上。图5a是工艺步骤202中引线框20沿4-4面的剖面图。在工艺步骤202中,支撑块118的空腔120提供了容纳集成电路芯片50的空间,引线框20在其末端的一面被真空吸住。如图,集成电路芯片90通过粘附层92放置于基座25的第二面。
在工艺步骤204中,贴于引线框20第一面的芯片被引线连接到引线框20相应的引脚上。引脚40包括对应于基座25的引脚44。引脚42包括对应于基座25的引脚46。
图5b是在工艺步骤204中,引线框20沿4-4面的剖面图。一对夹具110和112用来夹住基座25。在另一实施例中,夹具110包括一组定位孔以容纳支撑块118上的定位针(未画出)。夹具110和112的夹持力使基座25更加稳定,并可减少在集成电路芯片90的引线连接过程中基座25的振动。
在另一实施例中,支撑块118的定位针(未画出)与夹具110和112一起使用,以夹紧位于定位针之间的基座25。基座25被夹紧以进单步减少振动,并防止在引线连接集成电路芯片90的过程中,在已形成的集成电路芯片50的压点上出现焊坑。
并且,在集成电路芯片90的引线连接过程中,与集成电路芯片50粘在一起的粘附层52可以保证结构更稳定。
图6是引线框20沿6-6面的剖面图,图中示出了集成电路芯片50被引线连接到引线框20上的引脚44和46上。引线56连接集成电路芯片50上的压点54和引脚44。引线56通过引脚44的镀银区33连接到引脚44上。与此相似,引线58通过镀银区35连接压点55和引脚46。
在工艺步骤204中,引脚40包括引脚44由支撑块118支撑。另外,引脚42包括引脚46由支撑块108支撑,在连接工艺中,支撑块118还提供热量。在引线连接工艺中,高温可以减少所需外力和能量,这样就可以减少引线连接工艺中的振动。夹具110和112在第一面的引线连接过程中增加了稳定性并减少振动。
支撑块118的表面130和132之间的距离为支撑块118的空腔120的宽度,其宽度应以在引线接合中靠近引脚44和46的末端提供支撑为宜。表面130的位置在靠近引脚44的末端80提供支撑,表面132的位置在靠近引脚46的末端82提供支撑。表面130和132之间的空腔120的宽度提供了支撑,使得可以分别靠近末端80和82提供到引脚44和46的针脚式接合。
在工艺步骤206中,位于引线框20第二面的集成电路芯片被连接到引线框20相应的引脚上。图7显示了集成电路芯片90被连线接合到引脚44和46。引线94通过引脚44的镀银区75连接集成电路芯片90上的压点93和引脚44。与此相似,引线96通过引脚44的镀银区76连接集成电路芯片90上的压点95和引脚46。
在工艺步骤206中,支撑块122支撑着引脚44和46。夹具110和112在第二面引线连接过程中增强了稳定性并减少振动。在支撑块112中有一个空腔320,可以容纳集成电路芯片50和引脚56和58以及引脚上的相应接合点。支撑块122的表面100和102之间为空腔320的宽度,可容纳镀银区33和35的针脚式接合。表面100和表面102的位置提供了引线94和引线96与镀银区75和76的针脚接合的支撑。
与引线56和引线58的针脚接合相比,引线94和引线96的针脚接合从引脚44和引脚46的末端80和82向外形成。表面100和102之间的空腔320的尺寸可以容纳引线56和引线58的针脚接合,又可以在下面支撑引线94和引线96的针脚接合。
另外,由空腔320决定的支撑尺寸可以通过调整支撑块118的表面130和表面132的位置得到。这时,支撑块118包括可调节的部分,它支撑引线框20的引脚,又可以调节空腔120的大小。
图8是双面集成电路组件的顶视图,该组件包括集成电路芯片50和90和在工艺过程206中在基座25上形成的相应的引线。图中示出了定位孔300-305和引脚40和42,以及轮廓106,该轮廓指示包括支撑块122的表面100和102、由支撑块形成的空腔320的垂直面。同时图中也示出了包括引线56在内的、引脚40和集成电路芯片50之间的引线,以及包括写引线(write bond)96在内的、引脚42和集成电路芯片90之间的引线。
在工艺步骤210中,通过向模具中注入塑胶形成塑模,以便将集成电路芯片50和90封到一个塑模封装中。图9是在工艺步骤210中通过注入塑胶位于引线框20上的集成电路组件的剖面图。模具包括顶模100和底模102。顶模100和底模102为每一个位于引线框20上的集成电路组件提供一个空腔。例如,顶模100和底模102为集成电路组件提供了空腔60,该组件包括位于基座25上的集成电路芯片50和90。
塑胶注入器(未画出)向模具空腔注入塑胶,在位于引线框20上的每一个集成电路组件的周围形成塑模。基座22-29上的孔包括定位孔300-305使塑胶可以在基座25上的集成电路芯片周围更好地流动。在塑模注入工艺之后,塑模需要必要的处理。
在工艺过程212中,在引线框20的引脚上电镀一层铅锡合金。在工艺过程214中,在引线框20上的每个集成电路组件的引脚最后成型。图10是双面集成电路封装130的剖面图。双面集成电路封装130包括位于基座25相反的两面并被塑模66包围的集成电路芯片50和90。
图11是另一实施例的工艺步骤230-242,该工艺步骤用于在每个基座22-29上制造双面集成电路封装。在工艺步骤230中,集成电路芯片被贴到每个基座22-29的第一面上。在工艺步骤232中,被贴到基座22-29第一面上的集成电路芯片被引线接合到引线框20的相应引脚上。在工艺步骤230和232中,引线框20被支撑块支撑,与上述工艺步骤200-204一样,该支撑块具有空腔。
另外,在工艺步骤230和232中,引线框20可以用平板支撑块支撑。图12是引线框20沿基座25的A面的剖面图,图中示出了在工艺步骤230和232中,引线框20放置于平板支撑块350上。集成电路芯片50通过粘附层52贴在基座25的第一面。
引线56通过引脚44的镀银区33连接集成电路芯片50的压点5 4和引脚44。引线58通过镀银区35连接压点55和引脚46。平板支撑块350使得可以靠近末端80和82形成到引脚44和46的针脚接合。
在工艺过程234中,集成电路芯片被贴到引线框20的每个基座22-29的第二面上。在工艺过程234中,引线框20放在支撑块118上,与前述工艺过程202一样,该支撑块带有空腔120以容纳集成电路芯片50。
在工艺过程236中,引线框20的第二面上的集成电路芯片被引线接合到引线框20上相应的引脚上。在工艺过程236中,引脚44和46为支撑块122所支撑,与前述工艺过程206一样,该支撑块带有空腔320以容纳集成电路芯片50、引脚56和58以及相应的针脚接合。
在工艺过程238中,与前述工艺过程210一样,向模具中注入塑胶形成塑模将集成电路芯片50和90封入一个塑模封装中。在工艺过程240中。在引线框20的引脚上电镀一层铅锡合金。在工艺过程242中,在引线框20上的每个集成电路组件的引脚最后成型。
如上所述,根据所讲述的实施例详细介绍了本发明。但是,在不背离随后的权利要求中的本发明的实质和范围的前提下,可以进行许多改进和变动。说明和附图仅是用于解释,而不是限制意义。
Claims (28)
1.一种制造双面集成电路封装的方法,包括以下步骤:
制备一个引线框,该引线框至少有一个基座和一组与该基座相对应的引脚,该引线框有第一面和第二面;
在基座的第一面上放置第一面集成电路芯片;
将第二面集成电路芯片放置在基座的第二面上,利用带有空腔的支撑块支撑引线框,空腔可以容纳第一面集成电路芯片;
将第一面集成电路芯片引线接合到第一面相应引脚上,利用带有空腔的支撑块支撑引线框,支撑块支撑引脚的末端,空腔可以容纳第二面集成电路芯片;
将第二面集成电路芯片引线接合到第二面相应引脚上,利用带有空腔的支撑块支撑引线框,支撑块支撑着引脚,并提供空间容纳引线框第一面的连线的针脚接合,空腔可以容纳第一面集成电路芯片和相应的连线。
2.根据权利要求1的方法,其中引线框至少有一个基座和一组与该基座相对应的引脚,制备该引线框的步骤包括制备具有基座和一组与该基座相对应引脚的引线框,其中,在基座上用于放置第一面和第二面集成电路芯片的区域外围具有扩展区域。
3.根据权利要求2的方法,其中利用带有空腔的支撑块支撑引线框,将第一面集成电路芯片引线连接到相应引脚的第一面上,支撑块支撑在每个引脚的末端,空腔可以容纳第二面集成电路芯片,该连接工艺包括以下步骤:
提供带有空腔的支撑块,该带有空腔的支撑块支撑在引脚的末端;空腔可以容纳第二面集成电路芯片,并用真空力支持引线框;
将引线框放在具有空腔的支撑块上,空腔可以容纳第二面集成电路芯片;
利用至少一个夹具将引线框夹紧在支撑块上;
将第一面集成电路芯片引线接合到第一面相应引脚上。
4.根据权利要求3的方法,其中利用至少一个夹具将引线框夹紧在支撑块上的步骤还包括拉伸基座以减少在写接合(write bonding)过程中的振动的步骤。
5.根据权利要求2的方法,其中利用带有空腔的支撑块支撑引线框,将第二面集成电路芯片引线接合到第二面相应引线上,支撑块支撑着引脚,并提供容纳引线框第一面的每个连线的针脚接合的空间,空腔可以容纳第一面集成电路芯片和相应的连线,该工艺包括步骤:
提供带有空腔的支撑块,空腔可以容纳第一面集成电路芯片和相应的连线,支撑块支撑着每个引脚,并提供容纳引线框第一面的针脚接合的空间;
将引线框放在带有空腔的支撑块上,空腔可以容纳第二面集成电路芯片和相应的连线;
利用至少一个夹具将引线框夹紧在支撑块上;
将第二面集成电路芯片引线接合到第二面相应引线上。
6.根据权利要求5的方法,其中利用至少一个夹具将引线框夹紧在支撑块上的步骤还包括拉伸基座以减少在引线接合过程中的振动的步骤。
7.根据权利要求1的方法,制备至少有一个基座和一组与该基座相对应引脚的引线框的步骤,还包括在基座上形成一组定位孔的步骤,定位孔在基座的两面用于放置第一面和第二面集成电路芯片的区域的外围。
8.根据权利要求7的方法,其中将第一面集成电路芯片引线接合到第一面相应引脚上,利用带有空腔的支撑块支撑引线框,支撑块支撑在引脚的末端,空腔可以容纳第二面集成电路芯片,该连接工艺包括以下步骤:
提供带有空腔的支撑块,支撑块支撑在引脚的末端,空腔可以容纳第二面集成电路芯片,并且支撑块还有与基座上的定位孔相对应的定位针;
将引线框放在具有空腔的支撑块上,空腔可以容纳第二面集成电路芯片,定位针插入定位孔;
利用至少一个夹具将引线框夹紧在支撑块上,夹具带有定位孔以容纳定位针;
将第一面集成电路芯片引线接合到第一面相应引脚上。
9.根据权利要求8的方法,其中,在利用至少一个夹具将引线框夹紧在支撑块上的步骤中,夹具带有定位孔以容纳定位针,还包括拉伸位于定位针之间的基座以减少写连接(write bonding)过程中的振动的步骤。
10.根据权利要求7所述的方法,其中,将第二面集成电路芯片引线接合到第二面相应引脚上,利用带有空腔的支撑块支撑引线框,空腔可以容纳第一面集成电路芯片和相应的连线,并支持每个引脚,且提供容纳引线框的第一面上的引线针脚接合的空间,该工艺包括步骤:
提供带有空腔的支撑块,支撑块支撑着引脚并提供容纳引线框第一面上的引线针脚接合的空间,空腔可以容纳第二面集成电路芯片和相应的引线,并且支撑块还有与基座上的定位孔相对应的定位针;
将引线框放在具有空腔的支撑块上,空腔可以容纳第二面集成电路芯片和相应的引线,定位针插入定位孔;
利用至少一个夹具将引线框夹紧在支撑块上,夹具带有定位孔以容纳定位针;
将第二面集成电路芯片引线接合到第二面相应引脚上。
11.根据权利要求10的方法,其中,在利用至少一个夹具将引线框夹紧在支撑块上的步骤中,夹具带有定位孔以容纳定位针,还包括拉伸位于定位针之间的基座以减少引线接合过程中的振动的步骤。
12.一种制备双面集成电路芯片封装的方法,包括以下步骤:
制备一个引线框,该引线框至少有一个基座和一组与该基座相对应的引脚,该引线框有第一面和第二面;
在基座的第一面上放置第一面集成电路芯片;
利用第一个支撑块支撑引线框,将第一面集成电路芯片连接到第一面相应引脚上;
将第二面集成电路芯片放置在基座的第二面上,利用带有空腔的支撑块支撑引线框,空腔可以容纳第一面集成电路芯片和相应的引线,支撑块支撑着引脚并提供容纳引线框第一面上的引线的针脚接合的空间;
将第二面集成电路芯片引线接合到第二面相应引脚上,利用带有空腔的支撑块支撑引线框,支撑块支撑着引脚并提供容纳引线框第一面上的引线的针脚接合的空间,空腔可以容纳第一面集成电路芯片和相应的连线。
13.根据权利要求12的方法,其中在基座的第一面上放置第一面集成电路芯片的步骤包括利用第一个支撑块支撑引线框的步骤。
14.根据权利要求12的方法,其中,将第一面集成电路芯片引线接合到第一面相应引脚利用第一个支撑块支撑引线框的步骤,包括以下步骤:利用第一个支撑块支撑引线框,将第一面集成电路芯片引线接合到第一面相应引线,该支撑块具有空腔并且支撑着引脚。
15.根据权利要求12的方法,其中,将第一面集成电路芯片引线接合到第一面相应引脚利用第一个支撑块支撑引线框的步骤包括利用第一个支撑块支撑引线框,将第一面集成电路芯片引线接合到第一面相应引脚的步骤,该支撑块为平板支撑块并且支撑着基座和相应的引脚。
16.根据权利要求12的方法,其中,制备至少有一个基座和一组与该基座相对应引脚的引线框的步骤包括以下步骤:制备具有基座和一组与该基座相对应引脚的引线框,其中,在基座的两面用于放置第一面和第二面集成电路芯片的区域的外围有扩展区域。
17.根据权利要求16的方法,其中,将第一面集成电路芯片引线接合到第一面相应引脚上,并利用第一个支撑块支撑引线框的步骤包括以下步骤:
提供带有空腔的第一个支撑块,支撑块支撑在引脚的末端;
将引线框放在具有空腔的支撑块上,支撑块支撑在引脚的末端;
利用至少一个夹具将引线框夹紧在支撑块上;
将第一面集成电路芯片引线接合到第一面相应引线上。
18.根据权利要求17的方法,其中,在利用至少一个夹具将引线框夹紧在支撑块上的步骤还包括拉伸基座以减少引线接合过程中的振动的步骤。
19.根据权利要求16的方法,其中,将第二面集成电路芯片引线接合到相应引线的第二面上并利用带有空腔的支撑块支撑引线框,支撑块支撑着引脚并提供容纳引线框第一面上的引线的针脚接合的空间,空腔可以容纳第一面集成电路芯片和相应的连线,该工艺包括步骤:
提供带有空腔的支撑块,空腔可以容纳第一面集成电路芯片和相应的引线,支撑块支撑着引脚并提供引线框第一面上的引线的针脚接合的空间;
将引线框放在具有空腔的支撑块上,空腔可以容纳第一面集成电路芯片和相应的连线;
利用至少一个夹具将引线框夹紧在支撑块上;
将第二面集成电路芯片引线接合到第二面相应引脚上。
20.根据权利要求19的方法,其中利用至少一个夹具将引线框夹紧在支撑块上的步骤还包括拉伸基座以减少引线接合过程中的振动的步骤。
21.根据权利要求12的方法,其中,制备至少有一个基座和一组与该基座相对引脚的引线框的步骤,还包括在基座上形成一组定位孔的步骤,定位孔在基座的两面用于放置第一面和第二面集成电路芯片的区域的外围。
22.根据权利要求21的方法,其中,利用第一个支撑块支撑引线框,将第一面集成电路芯片引线接合到第一面相应引脚上的步骤包括以下步骤:
提供带有空腔的支撑块,支撑块支撑在引脚的末端,并且支撑块还有与基座上的定位孔相对应的定位针;
将引线框放在具有空腔的支撑块上,支撑块支撑在引脚的末端,定位针插入定位孔;
利用至少一个夹具将引线框夹紧在支撑块上,夹具带有定位孔以容纳定位针;
将第一面集成电路芯片引线接合到第一面相应引脚上。
23.根据权利要求22的方法,其中,利用至少一个具有定位孔的夹具将引线框夹紧在支撑块上的步骤还包括拉伸位于定位针之间的基座以减少引线接合过程中的振动的步骤。
24.根据权利要求21的方法,其中,利用带有空腔的支撑块支撑引线框,将第二面集成电路芯片引线接合到第二面相应引脚上,支撑块支撑着引脚并提供容纳引线框第一面上的连线的针脚接合的空间,空腔可以容纳第一面集成电路芯片和相应的连线,该工艺包括步骤:
提供带有空腔的支撑块,支撑块支撑着引脚并提供容纳引线框第一面上的连线的针脚接合的空间,空腔可以容纳第一面集成电路芯片和相应的连线,并且支撑块还有与基座上的定位孔相对应的定位针;
将引线框放在具有空腔的支撑块上,定位针插入定位孔,空腔可以容纳第一面集成电路芯片和相应的连线;
利用至少一个夹具将引线框夹紧在支撑块上,夹具带有定位孔以容纳定位针;
将第二面集成电路芯片引线接合到第二面相应引脚上。
25.根据权利要求24的方法,其中,利用至少一个具有定位孔的夹具将引线框夹紧在支撑块上的步骤还包括拉伸位于定位针之间的基座以减少引线接合过程中的振动的步骤。
26.一种双面集成电路芯片封装,包括:
基座和一组与基座相对应的引脚,基座具有第一面和第二面;
放置于基座第一面的第一块集成电路芯片;
放置于基座第二面的第二块集成电路芯片;
在第一块集成电路芯片和第一面相应引脚之间至少有一条连线;
在第二块集成电路芯片和第二面相应引脚之间至少有一条连线,其中,第二块集成电路芯片和第二面相应引脚之间的连线与第一块集成电路芯片和第一面相应引脚的之间的连线相比,从引脚的末端向外偏离;
具有一个容纳第一块集成电路芯片的空腔的第一支撑块;和
具有一个容纳第二块集成电路芯片的空腔的第二支撑块。
27.根据权利要求26的双面集成电路芯片封装,其中,在基座的两面用于放置第一面和第二面集成电路芯片的区域的外围有扩展区域。
28.根据权利要求27的双面集成电路芯片封装,其中,在扩展区域有一组定位孔,定位孔位于基座的两面用于放置第一面和第二面集成电路芯片的区域的外围。
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-
1994
- 1994-06-28 US US08/267,878 patent/US5527740A/en not_active Expired - Lifetime
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1995
- 1995-03-15 US US08/404,534 patent/US5545922A/en not_active Expired - Lifetime
- 1995-06-21 WO PCT/US1995/007893 patent/WO1996000980A1/en active IP Right Grant
- 1995-06-21 KR KR1019960707475A patent/KR100255550B1/ko not_active IP Right Cessation
- 1995-06-21 CN CN95193835A patent/CN1104045C/zh not_active Expired - Fee Related
- 1995-06-21 AU AU28698/95A patent/AU2869895A/en not_active Abandoned
- 1995-06-21 JP JP8503309A patent/JPH10506226A/ja active Pending
- 1995-06-21 MX MX9606556A patent/MX9606556A/es not_active IP Right Cessation
- 1995-06-21 EP EP95924032A patent/EP0774162B1/en not_active Expired - Lifetime
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WO1996000980A1 (en) | 1996-01-11 |
KR100255550B1 (ko) | 2000-05-01 |
EP0774162A4 (en) | 1997-07-30 |
AU2869895A (en) | 1996-01-25 |
CN1162366A (zh) | 1997-10-15 |
JPH10506226A (ja) | 1998-06-16 |
US5527740A (en) | 1996-06-18 |
EP0774162A1 (en) | 1997-05-21 |
MX9606556A (es) | 1997-03-29 |
EP0774162B1 (en) | 2006-11-02 |
US5545922A (en) | 1996-08-13 |
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