CN1102504A - 制造芯片隆起部的方法 - Google Patents

制造芯片隆起部的方法 Download PDF

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CN1102504A
CN1102504A CN94107870A CN94107870A CN1102504A CN 1102504 A CN1102504 A CN 1102504A CN 94107870 A CN94107870 A CN 94107870A CN 94107870 A CN94107870 A CN 94107870A CN 1102504 A CN1102504 A CN 1102504A
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barrier metal
protrusion
layer
metal
photoresist
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朴钟汉
朴春根
河善镐
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN1102504A publication Critical patent/CN1102504A/zh
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Abstract

一种制造芯片金属隆起部的方法，包括以下步 骤：在形成焊接区的衬底上形成阻挡层金属层；在阻 挡层金属层上形成光致抗蚀剂层以及在焊接区处开 窗口；通过对窗口区电镀形成芯片隆起部；用该隆起 部作为掩模选择性地去除光致抗蚀剂层；用残留的光 致抗蚀剂层作为掩模腐蚀阻挡层金属层的预定区域； 以及通过去除残留的光致抗蚀剂层在该焊接区上形 成芯片隆起部，从而得到高质量的芯片隆起部并在降 低生产成本的同时简化制造工艺。

Description

本发明涉及制造芯片隆起部的一种方法，更具体地说，涉及制造芯片隆起部的一种简化的方法，该方法在隆起部形成后从一个预先确定的区域去除阻挡层金属时，视需要可任选一种腐蚀方法。
随着半导体制造技术的进步，半导体器件的封装密度越来越高。同时，在不断改进电子元件的速度和性能的情况下对它们的小型化提出的要求已使芯片尺寸要更大但封装外壳的尺寸要更小和更薄，当然这二方面的要求是互相矛盾的。
在一个满足上述要求的制造半导体器件的常规方法的例子中，在半导体芯片上的金属焊接区上首先形成一个隆起部。然后，通过一种热压法将引线框的支撑引线固定在该隆起部上从而得到一个组件。将二个这样的组件安放在上、下两侧，而将引线框安放在中间的位置，从而使支撑引线弯曲、成形，并连接到每个引线框上。这种连接应用环氧树脂来完成。
本发明涉及一种制造芯片隆起部的方法，即一种为实现上述封装工艺而在芯片上制造隆起部的方法。
可应用金、铜或焊料来作为制造隆起部的材料，其中金由于它的高导电率是最好的材料。近来为了降低成本已采用了铜隆起部和焊料隆起部。对于焊料隆起部，可应用电镀、蒸发，或在焊料浴锅中进行浸蘸处理的工艺方法。
已提出了几种制造具有一种凹槽形状的底部的蘑菇型芯片隆起部的常规方法。在图1、图3和图4中分别例示了三种这样的方法。在这些方法中，图1的方法应用得最广，以下将通过参照图2A至2E对该方法进行详细的描述。
参照图2A至2E，为了制造隆起部，将金属层5（例如阻挡层金属）淀积在由硅层1、硅氧化层2、铝层3和保护层4组成的衬底的表面上（图2A）。通过应用光致抗蚀剂由光刻工艺形成镀层图形6。通过电镀的工艺方法，并以阻挡层金属作为一个电极在该金属层上的图形内形成隆起部（图2B）。在除去不需要的那部分光致抗蚀剂之后（图2C），再一次涂敷光致抗蚀剂以形成腐蚀阻挡层金属的图形（图2D）。此时，形成抗蚀剂图形以使抗蚀剂将隆起部和最接近的周围区域覆盖住。然后，通过腐蚀去除暴露出的阻挡层金属。在去除抗蚀剂图形后，就完成了芯片隆起部的制造（图2E）。但因阻挡层金属与隆起部之间的粘附性较弱，故要进行在200-300℃范围内的热处理。该热处理最好在完成电镀工艺后进行，它将有助于阻止粘附不牢的隆起部在随后的工艺过程中与金属层脱离。
但在按照上述掩模工艺制造芯片隆起部时，阻挡层金属是利用隆起部来进行腐蚀的，故得不到高分辨率的图形。此外，在图1描述的工序中，由于腐蚀阻挡层金属的光刻工艺是在制造隆起部之后进行的，因此在隆起部周围的抗蚀剂就变得比较厚。由于这层比较厚的抗蚀剂，因此在曝光剂量及其显影过程中会引起各种工艺缺陷，这些缺陷将会导致相邻的隆起部之间发生短路的潜在可能性。
图3和图4的热处理方法与上述热处理方法几乎是相同的。
图3中描述的工艺过程一直到电镀期间去除不需要的抗蚀剂这一步工艺为止都与图1所描述的工艺相同。在形成隆起部和在电镀期间去除抗蚀剂之后，通过不用光刻技术而用隆起部作为掩模进行腐蚀来去除阻挡层金属。这就是说，在按照图1的工艺形成隆起部之后，阻挡层金属的去除不是用其后形成的抗蚀剂图形作为掩模来进行，而是用隆起部作为掩模来进行的。
按照图4描述的工艺，首先将阻挡层金属淀积在保护层表面上，之后在其上形成光致抗蚀剂图形。然后，按照光刻工艺通过腐蚀将阻挡层金属的上层（即第一层）的预先确定的部分除去。其后，用剩下的第一阻挡层金属作为电镀的一个电极形成隆起部。应用阻挡层金属的第一层的图形作为腐蚀的掩模对阻挡层金属的第二层进行腐蚀。这时，如果第一层和第二层的阻挡层金属选择得合适，可防止一种金属的腐蚀液对另一种金属的侵蚀。例如，Ti-Pd或Ti-Cu的阻挡层金属的组合可得到好的结果。但对Cr-Cu的阻挡层金属层，铜可能被铬的腐蚀液腐蚀。为了解决这个问题，可用厚的铜层或在铜层上形成第三金属层（如一薄层金）。
由于在图4描述的工艺中形成隆起部时只有第一层阻挡层金属用作电镀的一个电极，因此在晶片的中央和边缘部分之间很容易引起隆起部高度的变化。由于第一阻挡层金属是由电阻率相对高些的材料（Ti，Cr等）形成的，故这个隆起部高度的变化就成为一个问题，尤其在大晶片的情况下更是如此。
在不用作为电导线的金属来制造芯片隆起部（如在图1至图4中描述的方法那样）的情况下，如用湿法腐蚀则在腐蚀阻挡层金属期间会发生隆起部的边缘腐蚀，如用干法腐蚀则会发生下层阻挡层金属的损坏。
在应用作为电导线的金属的场合，通过在图5A至5E中所描述的工艺来制造芯片隆起部。首先，形成光致抗蚀剂图形6（图5A），然后应用该图形作为掩模腐蚀阻挡层金属5（图5B），同时去除光致抗蚀剂。之后，覆盖用于电镀的导线8的金属，并应用第二个光致抗蚀剂图形6来制造隆起部7（图5C）。腐蚀作为电导线8的金属（图5D）以得到芯片隆起部（图5E）。
当应用上述的作为电导线的金属时，要增加许多不必要的工序，如淀积腐蚀用于电镀的电导线用的金属、去除阻挡层金属所进行的光刻等等，故导致了复杂的工艺过程。
本发明考虑了上述在芯片隆起部的制造工艺中产生的问题，其目的是提供一种制造高质量的芯片隆起部的方法，该方法既不形成作为电导线的金属，也不需要一个单独的用于腐蚀阻挡层金属的光刻工序。
本发明的目的通过在半导体芯片的焊接区上制造用于直接固定引线的芯片金属隆起部的方法来达到。本方法包括以下步骤：在形成焊接区的衬底上形成阻挡层金属层，在阻挡层金属层上形成光致抗蚀剂层并在焊接区上开窗口，通过电镀在开窗口的区域上形成芯片隆起部，应用隆起部作为掩模选择性地去除光致抗蚀剂层，应用残留的光致抗蚀剂层作为掩模腐蚀阻挡层金属层的预定区域，以及通过去除残留的光致抗蚀剂层在焊接区上形成芯片隆起部。
通过结合附图对较佳实施例进行详细描述，本发明的上述目的会变得更为明显。
图1是按照常规方法的一个实施例制造芯片隆起部的工艺流程图;
图2A至2E描述了按照图1的常规方法的实施例制造芯片隆起部的工艺;
图3是按照常规方法的另一个实施例制造芯片隆起部的工艺流程图;
图4是按照常规方法的又一个实施例制造芯片隆起部的工艺流程图;
图5A至5E描述了按照常规方法的另外一个实施例在应用电导线时制造芯片隆起部的工艺;
图6是按照本发明的一个实施例制造芯片隆起部的工艺流程图;
图7A至7E描述了按照图6的本发明的实施例制造芯片隆起部的工艺;
在本发明的方法中，阻挡层金属层是用在隆起部之下的、在芯片隆起部制造期间保留下来的光致抗蚀剂层作为掩模来进行腐蚀的。因此，按照本发明的方法，制造工艺得到简化，制造成本大幅度下降。
隆起部的厚度最好比阻挡层金属的厚度大数十倍，这样在腐蚀阻挡层金属期间不会因为腐蚀而引起隆起部的厚度的较大变动。
在隆起部之下的光致抗蚀剂的厚度最好在2至100微米的范围内。
选择性地保留光致抗蚀剂层的工艺可用隆起部作为掩模或用遮蔽该隆起部的掩模来完成，该工艺可通过湿法腐蚀、干法腐蚀、湿法显影、干法显影等等来实现。
至于隆起部的材料，可应用铜、焊料、金或其它连接金属（junction  metal）的沉积。
至于阻挡层金属，最好采用选自由Ti、TiW、TiWN、Ni、TiN、Pd、W、Cu、Cr、Au及其合金构成的一组材料中的至少一种。去除阻挡层金属的工艺也可应用湿法或干法腐蚀来进行。
阻挡层金属可由复合层形成。在这种情况下，对阻挡层金属层的腐蚀最好是以下述方式来进行。首先腐蚀上层的阻挡层金属层，然后去除在隆起部之下的光致抗蚀剂层并用此上层阻挡层金属作为掩模腐蚀下层的阻挡层金属。
把本发明中那样保留在隆起部下的光致抗蚀剂的步骤应用于下部开有凹槽的蘑菇型隆起部。至于制造在隆起部下的光致抗蚀剂层的材料，可应用正性或负性光致抗蚀剂。隆起部之下的光致抗蚀剂层的类型、厚度和长度可以通过调整蘑菇型隆起部的大小自由地在防止边缘腐蚀的范围内进行调整。
图6是按照本发明的一个实施例制造芯片隆起部的工艺流程图。图7A至7E描述了按照本实施例的工艺过程。以下将参照附图对本发明的一个实施例作详细说明。
首先，按照常规方法形成硅层1和硅氧化层2。通过光刻和腐蚀工艺在硅氧化层上形成铝的图形3。通过钝化形成保护层4，然后在部分铝的区域开出窗口。之后淀积和形成阻挡层金属5，并在其上形成光致抗蚀剂图形6（图7A）。通过电镀法形成蘑菇型隆起部7，并通过用隆起部作为掩模进行的曝光9和随后的显影（图7B），留下隆起部之下的光致抗蚀剂层10（图7C）。在利用隆起部7之下的光致抗蚀剂层10对阻挡层金属5进行湿法或干法腐蚀后（此时，也可应用隆起部的掩模遮蔽作用）（图7D），通过湿法或干法腐蚀去除光致抗蚀剂层10。按照本发明的实施例，用湿法或干法显影工艺（图7E）将产生芯片隆起部。
下文将详细描述较佳实施例。
实施例1
在硅片上形成4000
Figure 941078701_IMG2
厚的SiO2层，然后淀积铝，并通过光刻和腐蚀工艺形成图形。通过用Si3N4进行钝化处理形成保护层。然后在铝的区域上开出窗口，并用溅射工艺形成由2000
Figure 941078701_IMG3
厚的TiW层和1μm厚的Cu层组成的复合阻挡层金属。通过应用由TOK公司制造的PAR-900光致抗蚀剂形成5μm厚的光致抗蚀剂图形。之后应用该图形得到焊接区窗口，以获得蘑菇型的隆起部。从焊接区窗口处到铜的蘑菇型隆起部的端部的长度为几微米到几十微米。在制造隆起部后，在不用掩模的情况下，应用Perkin Elmer公司制造的一种对准器，以300mJ/cm2的能量对整个片子曝光，并进行显影。通过该工艺将隆起部之下的光致抗蚀剂选择性地保留下来。应用该光致抗蚀剂层作为掩模，用FeCl3对上层阻挡层金属（Cu）腐蚀3分钟，而用50℃的H2O2对下层阻挡层金属（TiW）腐蚀3.5分钟，这样来得到按本发明制造的芯片隆起部。
实施例2
在本实施例中，除了用Cr/Cu的组合作为阻挡层金属外，其余工序是按实施例1中描述的同样的方式来进行的。先腐蚀上层阻挡层金属（铜层），之后去除在隆起部之下的光致抗蚀剂层。应用上层阻挡层金属作为掩模来腐蚀下层阻挡层金属（铬层），从而得到本发明的芯片隆起部。
按照上述的本发明的方法，由于在隆起部之下的光致抗蚀剂层起到了掩模的作用，因此在对阻挡层金属进行湿法腐蚀期间不发生边缘腐蚀的问题。故通过湿法或干法腐蚀可得到高分辨率的图形。在应用用于电导线的金属的常规方法中，阻挡层金属是在电镀前进行腐蚀的。但按本发明，阻挡层金属是在电镀后进行腐蚀的。此外，可以省略一些不必要的工艺，例如，淀积为了腐蚀阻挡层金属而用作电导线的金属、光刻等。这样就简化了总的工艺过程。也就是说，达到了简化工艺和降低成本的目的。

Claims (6)

1、一种在半导体芯片的焊接区上制造用于直接固定引线的金属的芯片隆起部的方法，该方法包括以下步骤：
在形成所述焊接区的衬底上形成阻挡层金属层；
在所述阻挡层金属层上形成光致抗蚀剂层，并在焊接区处开窗口；
通过电镀该窗口区而形成芯片隆起部；
用所述隆起部作为掩模选择性地去除所述光致抗蚀剂层；
用残留的光致抗蚀剂层作为掩模腐蚀所述阻挡层金属层的预定区域；以及
通过去除所述残留的光致抗蚀剂层而在所述焊接区上形成芯片隆起部。
2、如权利要求1所述的方法，其中，所述隆起部的厚度比所述阻挡层金属的厚度大数十倍，以便在腐蚀阻挡层金属期间不会因为对隆起部的腐蚀而引起隆起部厚度的较大变动。
3、如权利要求1所述的方法，其中，所述光致抗蚀剂的厚度在2至100微米的范围内。
4、如权利要求1所述的方法，其中，选择性地去除所述光致抗蚀剂层的工艺是应用所述隆起部的掩模遮蔽作用来进行的。
5、如权利要求1所述的方法，其中，所述阻挡层金属由复合层组成。
6、如权利要求5所述的方法，其中，所述阻挡层金属层的腐蚀是通过首先腐蚀所述复合层的上层阻挡层金属、然后去除所述隆起部之下的光致抗蚀剂层，和用上层阻挡层金属作为掩模腐蚀下层阻挡层金属的方式来进行的。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1112722C (zh) * 1997-04-08 2003-06-25 索尼株式会社 半导体器件的制造方法

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6821821B2 (en) * 1996-04-18 2004-11-23 Tessera, Inc. Methods for manufacturing resistors using a sacrificial layer
US6001671A (en) * 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
US5620611A (en) * 1996-06-06 1997-04-15 International Business Machines Corporation Method to improve uniformity and reduce excess undercuts during chemical etching in the manufacture of solder pads
JPH09330934A (ja) * 1996-06-12 1997-12-22 Toshiba Corp 半導体装置及びその製造方法
FR2758015A1 (fr) * 1996-12-30 1998-07-03 Commissariat Energie Atomique Micro-champignons conducteurs et element de connexion electrique utilisant de tels micro-champignons
US6583444B2 (en) * 1997-02-18 2003-06-24 Tessera, Inc. Semiconductor packages having light-sensitive chips
US6117299A (en) * 1997-05-09 2000-09-12 Mcnc Methods of electroplating solder bumps of uniform height on integrated circuit substrates
KR100219806B1 (ko) 1997-05-27 1999-09-01 윤종용 반도체장치의 플립 칩 실장형 솔더 범프의 제조방법, 이에 따라 제조되는 솔더범프 및 그 분석방법
KR100244580B1 (ko) * 1997-06-24 2000-02-15 윤종용 금속 범프를 갖는 회로 기판의 제조 방법 및 그를 이용한 반도체 칩 패키지의 제조 방법
US6642136B1 (en) * 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
US6452271B2 (en) * 1998-07-31 2002-09-17 Micron Technology, Inc. Interconnect component for a semiconductor die including a ruthenium layer and a method for its fabrication
US6130141A (en) * 1998-10-14 2000-10-10 Lucent Technologies Inc. Flip chip metallization
US6936531B2 (en) 1998-12-21 2005-08-30 Megic Corporation Process of fabricating a chip structure
US8021976B2 (en) 2002-10-15 2011-09-20 Megica Corporation Method of wire bonding over active area of a semiconductor circuit
DE10017746B4 (de) * 2000-04-10 2005-10-13 Infineon Technologies Ag Verfahren zur Herstellung eines elektronischen Bauteils mit mikroskopisch kleinen Kontaktflächen
US6448171B1 (en) * 2000-05-05 2002-09-10 Aptos Corporation Microelectronic fabrication having formed therein terminal electrode structure providing enhanced passivation and enhanced bondability
US6293457B1 (en) * 2000-06-08 2001-09-25 International Business Machines Corporation Integrated method for etching of BLM titanium-tungsten alloys for CMOS devices with copper metallization
US6815324B2 (en) * 2001-02-15 2004-11-09 Megic Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
TWI313507B (en) 2002-10-25 2009-08-11 Megica Corporatio Method for assembling chips
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US8158508B2 (en) * 2001-03-05 2012-04-17 Megica Corporation Structure and manufacturing method of a chip scale package
US6869515B2 (en) 2001-03-30 2005-03-22 Uri Cohen Enhanced electrochemical deposition (ECD) filling of high aspect ratio openings
US7087510B2 (en) * 2001-05-04 2006-08-08 Tessera, Inc. Method of making bondable leads using positive photoresist and structures made therefrom
US7099293B2 (en) * 2002-05-01 2006-08-29 Stmicroelectronics, Inc. Buffer-less de-skewing for symbol combination in a CDMA demodulator
US7932603B2 (en) * 2001-12-13 2011-04-26 Megica Corporation Chip structure and process for forming the same
TWI245402B (en) 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
US6486054B1 (en) * 2002-01-28 2002-11-26 Taiwan Semiconductor Manufacturing Company Method to achieve robust solder bump height
KR100455387B1 (ko) * 2002-05-17 2004-11-06 삼성전자주식회사 반도체 칩의 범프의 제조방법과 이를 이용한 ｃｏｇ 패키지
US7547623B2 (en) * 2002-06-25 2009-06-16 Unitive International Limited Methods of forming lead free solder bumps
US7541275B2 (en) * 2004-04-21 2009-06-02 Texas Instruments Incorporated Method for manufacturing an interconnect
US8067837B2 (en) 2004-09-20 2011-11-29 Megica Corporation Metallization structure over passivation layer for IC chip
US8294279B2 (en) * 2005-01-25 2012-10-23 Megica Corporation Chip package with dam bar restricting flow of underfill
KR100790993B1 (ko) * 2006-07-04 2008-01-03 삼성전자주식회사 범프 구조체를 구비한 플립 칩 패키지 및 그 제조방법
TWI345816B (en) * 2007-08-28 2011-07-21 Advanced Semiconductor Eng Method for forming bumps on under bump metallurgy
US7713860B2 (en) * 2007-10-13 2010-05-11 Wan-Ling Yu Method of forming metallic bump on I/O pad
US8946891B1 (en) 2012-09-04 2015-02-03 Amkor Technology, Inc. Mushroom shaped bump on repassivation
US9491840B2 (en) 2013-09-13 2016-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Electrostatic discharge protection apparatus and process
JP6436531B2 (ja) * 2015-01-30 2018-12-12 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4293637A (en) * 1977-05-31 1981-10-06 Matsushita Electric Industrial Co., Ltd. Method of making metal electrode of semiconductor device
JPS58102542A (ja) * 1981-12-15 1983-06-18 Seiko Instr & Electronics Ltd バンプ電極の製造方法
JPS63305533A (ja) * 1987-06-05 1988-12-13 Nec Corp 半導体装置の製造方法
JPS6461934A (en) * 1987-09-02 1989-03-08 Nippon Denso Co Semiconductor device and manufacture thereof
JP2633586B2 (ja) * 1987-10-21 1997-07-23 株式会社東芝 バンプ構造を有する半導体装置
JP2664736B2 (ja) * 1988-08-30 1997-10-22 株式会社東芝 半導体装置用電極の形成方法
JPH02139934A (ja) * 1988-11-21 1990-05-29 Seiko Epson Corp 集積回路の製造方法
JP2874184B2 (ja) * 1989-05-19 1999-03-24 セイコーエプソン株式会社 半導体装置の製造方法
KR940010510B1 (ko) * 1988-11-21 1994-10-24 세이꼬 엡슨 가부시끼가이샤 반도체 장치 제조 방법
JP2748530B2 (ja) * 1989-04-13 1998-05-06 セイコーエプソン株式会社 半導体装置の製造方法
JPH0350734A (ja) * 1989-07-18 1991-03-05 Seiko Epson Corp 集積回路の製造方法
US5244833A (en) * 1989-07-26 1993-09-14 International Business Machines Corporation Method for manufacturing an integrated circuit chip bump electrode using a polymer layer and a photoresist layer
JP2936680B2 (ja) * 1990-09-12 1999-08-23 富士通株式会社 半導体装置の製造方法
JPH04130619A (ja) * 1990-09-20 1992-05-01 Mitsubishi Electric Corp 半導体装置の製造方法
JP2877168B2 (ja) * 1991-01-31 1999-03-31 富士電機株式会社 集積回路装置用バンプ電極の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1112722C (zh) * 1997-04-08 2003-06-25 索尼株式会社 半导体器件的制造方法

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DE4424962A1 (de) 1995-01-19
JPH0778826A (ja) 1995-03-20
FR2707797A1 (fr) 1995-01-20
KR950004464A (ko) 1995-02-18
US5418186A (en) 1995-05-23

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