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Publication numberCN1094610 C
Publication typeGrant
Application numberCN 95197430
Publication date20 Nov 2002
Filing date1 Dec 1995
Priority date2 Dec 1994
Also published asCN1173230A, CN1326033C, CN1492314A, CN1492315A, CN100412786C, CN101211255A, CN101211255B, CN102841776A, CN102841776B, EP0795153A1, EP0795153A4, EP1265132A2, EP1265132A3, US5802336, US5881275, US6119216, US6516406, US7966482, US8190867, US8495346, US8521994, US8601246, US8639914, US8793475, US8838946, US9015453, US9116687, US9141387, US9182983, US9223572, US9361100, US9389858, US20030115441, US20030131219, US20060236076, US20110093682, US20110219214, US20120198210, US20130117537, US20130117538, US20130117539, US20130117540, US20130117547, US20130124830, US20130124831, US20130124832, US20130124833, US20130124834, US20130124835, WO1996017291A1
Publication number95197430.0, CN 1094610 C, CN 1094610C, CN 95197430, CN-C-1094610, CN1094610 C, CN1094610C, CN95197430, CN95197430.0
InventorsA皮莱格, Y雅列, M米陶尔, LM门纳梅尔, B艾坦
Applicant英特尔公司
Export CitationBiBTeX, EndNote, RefMan
External Links: SIPO, Espacenet
MIcroprocessor with compression operation and unpacking operatino of composite operands
CN 1094610 C
Abstract  translated from Chinese
一个处理器包括用于存储第一压缩数据的第一寄存器(209),解码器(202)和功能单元(203)。 A processor includes a first register for storing a first compressed data (209), the decoder (202) and functional unit (203). 解码器有一个控制信号输入(207),用以接收第一控制信号和第二控制信号。 A decoder having a control signal input (207) for receiving a first control signal and second control signals. 第一控制信号用以指示压缩操作,而第二控制信号用以指示拆开操作。 A first control signal for indicating the compression operation, and the second control signal to indicate the open operation. 功能单元连接到解码器(202)和寄存器(209)上。 Functional unit is connected to a decoder (202) and register (209). 功能单元除执行移动操作外还使用第一压缩数据执行压缩操作和拆开操作。 In addition to the functional unit to perform the move operation also uses the first compression data compression is done and open operation.
Claims(13)  translated from Chinese
1.一个处理器,包括: 1. A processor, comprising:
用于存放分别包括第一组的多个数据元素和第二组的多个数据元素的第一压缩数据和第二压缩数据的一个存储区域,其中在所述第一组的多个数据元素中的每一个数据元素相应于在所述第二组的多个数据元素中的一个不同的数据元素; Respectively include a memory for storing the compressed data area of the first plurality of data elements of the first group and a second plurality of data elements and a second set of compressed data, wherein the plurality of data elements of the first group Each data element corresponding to a different data elements in the plurality of data elements in the second group;
用于解码一个拆开指令的解码器; For decoding a disassembled instruction decoder;
连接到所述存储区域和所述解码器上的电路,用于响应拆开指令,复制从所述第一和第二组的多个数据元素中选择的相应数据元素到所述存储区域作为第三压缩数据中的第三组的多个数据元素。 Connected to a circuit in the storage area and on the decoder, in response to open instruction, copy the corresponding data element selected from the plurality of data elements of said first and second group into the storage area as the first Three compressed data of a plurality of data elements in the third set.
2.权利要求1所述处理器,其中,从所述第一组的多个数据元素复制的数据元素和从所述第二组的多个数据元素复制的数据元素交错放置到所述存储区域,形成第三组的多个数据元素。 The processor of claim 1, wherein said plurality of data elements from the first set of data elements and data elements copied from a copy of a second set of said plurality of data elements are interleaved in the storage area , a plurality of data elements forming a third group.
3.权利要求2所述处理器,其中,所述电路配置为复制所述第一和第二组的多个数据元素中的一半的数据元素。 The processor according to claim 2, wherein the circuit is configured to replicate the first plurality of data elements and a second group of half of the data elements.
4.权利要求2所述处理器,其中,所述第一组的多个数据元素和所述第二组的多个数据元素中的每一个包含2、4或8个数据元素。 The processor of claim 2, wherein said plurality of data elements of the first group and the second group of the plurality of data elements each containing 2, 4 or 8 data elements.
5.权利要求2所述处理器,其中,被复制产生所述第三组的多个数据元素的所述第一组的多个数据元素中的每一个以和所述第一组的多个数据元素在所述第一压缩数据中的同一顺序存储。 The processor of claim 2, wherein the first group are copied to produce a plurality and each of said plurality of said third set of data elements of a plurality of data elements in the first set data element in said first compressed data stored in the same order.
6.一个处理器,包括: 6. A processor, comprising:
用于存放分别包括第一组的多个数据元素和第二组的多个数据元素的第一压缩数据和第二压缩数据的一个存储区域,其中在所述第一组的多个数据元素中的每一个数据元素相应于在所述第二组的多个数据元素中的一个不同的数据元素; Respectively include a memory for storing the compressed data area of the first plurality of data elements of the first group and a second plurality of data elements and a second set of compressed data, wherein the plurality of data elements of the first group Each data element corresponding to a different data elements in the plurality of data elements in the second group;
用于解码一个压缩指令的解码器; For decoding a compressed instruction decoder;
连接到所述存储区域和所述解码器上的电路,用于响应压缩指令,复制所述第一和第二组的多个数据元素中的每一数据元素的一部分到所述存储区域作为第三压缩数据中的第三组的多个数据元素。 Connected to a circuit in the storage area and on the decoder, in response to the compression command, and a copy of said first portion of said storage area to the second group of the plurality of data elements in each of the data elements as the first Three compressed data of a plurality of data elements in the third set.
7.权利要求6所述处理器,其中所述每一数据元素的被复制的部分是所述第一和第二组的多个数据元素中的每一个数据元素位数的一半。 The processor of claim 6, wherein the copied portion of said each data element is one-half the number of bits of each data element of said plurality of data elements of the first and second groups of.
8.权利要求7所述处理器,其中,所述每一数据元素的被复制的部分是所述第一和第二组的多个数据元素中的每一个数据元素的低阶或高阶位。 The processor of claim 7, wherein the copied portion of said each data element is the low order or high order bits of said plurality of data elements of the first and second groups of each data element .
9.权利要求8所述处理器,其中,从所述第一组的多个数据元素中的数据元素复制的部分相邻存储在所述第三组的多个数据元素中。 The processor of claim 8, wherein said plurality of data elements from the first set of data elements adjacent to the part in the replication of the plurality of data elements stored in the third set.
10.权利要求9所述处理器,其中,从所述第一和第二组的多个数据元素中复制的部分以和所述第一和第二组的多个数据元素在所述第一和第二压缩数据中的同样的顺序存储。 10. The processor of claim 9, wherein the plurality of data copied from the first set of elements and a second portion and said plurality of data elements and a second set of a first of said first and the second compressed data stored in the same order.
11.权利要求10所述处理器,其中,在所述第一和第二组的多个数据元素中的所有数据元素都带符号;以及其中,在所述第三组的多个数据元素中的所有数据元素或者带符号或者不带符号。 11. The processor of claim 10, wherein all data elements in the plurality of data elements in the first and second sets are signed; and wherein, in said plurality of data elements in the third set All data elements or signed or unsigned.
12.权利要求11所述处理器,其中,所述第三组的多个数据元素中的所有数据元素或者饱和或者不饱和。 12. The processor of claim 11, wherein said plurality of data elements in the third set of all data elements or a saturated or unsaturated.
13.权利要求6所述处理器,其中,所述第一和第二组的多个数据元素的每一个数据元素包含2、4或者8个数据元素。 13. The processor of claim 6, wherein said first plurality of data elements and each of the second group of data elements comprising 2, 4 or 8 data elements.
Description  translated from Chinese
可以对复合操作数进行压缩操作和拆开操作的微处理器 Composite operands can compress operation and open operation microprocessor

发明背景 Background of the Invention

[002] 本发明包括使用单个控制信号处理多个数据元素而执行操作的一种装置和方法。 [002] The present invention includes an apparatus and method for performing operations using a single control signal processing a plurality of data elements. 本发明允许对压缩数据类型执行移动、压缩和拆开的操作。 The present invention allows the implementation of a mobile type of compressed data, the compression and open operations.

[003] 当今,大多数个人计算机系统的工作机制是使用一个指令产生一个结果。 [003] Today, most personal computer systems working mechanism is to use a command to produce a result. 通过增加指令的执行速度和处理器指令的复杂程度以及并行执行多个指令来增加处理器性能,这种计算机称为复杂指令集计算机(CISC)。 By increasing the complexity of the instruction execution speed and processor instructions and execute multiple instructions in parallel to increase processor performance, such computer-called complex instruction set computer (CISC). 例如加里福尼亚州Santa Clara的INTEL公司的INTEL80386TM微处理器就属于CISC类型的处理器。 For example, in Santa Clara, California company INTEL80386TM INTEL microprocessor belongs CISC processor type.

[004] 先前的计算机系统结构经过优化以利用CISC概念。 [004] previous computer system architecture has been optimized to take advantage of CISC concept. 这样的系统通常具有32位宽的数据总线。 Such systems typically have a 32-bit wide data bus. 然而,针对计算机支持的协作(CSC-电话会议与混合媒体数据操作集成)、2维/3维图像、图像处理、视频压缩/解压、识别算法和音频处理方面的应用增加了对更高性能的需求。 However, for computer-supported cooperative (CSC- conference call mixed media data manipulation and integration), two-dimensional / three-dimensional image, image processing, video compression / decompression, recognition algorithms and audio processing applications increased respect for higher performance needs. 但是,执行速度和指令复杂性的增加只是一种解决方案。 However, the execution speed and complexity increase instruction is a solution.

[005] 这些应用的一个共同的特征是它们常常操作大量的数据,其中只有少数位是重要的。 [005] A common feature of these applications is that they often operate a large number of data, where only a few bits are important. 也就是说,是有关位用比数据总线大小少得多的位表示的数据。 That is, the data on the data bus bit size with much less than the bit representation. 例如,处理器的许多操作是就8位和16位数据执行的(例如视频图像中的像素彩色分量),但是具有宽得多的数据总线和寄存器。 For example, many processors are operating on 8-bit and 16-bit data is performed (e.g., video image pixel color component), but with a much wider data bus and registers. 因此,具有32位数据总线和寄存器并且执行这样一种算法的处理器可能损失多达75%的数据处理、运载和存储能力,因为只有前8位数据是重要的。 Thus, 32-bit data bus and having a register and performs an algorithm that a processor may lose as much as 75% of the data processing, carrying and storage capacity, as only the first 8-bit data is important.

[006] 因此,希望有一个处理器,它通过更加有效地利用表示被操作数据需要的位数和处理器实际数据运载和存储容量之间的差,从而提高其性能。 [006] It is therefore desirable to have a processor, through more efficient use of the data showing the difference between the operated and the number of bits required for actual data processor and storage capacity between the carrier, thereby improving its performance.

[007] 发明总结 [007] invention summary

[008] 本文说明一种改进了数据处理操作的处理器。 [008] This article describes an improved data processing operations.

[009] 一种处理器,它包括存储第一压缩数据的第一寄存器,一个解码器和一个功能单元。 [009] A processor including a first register storing a first compressed data, a decoder and a functional unit. 解码器有一个控制信号输入。 A decoder having a control signal input. 控制信号输入用于接收第一控制信号和第二控制信号。 A first control signal input for receiving a control signal and a second control signal. 第一控制信号用于指示一个压缩操作。 A first control signal for instructing a compression operation. 第二控制信号用于指示一个拆开操作。 A second control signal for instructing an open operation. 功能单元连接到解码器和寄存器。 Functional unit is connected to the decoder and registers. 功能单元使用第一压缩数据执行压缩和拆开操作。 Compressed data using the first functional unit performs a compression operation and disassembled. 处理器还支持移动操作。 The processor supports the move operation.

[010] 根据本发明的一个方面,提供了一个处理器,包括: [010] In accordance with one aspect of the present invention, there is provided a processor, comprising:

[011] 用于存放分别包括第一组的多个数据元素和第二组的多个数据元素的第压缩数据和第二压缩数据的一个存储区域,其中在所述第一组的多个数据元素中的每一个数据元素相应于在所述第二组的多个数据元素中的一个不同的数据元素;用于解码一个拆开指令的解码器;连接到所述存储区域和所述解码器上的电路,用于响应拆开指令,复制从所述第一和第二组的多个数据元素中选择的相应数据元素到所述存储区域作为第三压缩数据中的第三组的多个数据元素。 [011] for storing a plurality of data elements each comprising a first set of first and a plurality of data elements of the second set of compressed data storage area and a second compressed data, wherein the plurality of data in said first group of Each element in the data element corresponding to a different data elements in the plurality of data elements in the second set; means for decoding an open instruction decoder; connected to the storage area and the decoder on the circuit, in response to open instruction, copy the corresponding data element selected from the plurality of data elements of said first and second group into said storage area as the third group of the third plurality of compressed data data element.

[012] 优选地在所述处理器中,从所述第一组的多个数据元素复制的数据元素和从所述第二组的多个数据元素复制的数据元素交错放置到所述存储区域,形成第三组的多个数据元素。 [012] Preferably in the processor, the data elements copied from the first set of the plurality of data elements and data elements copied from the second group of the plurality of data elements are interleaved in the storage area , a plurality of data elements forming a third group.

[013] 优选地,其中所述的电路配置为复制所述第一和第二组的多个数据元素中的一半的数据元素。 [013] Preferably, wherein said circuit is configured to replicate the first plurality of data elements and a second group of half of the data elements.

[014] 优选地,所述第一组的多个数据元素和所述第二组的多个数据元素中的每一个包含2、4或8个数据元素。 [014] Preferably, the plurality of data elements of the first group and the second group of the plurality of data elements each containing 2, 4 or 8 data elements.

[015] 优选地,被复制产生所述第三组的多个数据元素的所述第一组的多个数据元素中的每一个以和所述第一组的多个数据元素在所述第一压缩数据中的同一顺序存储。 [015] Preferably, the copy generation of said plurality of data elements of the third group of the plurality of data elements in the first set and each of said plurality of data elements in the first group in the first a compressed data stored in the same order.

[016] 根据本发明的再一个方面,提供了一个处理器,包括: [016] According to a further aspect of the invention, there is provided a processor, comprising:

[017] 用于存放分别包括第一组的多个数据元素和第二组的多个数据元素的第一压缩数据和第二压缩数据的一个存储区域,其中在所述第一组的多个数据元素中的每一个数据元素相应于在所述第二组的多个数据元素中的一个不同的数据元素; [017] each include a memory for storing the compressed data area of the first plurality of data elements of the first group and a second plurality of data elements and a second set of compressed data, a plurality of first group in which the data elements corresponding to each data element to a different data elements in the plurality of data elements in the second group;

[018] 用于解码一个压缩指令的解码器; [018] for decoding a compressed instruction decoder;

[019] 连接到所述存储区域和所述解码器上的电路,用于响应压缩指令,复制所述第一和第二组的多个数据元素中的每一数据元素的一部分到所述存储区域作为第三压缩数据中的第三组的多个数据元素。 [019] connected to a circuit in the storage area and on the decoder, in response to the compression command, and a copy of the first portion to the second group of the plurality of data elements in each of said data storage elements third compression data area as a plurality of data elements in the third set.

[020] 优选地在所述处理器中,所述每一数据元素的被复制的部分是所述第一和第二组的多个数据元素中的每一个数据元素位数的一半。 [020] Preferably in the processor, the copied portion of said each data element is one-half the number of bits of each data element of said first and second plurality of data elements in the set.

[021] 更优选地,所述每一数据元素的被复制的部分是所述第一和第二组的多个数据元素中的每一个数据元素的低阶或高阶位。 [021] More preferably, the copied portion of said each data element of said first high order and low-order bits or the second group of the plurality of data elements of each data element.

[022] 优选地,其中,从所述第一组的多个数据元素中的数据元素复制的部分相邻存储在所述第三组的多个数据元素中。 [022] Preferably, wherein said plurality of data from adjacent storage elements of the first group of data elements copied portion of said plurality of data elements in the third group.

[023] 优选地,其中,从所述第一和第二组的多个数据元素中复制的部分以和所述第一和第二组的多个数据元素在所述第一和第二压缩数据中的同样的顺序存储。 [023] Preferably, wherein, copied from the first plurality of data elements and a second group of the first portion and the plurality of data elements and a second group in the first and second compression sequentially storing the same data.

[024] 优选地,其中,在所述第一和第二组的多个数据元素中的所有数据元素都带符号;以及其中,在所述第三组的多个数据元素中的所有数据元素或者带符号或者不带符号。 [024] Preferably, wherein all data elements in said first and second plurality of data elements in the set are signed; and wherein all data elements in the plurality of data elements in the third group or signed or unsigned.

[025] 优选地,其中,所述第三组的多个数据元素中的所有数据元素或者饱和或者不饱和。 [025] Preferably, wherein said plurality of data elements in the third set of all data elements or a saturated or unsaturated.

[026] 优选地,其中,所述第一和第二组的多个数据元素的每一个数据元素包含2、4或者8个数据元素。 [026] Preferably, wherein, the first data element and each of the plurality of data elements of the second group comprising 2, 4 or 8 data elements.

[027] 虽然在说明书和附图中包含了大量的细节,但是,本定明由权利要求的范围限定。 [027] Although the amount of detail contained in the specification and drawings, but the present invention is defined by the given scope of the claims. 只有在这些权利要求中提到的限制适用于本发明。 Only the limitations mentioned in these claims as applied to the present invention.

[028] 附图的简要说明 [028] Brief Description

[029] 本发明用附图中的、但不限于附图中的实例说明,相同的参考标号表示相似的元件。 [029] The present invention is used in the figures, but not limited to the examples in the drawings, the same reference numerals denote similar elements.

[030] 图1表示使用本发明的方法和装置的计算机系统的一个实施例; [030] Figure 1 shows an embodiment of the methods and apparatus of the present invention is a computer system embodiment;

[031] 图2表示本发明的处理器的一个实施例; [031] Figure 2 shows an embodiment of a processor of the present invention;

[032] 图3是说明由本发明的处理器使用的操作寄存器文件中的数据的总步骤的流程图; [032] FIG. 3 is a flowchart illustrating operation of the register file is used by the processor of the present invention in the steps of the overall data;

[033] 图4a说明存储器数据类型; [033] Figure 4a illustrates the memory data type;

[034] 图4b、图4c和图4d说明整数数据的寄存器内表示; [034] Figures 4b, 4c and Fig. 4d illustrate the integer representation of data registers;

[035] 图5a表示压缩数据类型; [035] Figure 5a shows the compressed data type;

[036] 图5b,图5c和图5d说明压缩数据的寄存器内表示; [036] Figure 5b, Figure 5c and Figure 5d illustrate the representation of compressed data register;

[037] 图6a表示在该计算机系统中使用的指示使用压缩数据的控制信号格式; [037] Figure 6a shows indicate that use of the computer system in a compressed format of the data control signal;

[038] 图6b表示第二控制信号格式,它可以用于该计算机系统指示使用压缩数据或者整数数据; [038] Figure 6b shows the second control signal format, it can be used for indicating in the computer system using compressed data or integer data;

[039] 图7表示由处理器在对压缩数据执行压缩操作时所遵循的方法的一个实施例; [039] Figure 7 shows the compressed data by a processor perform the method followed when the compression operation of one embodiment;

[040] 图8a表示能够对压缩字节数据实现压缩操作的电路; [040] Figure 8a shows the compressed bytes of data can achieve compression operation of the circuit;

[041] 图8b表示能够对压缩字数据实现压缩操作的电路; [041] Figure 8b shows the compressed digital data can achieve compression operation of the circuit;

[042] 图9表示由处理器在对压缩数据执行拆开操作时所遵循的方法的一个实施例; [042] Figure 9 shows the compressed data by a processor perform the method of operation followed when disassembled one embodiment;

[043] 图10表示能够对压缩数据实现拆开操作的电路。 [043] Figure 10 shows the compressed data can be realized open circuit operation.

[044] 优选实施例的说明 Description [044] of the preferred embodiment

[045] 本文叙述了对多个数据元素进行移动、压缩和拆开操作的处理器。 [045] This paper describes the multiple data elements to move, compress and open operation of the processor. 在下面的说明中,叙述了大量的诸如电路等这样的细节,以便提供对本发明彻底的了解。 In the following description, numerous specific details are described such as circuits and the like, in order to provide a thorough understanding of the present invention. 在另外的场合,为避免不必要地冲淡对本发明的理解,对熟知的结构和技术未作详细的叙述。 In another occasion, in order to avoid unnecessarily dilute understanding of the invention, for well-known structures and techniques have not been described in detail.

[046] 定义 [046] definition

[047] 为了对理解本发明的实施例的说明提供基础,提供下面的定义。 [047] In order to understand the embodiments of the present invention to provide an explanatory basis, following definitions are provided.

[048] 位X到位Y:定义二进制数的一个子字段。 [048] Bit X in place Y: defines a subfield of binary number. 例如字节001110102(以2为基表示)的位5到位0表示子字段1110102,二进制数后面的2表示以2为基。 For example 001,110,102 bytes (base 2 representation) Bit 5 0 indicates subfield 1,110,102 place, behind the two binary numbers represented in base 2. 因此,10002等于810,而F16等于1510。 Therefore, 10002 equals 810, and F16 equal to 1510.

[049] Rx:是一个寄存器。 [049] Rx: a register. 寄存器是能够存储和提供数据的任何设备。 Register is any device capable of storing and providing data. 寄存器的另外的功能下面说明。 Another function registers described below. 一个寄存器不一定是处理器组件的一部分。 A register is not necessarily part of the processor assembly.

[050] DEST:是一个数据地址。 [050] DEST: is a data address.

[051] SRC1:是一个数据地址。 [051] SRC1: is a data address.

[052] SRC2:是一个数据地址。 [052] SRC2: is a data address.

[053] Result:要存储在由DEST寻址的寄存器中的数据。 [053] Result: the data to be stored in the register addressed by the DEST.

[054] Source1:存储在由SRC1寻址的寄存器中的数据。 [054] Source1: data stored in the SRC1 addressed register.

[055] Source2:存储在由SRC2寻址的寄存器中的数据。 [055] Source2: data is stored in the register addressed by the SRC2.

[056] 计算机系统 [056] Computer Systems

[057] 参考图1,可以实现本发明的实施例的计算机系统作为计算机系统100表示。 [057] Referring to Figure 1, embodiments of the present invention may be implemented in a computer system as the computer system 100 represents. 计算机系统100包括总线101或者其它传输信息的通信硬件和软件以及与总线101连接的处理信息的处理器109。 The computer system 100 includes a bus 101 or other communications hardware and software to transfer information and a processor 101 connected to bus 109 for processing information. 计算机系统100另外还包括一个随机存取存储器(RAM)或者其它动态存储设备(称为主存储器104),它连接到总线101上,用于存储信息和要由处理器109执行的指令。 The computer system 100 additionally includes a random access memory (RAM) or other dynamic storage device (referred to as main memory 104), which is connected to the bus 101, storing information and instructions to be executed by processor 109 for. 主存储器104也可以用于暂存变量或者其它在处理器109执行指令时期的中间信息。 The main memory 104 can also be used for temporary storage variables or other intermediate information processor 109 performs instruction period. 计算机系统100还包括连接在总线101上的只读存储器(ROM)106,和/或其它静态存储设备,用于存储静态信息和处理器109要执行的指令。 The computer system 100 also includes a bus 101 connected to the read only memory (ROM) 106, and / or other static storage device to store static information and instructions to processor 109 for execution. 数据存储设备107连接到总线101上用于存储信息和指令。 Data storage device 107 is connected to for storing information and instructions on the bus 101.

[058] 另外,数据存储设备107,例如磁盘或光盘以及它们相应的驱动器,可以连接到计算机100上。 [058] In addition, the data storage device 107, such as a disk or CD-ROM as well as their corresponding drive, you can connect to the computer 100. 计算机系统100也可以通过总线101连接到一个显示设备121上,以便显示信息给计算机用户。 The computer system 100 may also be connected to a display device 121 via bus 101, to display information to a computer user. 显示设备121可以包括一个帧缓冲器,专用图形处理设备,一个阴极射线管(CRT),和/或一个平面面板显示器。 The display device 121 may include a frame buffer, a dedicated graphics processing apparatus, a cathode ray tube (CRT), and / or a flat panel display. 通常一个包括字母数字和其它键的字母数字输入设备122连接到总线101上,用于给处理器109传输信息和命令选择。 Typically, an alphanumeric input device 122, including alphanumeric and other keys coupled to the bus 101 for transmitting information to the processor 109 and command selections. 另一类型的用户输入设备是光标控制设备123,例如鼠标、轨迹球、光笔、触摸屏、或者光标指示键,用于给处理器109传输方向信息和命令选择以及控制光标在显示设备121上的移动。 Another type of user input device is cursor control device 123, such as a mouse, trackball, light pen, touch screen, or the cursor keys, for transmission to the processor 109 and the direction information and command selections to control the cursor in the display on the mobile device 121 . 这种输入设备通常在两个轴上有两个自由度,第一轴(例如x轴)和第二轴(例如y轴),它们允许光标控制设备在一个平面内指定位置。 This input device typically has two degrees of freedom in two axes, a first axis (e.g., x-axis) and a second axis (e.g., y axis), which allows a cursor control device to specify positions in a plane. 然而本发明不应该局限于只有两个自由度的输入设备。 However, the present invention should not be limited to input devices with only two degrees of freedom.

[059] 另一个可以连接到总线101上的设备是硬拷贝设备124,它可能用于在诸如纸、胶片、或者类似类型介质上打印指令、数据或者其它信息。 [059] can be connected to another device on the bus 101 is hard copy device 124, it may be used, such as paper, film, or similar types of media on the print command, data, or other information. 另外计算机系统100可以连接到声音记录和/或回放设备125上,例如连接到一个麦克风上记录信息的音频数字转换器。 Another computer system 100 may be connected to and / or sound playback device 125 is recorded, for example, connected to a microphone recording audio digitizer information. 另外,该设备还可能包括一个连接到数/模(D/A)转换器的扬声器,用于回放数字化的声音。 Additionally, the apparatus may also include a connection to a digital / analog (D / A) converter is a speaker, for playing back the digitized sounds.

[060] 还有,计算机系统100可以是一个计算机网络(例如一个局域网)的一个终端。 [060] In addition, computer system 100 may be a computer network (e.g., a local area network) of a terminal. 这样,计算机系统100便是包括若干连网设备的一个计算机系统的一个计算机子系统。 Thus, computer system 100 is a computer subsystem comprising a plurality of networked computer system device. 计算机系统100可以包括视频数字化设备126。 The computer system 100 may include a video digitizing device 126. 视频数字化设备126可以用于获取视频图像,而传输给网络中的其它设备。 Video digitizing device 126 can be used to obtain video images, is transferred to the other network devices.

[061] 计算机系统100对于支持计算机支持的协作(CSC-电话会议与混合介质数据操作的集成)、2维/3维图形、图像处理、视频压缩/解压、识别算法和音频操作十分有用。 [061] The computer system 100 to support computer-supported collaborative (CSC- teleconference mixed media data manipulation and integration), 2-D / 3-D graphics, image processing, video compression / decompression, recognition algorithms and audio operation is very useful.

[062] 处理器 [062] Processor

[063] 图2表示处理器109的详图。 [063] Figure 2 shows a detail of 109 processors. 处理器109可以在使用一层或多层诸如BiCMOS、CMOS和NMOS等工艺技术的基底上实现。 Processor 109 may be implemented on one or more layers, such as the use of technology BiCMOS, CMOS and NMOS like substrate.

[064] 处理器109包括一个解码由处理器109使用的控制信号和数据的解码器202。 [064] processor 109 includes a processor 109 is decoded by the decoder using the control signal and data 202. 然后数据可以通过内部总线205存储在寄存器文件204中。 Data can then be stored via the internal bus 205 in the register file 204. 显然,一个实施例的寄存器不应该局限于特定类型的电路,相反,一个实施例的寄存器只需要能够存储和提供数据,以及执行这里叙述的功能。 Obviously, an embodiment of the register should not be limited to a particular type of circuit, the contrary, the register of an embodiment need only capable of storing and providing data, and performing the functions described herein.

[065] 根据不同的数据类型,数据可能存储在整数寄存器组201、寄存器组209、状态寄存器组208或者指令指针寄存器211中。 [065] Depending on the type of data, the data group may integer registers 201, registers 209, status registers 208 or instruction pointer register group 211 are stored in. 其它的寄存器例如浮点寄存器可以包含在寄存器文件204中。 Other registers such as the floating-point register file 204 may include a register in. 在一个实施例中,整数寄存器组201存储32位整数数据。 In one embodiment, the integer register group 201 stores 32-bit integer data. 在一个实施例中寄存器209组包括8个寄存器,R0 212a到R7 212h。 In one embodiment, register group 209 includes eight registers embodiment, R0 212a to R7 212h. 寄存器组209中的每一个寄存器为64位长。 Register set 209 in each register is 64 bits long. R0 212a、R1 212b和R2 212c是寄存器组209中单个寄存器的例子。 R0 212a, R1 212b and R2 212c are examples of register set 209 in a single register. 寄存器组209中的一个寄存器的32位可以移动到整数寄存器组201中的一个整数寄存器中。 A register bank 209 of 32-bit register can be moved into an integer register set 201 in an integer register. 类似地,一个整数寄存器中的值可以移动到寄存器组209中的一个寄存器的32位中。 Similarly, an integer value in the register 32 can be moved to a register group 209 in the register.

[066] 状态寄存器组208指示处理器109的状态。 [066] 208 instruction set processor status register 109 status. 指令指针寄存器211存储下一要执行的指令的地址。 Address of the instruction pointer register 211 stores the next instruction to be executed. 整数寄存器组201、寄存器组209、状态寄存器组208、和指令指针寄存器211都连接到内部总线205上。 Integer register set 201, register group 209, group of state registers 208, and instruction pointer register 211 are connected to the internal bus 205. 任何另外的寄存器也都应该连接到内部总线205上。 Any additional registers also be connected to the internal bus 205.

[067] 在另一个实施例中,这种寄存器中的某一些可以用于两种类型的数据。 Example, a number of such registers may be used for both types of data [067] In yet another embodiment. 例如,寄存器组209和整数寄存器组201可以组合,其中每一个寄存器既可以存储整数数据也可以存储压缩数据。 For example, register set 209 and the integer register set 201 may be combined, in which each register can store either integer data to be stored compressed data. 在另一个实施例中,寄存器组209可以用作浮点寄存器组。 In another embodiment, the register bank 209 can be used as floating point registers. 在这一实施例中,压缩数据或者浮点数据可以存储在寄存器组209中。 In this embodiment, the compressed data or floating point data can be stored in the register group 209. 在一个实施例中,组合寄存器为64位长,而整数用64位表示。 In one embodiment, the combination of the register is 64 bits long, and a 64-bit integer representation. 在该实施例中,在存储压缩数据和整数数据时,寄存器不需区分这两种数据类型。 In this embodiment, in storing the compressed data and integer data, the registers do not need to distinguish between the two data types.

[068] 功能单元203执行由处理器109执行的操作。 [068] function unit 203 perform the operations executed by the processor 109. 这样的操作包括移位、加法、减法和乘法等。 Such operations include shift, addition, subtraction and multiplication. 功能单元203连接到内部总线205。 Function unit 203 is connected to the internal bus 205. 高速缓冲存储器206是处理器109的一个选件,可以用于缓冲存储例如来自主存储器104的数据和/或控制信号。 Cache memory 206 is an optional processor 109, may be used such as buffered data and / or control signals from the main memory 104. 高速缓冲存储器206连接到解码器202以接收控制信号207。 Cache memory 206 is connected to the decoder 202 to receive control signal 207.

[069] 图3表示处理器109的总操作。 [069] Figure 3 shows the total operating processor 109. 也就是说,图3表示处理器109在对压缩数据执行操作、对未压缩数据执行操作或者执行某个其它操作时遵循的步骤。 That is, in Figure 3 indicates that the processor 109 to perform operations on the compressed data, perform operations on the data compression is not performed or the steps to follow some other operation. 例如这样的操作包括用从高速缓冲存储器206、主存储器104、只读存储器(ROM)106或者数据存储设备107的数据加载寄存器文件204中的一个寄存器的加载操作。 Such operations include, for example with from the cache memory 206, data in the main memory 104, read only memory (ROM) 106 or data storage device 107 of the register file load operation to load a register 204. 在本发明的一个实施例中,处理器109支持由加里福尼亚州圣大克拉热INTEL公司的INTEL80486TM支持的大多数指令。 In one embodiment of the present invention, the processor 109 is supported by the California Santa carat hot INTEL company INTEL80486TM supports most of the instructions. 在本发明另一个实施例中,处理器109支持由加里福尼亚州圣大克拉热INTEL公司的INTEL 80486TM支持的全部操作。 Embodiment, the processor 109 is supported by the California Santa carat hot INTEL INTEL 80486TM support the company's overall operations implemented in another embodiment of the invention. 在本发明的再一个实施例中,处理器109支持由加里福尼亚州圣大克拉热INTEL公司制造的奔腾处理器、INTEL 80486TM处理器、80386TM处理器、INTEL 80286TM处理器、和INTEL 8086TM处理器支持的全部操作。 Pentium processor in another one embodiment of the present invention, the processor 109 supports manufactured by California Santa carat hot INTEL company, INTEL 80486TM processor, 80386TM processor, INTEL 80286TM processor, and the processor INTEL 8086TM supports all operations. 在本发明的另一个实施例中,处理器109支持由加里福尼亚州Santa Clara的INTEL公司定义的IATM-INTEL结构支持的全部操作(参见“微处理器”,INTEL数据丛书卷1和卷2,1992年和1993年,加里福尼亚州Santa Clara INTEL公司出版)。 In another embodiment of the present invention, the processor 109 supports IATM-INTEL structure supported by California's Santa Clara INTEL company defined the entire operation (see "microprocessor", INTEL Data Series Volume 1 and Volume 2 , 1992 and 1993, California Santa Clara INTEL publishing company). 一般来说,处理器109可以支持奔腾处理器的当前指令集,但是也可以修改为支持未来指令以及这里叙述的指令集的集合。 Generally, processor 109 can support current Pentium processor instruction set, but can also be modified to support future instruction set described herein and instruction set. 重要的是,处理器109除这里叙述的操作外,可以支持先前所用的操作。 Importantly, the processor 109 in addition to the operation described herein, but may be used to support operations previously.

[070] 在步骤301,解码器202从高速缓冲存储器206或者总线101接收一个控制信号207。 [070] In step 301, the decoder 202 receives from the cache 206 or bus 101 a control signal 207. 解码器202解码控制信号以判定要执行的操作。 The decoder 202 decodes the control signal to determine the action to be performed.

[071] 在步骤302,解码器202访问寄存器204或者存储器中的一个存储单元。 [071] In step 302, the decoder 202 to access the memory in the register 204 or a storage unit. 根据在控制信号207中指定的寄存器地址访问寄存器文件204中的寄存器或在存储器中的存储单元。 In accordance with the control signal 207 in the specified register address to access the register file 204 registers or memory cells in the memory. 例如,为对压缩数据进行操作,控制信号207可以包括SRC1、SRC2和DEST寄存器地址。 For example, to operate on compressed data, the control signal 207 may include SRC1, SRC2 and DEST register addresses. SRC1是第一源寄存器地址。 SRC1 is the first source register address. SRC2是第二源寄存器地址。 SRC2 is the second source register address. 在一些情况下,SRC2地址是可选项,因为并非所有的操作需要两个源地址。 In some cases, SRC2 address is optional as not all operations require two source addresses. 如果一个操作不需要SRC2地址,则只使用SRC1地址。 If an operation is not required SRC2 address, only the SRC1 address. DEST是存储结果数据的目的寄存器的地址。 DEST is the address of the destination register to store the result data. 在一个实施例中,SRC1或SRC2也用作DEST。 In one embodiment, SRC1 or SRC2 is also used as DEST. SRC1、SRC2和DEST将结合图6a和图6b更充分地说明。 SRC1, SRC2 and DEST connection with Figures 6a and 6b explained more fully. 存储在相应寄存器中的数据分别称为Source1、source2和Result。 Data stored in the corresponding registers are called Source1, source2 and Result. 它们每一个为64位长。 Each of them is 64 bits long.

[072] 在本发明的另一个实施例中,SRC1、SRC2和DEST中的任何一个或者全部可以定义为处理器109中的可寻址存储器空间的一个存储单元。 [072] In another embodiment of the present invention, SRC1, SRC2 and DEST any one or all of which may be defined as one memory cell processor 109 in the embodiment of the addressable memory space. 例如,SRC1可能确定在主存储器104中的一个存储单元,而SRC2确定在整数寄存器组201中的第一寄存器,以及DEST确定寄存器组209中的第二寄存器。 For example, SRC1 may identify a main memory 104 in the storage unit, and SRC2 integer register group 201 is determined in the first register, and DEST register group 209 is determined in a second register. 这里为说明简单起见,参考标号是对寄存器文件204的访问标注的,然而这些访问也可以对存储器进行。 For simplicity of description herein, reference numeral 204 is the access to the register file annotation, but which may also be access to memory.

[073] 在本发明的另一个实施例中,操作码只包含两个地址,SRC1和SRC2。 [073] In another embodiment of the present invention, the operation code includes only two addresses, SRC1 and SRC2. 在该实施例中,运算结果存储在SRC1或SRC2寄存器中,也就是说,SRC1(或SRC2)用作DEST。 In this embodiment, the operation result is stored in the SRC1 or SRC2 register, that is to say, SRC1 (or SRC2) used as DEST. 这种类型的寻址与前面只具有两个地址的CISC指令兼容。 CISC instruction addressing this type of previously having only two addresses compatible. 这简少了解码器202的复杂性。 This simplifies the complexity of the decoder less 202. 注意,在这一实施例中,如果在SRC1寄存器中包含的数据不准备破坏,则在执行操作前必须首先把该数据复制到另一个寄存器中。 Note that, in this embodiment, if the data contained in the SRC1 register Ready damage, it must first of all replicated before the operation of the data to another register. 这一复制需要一个另外的指令。 This replication requires an additional instruction. 这里为说明简单起见,将使用三地址寻址模式(亦即SRC1、SRC2和DEST)。 Here for simplicity of description, will address the use of three addressing modes (ie SRC1, SRC2 and DEST). 然而应当记住,在一个实施例中,控制信号可能只包括SRC1和SRC2,以及SRC1(或SRC2)标识目的寄存器。 It should be remembered, however, in one embodiment, the control signal may include only the SRC1 and SRC2, and SRC1 (or SRC2) identifies the destination register.

[074] 在控制信号需要一个操作时,在步骤303,允许功能单元203对来自寄存器文件204的被访问的数据执行该项操作。 [074] when the control signal needed an operation, in step 303, the function unit 203 allows data from the register file is accessed 204 perform the operation. 一旦功能单元203执行完这一操作,在步骤304,则根据控制信号207的要求把结果回存到寄存器文件204中。 Once the function unit 203 executed this operation, in step 304, then in accordance with the requirements of the control signal 207 the results back into the register file 204.

[075] 数据和存储格式 [075] data and storage format

[076] 图4a表示可以用于图1的计算机系统的一些数据格式。 [076] Figure 4a shows some data formats can be used for the computer system of FIG. 1. 这些数据格式是定点格式。 The data format is fixed point format. 处理器109可以操作这些数据格式。 Processor 109 can operate these data formats. 多媒体算法常常使用这些数据格式。 Multimedia algorithms often use the data format. 一个字节401包含8个信息位。 A byte 401 contains eight bits of information. 一个字402包含16个信息位,或者两个字节。 An information word 402 includes 16 bits, or two bytes. 一个双字403包含32个信息位,或者4个字节。 A double word 403 contains 32 information bits, or 4 bytes. 于是,处理器109执行可能操作这些存储器数据格式中任何一个的控制信号。 Thus, processor 109 may perform any of these memory data formats of a control signal operation.

[077] 在下面的说明中,对位、字节、字、和双字的子字段加参考标号。 [077] In the following description, the sub-field bit, byte, word, and double word plus reference numerals. 例如,字节001110102(以2为基表示)的位6到位0表示子字段1110102。 For example, the byte 001,110,102 (base 2 representation) of bits 6 0 indicates subfield 1,110,102.

[078] 图4b到图4d表示本发明的实施例中使用的寄存器内表示。 [078] Figure 4b to Figure 4d shows the embodiment of the present invention is used in the register indicates. 例如无符号字节寄存器内表示410可以表示存储在整数寄存器组201中的一个寄存器中的数据。 For example, in an unsigned byte register indicates a register 410 may represent data stored in the integer registers 201 in the group. 在一个实施例中,整数寄存器组201中的一个寄存器为64位长。 In one embodiment, the integer register set 201 in a register is 64 bits long. 在另一个实施例中,整数寄存器组201中的一个寄存器为32位长。 In another embodiment, the integer register set 201 a register is 32 bits long. 为说明简单起见,下面叙述64位的整数寄存器,然而也可以使用32位的整数寄存器。 For simplicity of description, the following describes a 64-bit integer registers, but also can use a 32-bit integer registers.

[079] 无符号字节的寄存器内表示410示出处理器109在整数寄存器组201中存储一个字节401,在该寄存器中的头8位,即位7到位0用于该数据字节401。 [079] an unsigned byte register representation 410 shows a processor 109 stores in integer registers 201, a group of 401 bytes, in the register of the first eight, came to the throne in place 0 7 401 for the data byte. 这些位表示为{b}。 These bits are represented as {b}. 为适当地表示这一字节,其余的56位必须为0。 To properly represent the byte, the rest of the 56 must be zero. 对于一个有符号字节的寄存器内表示411,整数寄存器组201在头7位,即位6到位0存储该数据,为数据部分,第7位表示符号位,图中表示为{S}。 For a signed byte register 411 represents the integer register group 201 in the first seven, bits 6 to bit 0 of the data storage, the data portion, bit 7 represents the sign bit, indicated as {S}. 其余的位63到位8为该字节的符号的延续。 The remaining bits 63 in place of 8 bytes for the continuation of the symbol.

[080] 无符号字的寄存器内表示412存储在整数寄存器组201中的一个寄存器中。 [080] an unsigned word register indicates a register 412 is stored in the integer registers 201 in the group. 位15到位0包含一个无符号字402。 Bit 15 to Bit 0 contains an unsigned word 402. 这些位表示为{w}。 These bits are denoted as {w}. 为适当地表示该字,其余的位63到位16必须为0。 This character is represented where appropriate, the remaining bits 63 in place 16 must be zero. 带符号的字402存储在位14到位0,如带符号字的寄存器内表示413所示。 Word 402 stores the bit unsigned 14 bit 0, as in the register unsigned word shown represent 413. 其余的位64到位15是符号字段。 64 to 15 of the remaining bits are symbolic field.

[081] 双字403可以作为无符号双字的寄存器内表示414存储,或者作为带符号双字的寄存器内表示415存储。 [081] 403 may be within a double word as an unsigned double word registers, said 414 stores, or as an internal unsigned double word represents 415 storage registers. 无符号双字的寄存器内表示414的位31到位0为数据。 An unsigned double-word 31-bit register indicates 414 0 place for data. 这些位表示为{d}。 These bits are denoted as {d}. 为适当表示该无符号双字,其余的位63到位32必须为0。 Appropriate representation of the unsigned double word, the remaining bits must be 0 32 63 place. 整数寄存器组201在其位30到位0存储一个带符号双字的寄存器内表示415,其余的位63到位31是符号字段。 201 represents the integer register set 415 in its storage position 30 in place 0 a signed double word register, and the remaining 63 to 31 is the sign bit field.

[082] 如上面图4b到图4d所示,一些数据类型在64位宽的寄存器中的存储是一种低效的存储方法。 [082] As above, as shown in Figure 4b to Figure 4d, a number of data types are stored in 64-bit wide register is an inefficient storage method. 例如,为存储一个无符号字节的寄存器内表示410,位63到位8必须为0,而只有位7到位0可能包含非0位。 For example, for the storage of an unsigned byte register indicates 410, 8-bit 63 in place must be 0, but only bits 7 to 0 may contain non-0. 因此,在一个64位寄存器中存储一个字节的处理器只使用寄存器容量的12.5%。 Thus, a byte is stored in a 64-bit register in the processor using only 12.5% of the capacity of the register. 相似地,由功能单元203执行的操作只有前几位是重要的。 Similarly, the operations performed by the functional unit 203 is only the first of several important.

[083] 图5a表示压缩数据的数据格式。 [083] Figure 5a shows the data format of the compressed data. 每一压缩数据包括多于一个独立的数据元素。 Each compressed data include more than one independent data element. 图中说明3种压缩数据格式:压缩字节501,压缩字502和压缩双字503。 Illustrated in Figure 3 kinds of compressed data format: 501 bytes compression, compression word 502 and 503 compression double word. 在本发明的一个实施例中,压缩字节为64位长,包含8个数据元素,每一个数据元素为一字节长。 In one embodiment of the present invention, the compression is 64 bytes long and contains eight data elements, each data element is one byte long. 一般来说,一个数据元素是一个单个的数据,它与具有同样长度的其它数据元素存储在一个单一寄存器中(或存储单元)。 Generally, a data element is an individual data, which is stored with the other data elements having the same length in a single register (or memory cells). 在本发明的一个实施例中,存储在一个寄存器中的数据元素的数目等于64除以数据元素的位长。 In one embodiment of the present invention, the number of data elements stored in a register is equal to 64 divided by the bit length of the data element.

[084] 压缩字502为64位长,包含4个字402数据元素。 [084] packed word 502 is 64 bits long and contains four word 402 data elements. 每一个字402数据元素包含16个信息位。 Every word 402 data element contains 16 bits of information.

[085] 压缩双字503为64位长,包含两个双字403数据元素。 [085] 503 compression double word length is 64, including two pairs of word 403 data elements. 每一个双字403数据元素包含32个信息位。 Each double-word 403 data element contains 32 bits of information.

[086] 图5b到图5d表示寄存器内压缩数据存储表示。 [086] Figure 5b to Figure 5d shows the compressed data stored within the register indicated. 无符号压缩字节的寄存器内表示510示出压缩字节501在寄存器组R0212a到寄存器组Rn212af中的一个寄存器中的存储方式。 An unsigned byte register compressed representation of compressed bytes 501 510 shown in the register-to-register group Rn212af group R0212a a register storage. 每个字节数据元素的信息对于字节0存储在位7到位0,对于字节1存储在位15到位8,对于字节2存储在位23到位16,对于字节3存储在位31到位24,对于字节4存储在位39到位32,对于字节5存储在位47到位40,对于字节6存储在位55到位48,对于字节7存储在位63到位56。 Information for each byte of data elements stored in the bit for byte 0 0 7 in place for a byte stored in the bit 15 bit 8 for byte 2 stored in the bit 23 in place 16, 31 stored in the bit for byte 3 place 24, 4 bytes stored in the bit 39 for 32 in place, for the reign of 47-byte storage place 5 40 6 bytes of storage in place for 55 place 48, stored in the bit for byte 7 63 56 place. 因此寄存器中所有可用的位都被使用。 Thus all of the available bits in the register are used. 这种存储安排增加了处理器的存储效率。 This storage arrangement increases the storage efficiency of the processor. 另外,通过访问8个数据元素,现在可以同时对8个数据元素执行操作。 Further, now perform operations by accessing eight data elements simultaneously eight data elements. 带符号压缩字节的寄存器内表示511类似地存储在寄存器组209中的一个寄存器中。 A register signed packed byte representation 511 is similarly stored in the register group 209 in a register. 注意,每一字节数据元素只有第8位是必须的符号位,其它位可以用于或者可以不用于指示符号。 Note that each byte data element is only the first 8 necessary sign bit, other bits may be used or may not be used to indicate the symbol.

[087] 无符号压缩字的寄存器内表示512示出字3到字0是怎样存储在寄存器组209中的一个寄存器中的。 [087] within the unsigned packed word representation registers 512 shows three word to word 0 is what is stored in a register in the register set 209 in. 位15到位0包含对于字0的数据元素信息,位31到位16包含对于字1的数据元素信息,位47到位32包含对于字2的数据元素信息,而位63到位48包含对于字3的数据元素信息。 Bit 15 to Bit 0 contains data elements for information word 0, bit 31 in place 16 contains data elements for an information word, 47-bit word in place 32 contains two data elements for information, while 48-bit 63 in place for the word 3 contains data elements of information. 带符号压缩字的寄存器内表示513类似于无符号压缩字的寄存器内表示512。 A register signed packed word representation 513 is similar to unsigned packed word representation 512 registers. 注意,每一字数据元素只有第16位包含必要的符号指示符。 Note that each data element only the first word 16 contains the necessary symbolic indicator.

[088] 无符号压缩双字的寄存器内表示514表示寄存器组209怎样存储两个双字数据元素。 [088] within the unsigned packed doubleword register 514 indicates that the register 209 represents how the data elements stored in two double words. 双字0存储在寄存器的位31到位0。 Double word 0 0 storage place in 31-bit registers. 双字1存储在寄存器的位63到位32。 Double word is stored in a 63-bit register 32 in place. 带符号压缩双字的寄存器内表示515类似于无符号压缩双字的寄存器内表示514。 A register signed packed doubleword representation within 515 similar to unsigned packed doubleword registers represent 514. 注意,必要的符号位是该双字数据元素的第32位。 Note that the necessary sign bit is bit 32 of the doubleword data element.

[089] 如前所述,寄存器组209既可以用于压缩数据,也可以用于整数数据。 [089] As described above, the register group 209 can be used to compress both the data to be used for integer data. 在本发明的这一实施例中,可以要求单个程序处理器109跟踪一个被寻址的寄存器,例如R0212a,是否正在存储压缩数据或者简单整数/定点数据。 In this embodiment of the present invention may be required to track a single program processor 109 to the addressed register, e.g. R0212a, if compressed data is being stored, or simply the integer / fixed-point data. 在另一可选实施例中,处理器109可以跟踪存储在寄存器组209中的单个寄存器中的数据类型。 In another alternative embodiment, the processor 109 can track the individual registers in the register group 209 are stored in the data type. 因此,如果例如试图对简单/定点整数数据施行一个压缩的加法运算的话,这一可选实施例可能产生错误。 So, if for example, attempt to Simple / fixed-point integer data compression implemented an addition operation, then this alternative embodiment, errors may occur.

[090] 控制信号格式 [090] control signal format

[091] 下面说明处理器109所用操作压缩数据的控制信号格式的一个实施例。 [091] The following describes the processor 109 with a control signal format of the data compression operation of one embodiment. 在本发明的一个实施例中,控制信号用32位表示。 In one embodiment of the present invention, the control signal 32 indicates. 解码器202可以从总线101接收控制信号207。 Decoder 202 may receive a control signal 207 from the bus 101. 在另一个实施例中,解码器202也可以从高速缓冲存储器206接收这样的控制信号。 In another embodiment, decoder 202 can also receive such control signals from cache memory 206.

[092] 图6a表示对压缩数据进行操作的控制信号的一般格式。 [092] Figure 6a shows the compressed data format of a control signal of the general operation. 操作字段OP601,即位31到位26,提供关于由处理器109要执行的操作的信息;例如压缩加,压缩减等。 Operation Field OP601, ascended the throne in place 31 26, to provide information about the operation to be executed by the processor 109; for example compression plus, minus, etc. compression. SRC1602,即位25到位20,提供寄存器组209中的一个寄存器的源寄存器地址。 SRC1602, ascended the throne in place 25 20, register 209 provides a register of source register address. 该源寄存器包含在控制信号执行中要用的第一压缩数据,Source1。 The source register contains the first compressed data to use in the execution of the control signal, Source1. 相似地,SRC2 603,即位19到位14,包含寄存器组209中的一个寄存器的地址。 Similarly, SRC2 603, Accession 19 in place 14, the address register group 209 comprises a register. 这一第二源寄存器包含执行操作期间要用到的压缩数据,Source2。 This second source register contains the operation to use during execution of the compressed data, Source2. DEST605,即位5到位0包含寄存器组209中的一个寄存器的地址。 DEST605, ascended the throne in place 5 0 contains the address register 209 in a register. 该目的寄存器将存储压缩数据操作的结果压缩数据Result。 This destination register will store the compressed data is compressed data operation result Result.

[093] 控制位SZ610,即位12和位13,指示在第一和第二压缩数据源寄存器中的数据元素的长度。 [093] control bits SZ610, ascended the throne 12 and bit 13, indicates the length of the first and second compressed data source register data elements. 如果SZ610等于012,则压缩数据作为压缩字节501格式化。 If SZ610 equal to 012, then 501 bytes of compressed data as a compressed format. 如果SZ610等于102,则压缩数据作为压缩字502格式化。 If SZ610 equal to 102, the compressed data word 502 as a compressed format. SZ610等于002或112预留,然而,在另一个实施例中,其中的一个可以用来指示压缩双字503。 SZ610 equal to 002 or 112 is reserved, however, in another embodiment, one can be used to indicate packed doubleword 503.

[094] 控制位T611,即位11,指示该操作是否以饱和方式执行。 [094] control bits T611, ascended the throne 11, indicating whether the operation saturated manner. 如果T611等于1,则执行饱和操作。 If the T611 is equal to 1, the saturation operation is performed. 如果T611等于0,则执行非饱和操作。 If the T611 is equal to 0, then perform a non-saturation operation. 后面说明饱和操作。 Saturation operation described later.

[095] 控制位S612,即位10,指示使用带符号操作。 [095] control bits S612, ascended the throne 10, indicating the use of a signed operation. 如果S612等于1,则执行带符号操作;如果S612等于0,则执行无符号操作。 If the S612 is equal to 1, the operation is performed with sign; if S612 is equal to 0, then execute unsigned operation.

[096] 图6b表示操作压缩数据的控制信号的第二种一般格式。 [096] The general format of Figure 6b shows a second operation of compression control signal data. 该格式相应于在“奔腾处理器系列用户手册”中叙述的一般整数操作码格式,该手册由INTEL公司文献销售部出版,地址为POBox 7641,Mt.prospect,IL,60056-7641。 The format corresponding to the general integer opcode format "Pentium Processor Series User's Manual," described in the handbook published by the INTEL company sales literature, the address is POBox 7641, Mt.prospect, IL, 60056-7641. 注意,OP601,SZ610,T611,和S612都结合在一个大字段中。 Note, OP601, SZ610, T611, and S612 are combined in a large field. 对于一些控制信号,位3到位5是SRC1 602。 For some control signals, bits 3 in place 5 is SRC1 602. 在一个实施例中,其中有一个SRC1 602地址,则位3到位5也相应于DEST605。 In one embodiment, where there is a SRC1 602 address, then bits 3 in place 5 also corresponds to DEST605. 在一个可选的实施例中,其中有一个SRC2 603地址,则位0到位2也相应于DEST605。 In an alternative embodiment, wherein there is a SRC2 603 address, then bits 0 through 2 also corresponds to DEST605. 对于其它的控制信号,例如压缩移位立即操作,位3到位5表示操作码场的扩展。 For other control signals, such as compression shift immediate operation, bits three extensions 5 shows place opcode field. 在一个实施例中,这种扩展允许程序员把一个立即数与控制信号结合,例如一个移位计数值。 In one embodiment, this extension allows the programmer to a literal and control signals combine, such as a shift count. 在一个实施例中,立即数跟着控制信号。 In one embodiment, immediately followed by the number of control signals. 这在“奔腾处理器系列用户手册”一书的附录F,从F-1到F-3页有详细介绍。 This is the "Pentium Processor Series User's Manual," a book of Appendix F, from F-1 to F-3 page contains a detailed description. 位0到位2表示SRC2603。 Bits 0 2 represents SRC2603. 这种一般格式允许寄存器到寄存器,存储器到寄存器,由存储器对寄存器,由寄存器对寄存器,由立即数对寄存器,由寄存器到存储器寻址。 This general format allows register to register, memory to register, register by memory, register by register, register by immediate data from register to memory addressing. 在一个实施例中,这种一般格式也可以支持整数寄存器到寄存器和寄存器到整数寄存器寻址。 In one embodiment, this general format can support integer register to register, and register to integer register addressing.

[097] 饱和/非饱和的说明 [097] saturated / unsaturated description

[098] 如前所述,T611指示操作是否可选为饱和。 [098] As mentioned earlier, T611 indicate whether the operation Optional saturated. 在允许饱和的场合,当一个操作的结果溢出或下溢数据的范围时,其结果被箝位。 Allowing saturated occasions when the result of an operation overflow or underflow range of the data, the result is clamped. 箝位指的是如果结果超过该范围的最大或最小值时把结果设定在最大或最小值。 Clamp refers to the maximum or minimum value if the result exceeds the range of the results set at the maximum or minimum value. 在下溢的场合,饱和把结果箝位在该范围的最小值,而在溢出的场合,饱和把结果箝位在最大值。 The case of underflow, saturation clamps the result in the minimum value of the range, and in the case of overflow, the result is clamped at the maximum saturation. 对于每一种数据格式允许的范围示于表1。 For each of the allowable range of data formats shown in Table 1. 数据格式 最小值 最大值无符号字节 0 255带符号字节 -128 127无符号字 0 65535带符号字 -32768 32767无符号双字 0 264-1带符号双字 -263 263-1 Data minimum maximum unsigned byte format 0255 signed byte unsigned word -128 127 065 535 unsigned word -3276832767 unsigned double word 0264-1 DOUBLE SIGNED -263263-1

[099] 表1 [099] Table 1

[100] 如上所述,T611指示是否正在执行饱和操作。 [100] As noted above, T611 saturation indicates whether the operation is being performed. 因此,使用无符号字节数据格式,如果一个运算结果=258并且允许饱和,则在该结果被存储在该操作的目的寄存器之前被箝位在255。 Therefore, using the unsigned byte data format, if an operation result = 258 and allowed to saturate, then the result is stored in the destination register prior to the operation 255 is clamped. 类似地,如果运算的结果=-32999且处理器109使用带符号字数据格式同时允许饱和,则运算结果在被存储在该运算的目的寄存器之前被箝位在-32768。 Similarly, if the result of operation = -32 999 and 109 processors use unsigned word data format while allowing saturation, the result of the operation before it is stored in the operation of the destination register is clamped to -32768.

[101] 数据处理操作 [101] data processing operations

[102] 在本发明的一个实施例中,多媒体应用的性能不仅通过支持标准的CISC指令集(未压缩数据操作),而且通过支持对压缩数据的操作而得以改善。 [102] In one embodiment of the present invention, the performance of multimedia applications by supporting not only the standard CISC instruction set (uncompressed data manipulation), and by supporting the operation of the compressed data is improved. 这样的压缩数据操作可能包括加法、减法、乘法、比较、移位、与和异或。 Such operations may include the compressed data addition, subtraction, multiplication, compare, shift, with and XOR. 然而,为充分使用这些操作,已经确定,应该包括数据处理操作。 However, to make full use of these operations, it has been determined, the data processing operation should be included. 这样的数据处理操作可能包括移动、压缩和拆开。 Such a data processing operation may include moving, compress and open. 移位、压缩和拆开由于产生出允许程序员容易使用的格式的压缩数据而方便了其它操作的执行。 Shift, due to the generation of compression and disassembled easily allows programmers to use compressed data format convenient to perform other operations.

[103] 对于其它压缩操作的进一步的背景,参见流水号为_,于_申请的“具有比较操作的微处理器”,流水号为_于_申请的“具有移位操作的新型处理器”,流水号为08/176123,于1993年12月30日申请的“处理器中使用压缩数据的方法和装置”,流水号为08/175772,于1993年12月30日申请的“在处理器中使用新型操作的方法和装置”,所有这些申请都转让给本发明的受让人。 [103] For further background other compression operations, see the serial number for the _, _ apply to "a microprocessor comparison operation", the serial number for the application _ in _ "has the shift operation of the new processor." , Serial No. 08/176123, on December 30, 1993 to apply for a "method and apparatus for use in a processor compressed data", serial number for 08/175772, on December 30, 1993 Application "in the processor Method and apparatus "in the use of new operations, all of which applications are assigned to the assignee of the present invention.

[104] 移动操作 [104] move operations

[105] 移动操作把数据传输给寄存器209或从寄存器209传输出数据。 [105] move operations to transfer data to register 209 or 209 to transfer data from the register. 在一个实施例中,SRC2 603是包含源数据的地址,而DEST605是数据要传输到的地址。 In one embodiment, SRC2 603 is an address that contains the source data, while DEST605 is data to be transmitted to the address. 在该实施例中,不用SRC1 602。 In this embodiment, without SRC1 602. 在另一个实施例中,SRC1 602就是DEST605。 In another embodiment, SRC1 602 is DEST605.

[106] 为解释移动操作,要区分寄存器和存储单元这两种情况。 [106] To explain the move operation, the register and the memory unit to distinguish between these two cases. 寄存器在寄存器文件204中寻找,而存储器可以是高速缓冲存储器206、主存储器104、ROM106、数据存储设备107。 Registers in the register file 204 to find, and the memory 206 may be a cache memory, a main memory 104, ROM106, the data storage device 107.

[107] 移动操作可以从存储器到寄存器组209、从寄存器组209到存储器、和从寄存器组209中的一个寄存器到寄存器组209中的另一个寄存器移动数据。 [107] move operation from the memory to the register set 209, to the memory from the register group 209, and from the register bank 209 in a register to another register mobile data register group 209. 在一个实施例中,压缩数据存储在不同于存储整数数据的寄存器中。 In one embodiment, the compressed data stored in the memory is different from the integer data registers. 在该实施例中,移动操作可以把数据从整数寄存器组201移动到寄存器组209中。 In this embodiment, the mobile operator can set the data from the integer register 201 is moved to the register bank 209. 例如,在处理器109中,如果压缩数据存储在寄存器组209中而整数数据存储在整数寄存器组201中,则可以使用移动指令从整数寄存器组201移动数据到寄存器组209,反之亦然。 For example, the processor 109, if the compressed data is stored in the register group 209 and the integer data stored in the integer register set 201, integer instructions can be used to move data from the register group 201 moves to the register group 209, and vice versa.

[108] 在一个实施例中,当为移动指定一个存储器地址时,在存储单元(指示最低有效字节的存储器单元)中的数据的8个字节加载到寄存器组209中的一个寄存器或从该寄存器存储数据的8个字节到该存储单元。 [108] In one embodiment, when specifying a memory address for the mobile, the 8-byte memory cells (indicating the least significant byte of memory cells) in the data loaded into the register set 209 in a register or from This register is 8 bytes to store data to the storage unit. 当指定寄存器组209中的一个寄存器时,该寄存器中的内容被移动到寄存器组209中的第二寄存器或从寄存器组209中的第二寄存器加载内容到该寄存器。 When specifying a register set 209 register, the register contents are moved to register 209 in the second register or load content from the register 209 in the second register to the register. 如果整数寄存器201为64位长,且指定一个整数寄存器,则在该整数寄存器中的数据的8个字节加载到寄存器209中的一个寄存器中或从后者存储在该整数寄存器中。 If the integer register 201 is 64 bits long and specifies an integer register, the 8 bytes in the integer registers of the data loaded into the register 209 in a register or from the latter is stored in the integer registers.

[109] 在一个实施例中,整数用32位表示。 [109] In one embodiment, a 32-bit integer representation. 当从寄存器组209到整数寄存器组201执行移动操作时,则只有低32位压缩数据移动到指定的整数寄存器。 When set to 209 from the register 201 integer registers group move operation, then only the lower 32 compressed data is moved to the specified integer register. 在一个实施例中,高阶32位被置0。 In one embodiment, the high order 32-bit is set to zero. 相似地,当执行从整数寄存器组201到寄存器组209的移动时,只加载寄存器组209中的一个寄存器的低32位。 Similarly, when executed from the integer register set 201 to register set 209 is moving, only the low load register group 209 in a 32-bit register. 在一个实施例中,处理器109支持在寄存器组209的一个寄存器到存储器之间的32位移动操作。 In one embodiment, the processor 109 in the register group 209 to support a 32-bit register to memory move operation between. 在另一个实施例中,只有32位的移动操作是就压缩数据的高阶32位进行的。 In another embodiment, only 32 of the move operation is on the high order 32-bit compressed data carried.

[110] 压缩操作 [110] compression operation

[111] 在本发明的一个实施例中,SRC1 602寄存器包含数据(Source1),SRC2 603寄存器包含数据(Source2),而DEST605寄存器包含运算的结果数据(Result)。 Results [111] In one embodiment of the present invention, SRC1 602 register contains data (Source1), SRC2 603 register contains data (Source2), and the DEST605 register contains operations (Result). 也就是说,Source1的各部分和Source2的各部分压缩在一起产生Result。 In other words, the various parts and each part Source1 Source2 compressed together to produce Result.

[112] 在一个实施例中,压缩操作通过把源压缩字(或双字)的低位字节(或字)压缩到Result的字节(或字)中而把压缩字(或双字)变换为压缩字节(或字)。 [112] In one embodiment, the compression operation by the compression of the source word (or double word) in the low byte (or word) to byte Result compressed (or word) and the packed word (or double word) conversion compressed byte (or word). 在一个实施例中,压缩操作把四压缩字变换为压缩双字。 In one embodiment, the compression operation of the four words are converted to compressed packed doubleword. 这一操作可选使用带符号数据执行。 This operation is optional to use unsigned data execution. 另外,该操作可选使用饱和方式执行。 In addition, the operation of the optional use of saturated manner.

[113] 图7表示对压缩数据执行压缩操作的方法的实施例。 [113] Figure 7 shows the implementation of a method for compressing data compression operation of the embodiment. 该实施例可以在图2中的处理器109中实现。 This embodiment may be processor 109 in Figure 2 is implemented.

[114] 在步骤701,解码器202解码由处理器109接收的控制信号207。 [114] In step 701, the decoder 202 decodes the control signal received by processor 109 207. 于是,解码器202解码:适当的压缩操作的操作码;寄存器组209中的SRC1 602、SRC2 603和DEST605的地址;饱和/非饱和、带符号/无符号、和在压缩数据中的数据元素的长度。 Thus, decoder 202 decodes: the operation code suitable compression operation; register set 209 SRC1 602, address SRC2 603 and DEST605; the saturated / unsaturated, signed / unsigned, and in the compressed data of data elements length. 如前所述,SRC1602(或SRC2 603)可以用作DEST605。 As described above, SRC1602 (or SRC2 603) may be used as DEST605.

[115] 在步骤702,通过内部总线205,解码器202访问寄存器 [115] In step 702, via internal bus 205, decoder 202 to access the register

文件204中的寄存器组209,给出SRC1 602和SRC2603的地址。 File 204 in the register group 209, and SRC2603 given SRC1 602 address. 寄存器组209供给功能单元203存储在SRC1602寄存器中的数据(Source1)和存储在SRC2 603寄存器中的数据(Source2)。 The data (Source1) 203 storage registers 209 supply functional units in SRC1602 register and stored in the register SRC2 603 (Source2). 也就是说,寄存器组209通过内部总线205给功能单元203传输数据。 That is, the register group 209 via the internal bus 205 to transfer data 203 to the functional units.

[116] 在步骤703,解码器202允许功能单元203执行适当的压缩操作。 [116] In step 703, the decoder 202 allows the function unit 203 performs the appropriate compression operation. 解码器202通过内部总线205进一步传输在Source1和Source2中的数据元素的饱和和大小。 Decoders 202 and 205 for further transmission saturated Source1 and Source2 size of data elements via an internal bus. 饱和作为选项用以使在结果数据元素中的数据取最大值。 Saturation as an option to make the data in the results of the data elements to take maximum. 如果在Source1和Source2中的数据元素的值大于或者小于在Result中的数据元素所能表示的值的范围,则相应的结果数据元素设定为其最大或最小值。 If the value in the range of values Source1 and Source2 data element is greater than or less than in the Result data elements can be represented by the corresponding resultant data element is set to its maximum or minimum value. 例如,如果在Source1和Source2中的字数据元素中的带符号值小于080(或对双字来说为08000),则结果字节(或字)数据元素箝位在080(或对双字来说为08000)。 For example, if the word data elements Source1 and Source2 of the unsigned value of less than 0 80 (or double-word terms is 0 8000), the result byte (or word) data elements clamped at 0 80 (or two-word terms is 0 8000). 如果在Source1和Source2中的字数据元素中的带符号值大于07F(或对双字来说为07FFF),则结果字节(或字)数据元素箝位在07F(或07FFF)。 If the word data elements Source1 and Source2 symbol values in the band is greater than 0 7F (or double word is to 0 7FFF), the result byte (or word) data elements clamped to 0 7F (or 0 7FFF).

[117] 在步骤710,数据元素的大小决定下一步要执行哪个步骤。 [117] In step 710, the size of the data elements which decide on the next steps to be performed. 如果数据元素的大小为16位(压缩字502数据),则功能单元203执行步骤712。 If the size of the data element is 16 bits (compressed data word 502), the function unit 203 to step 712. 然而,如果压缩数据的数据元素的大小为32位(压缩双字503数据),则功能单元203执行步骤714。 However, if the size of the compressed data of the data element is 32-bit (double word 503 data compression), the function unit 203 to step 714.

[118] 假定源数据元素的大小为16位,则执行步骤712。 [118] assumed that the size of the source data element is 16, step 712. 在步骤712,执行下面的内容。 In step 712, the following content. Source1位7到0为Result位7到0。 Source1 bits 7-0 to 7-0 Result bit. Source1位23到16为Result位15到8。 Source1 bits 23-16 for Result bits 15-8. Source1位39到32为Result位23到16。 Source1 bits 39-32 for Result bits 23-16. Source1位63到56为Result位31到24。 Source1 bits 63-56 for Result bits 31-24. Source2位7到0为Result位39到32。 Source2 bits 7-0 for Result bits 39-32. Source2位23到16为Result位47到40。 Source2 bits 23-16 for Result bits 47-40. Source2位39到32为Result位55到48。 Source2 bits 39-32 for Result bits 55-48. Source2位63到56为Result31到24。 Source2 bits 63-56 for Result31 to 24. 如果设定了饱和,则测试每一字的高阶位以判定是否要箝位Result数据元素。 If you set the saturation, the high-order bit of each word in the test to determine whether or not to clamp Result data element.

[119] 假定源数据元素的大小为32位,则执行步骤714。 [119] Assume that the source data element size of 32 bits, step 714 is performed. 在步骤714,执行下面的内容。 In step 714, the following content. Source1位15到0为Result位15到0。 Source1 bits 15-0 to 15-0 Result bit. Source1位47到32为Result位31到16。 Source1 bits 47-32 for Result bits 31-16. Source2位15到0为Result位47到32。 Source2 bits 15-0 for Result bits 47-32. Source2位47到32为Result位63到48。 Source2 bits 47-32 for Result bits 63-48. 如果设定了饱和,则测试每一双字的高阶位以判定是否要箝位Result数据元素。 If you set the saturation, the high-order bit double word of each test to determine whether or not to clamp Result data element.

[120] 在一个实施例中,步骤712的压缩操作同时执行。 [120] In one embodiment, step 712 of the compression operation performed simultaneously. 然而,在另一个实施例中,这一压缩操作顺序执行。 However, in another embodiment, the sequence of operations to perform this compression. 在再一个实施例中,一部分压缩操作同时执行,而一部分顺序执行。 In a further embodiment, a portion of the compression operation performed simultaneously, and a portion sequentially. 这一讨论也适用于步骤714的压缩操作。 This discussion also applies to step 714 to compress operation.

[121] 在步骤720,Result存储在DEST605寄存器中。 [121] Step 720, Result stored in DEST605 register.

[122] 表2表示非饱和无符号字压缩操作的寄存器内表示。 Expressed in the [122] Table 2 shows the unsaturated unsigned word compression operation register. 第一行的位为Source1的压缩数据表示。 Source1 bits for the first line of compressed data representation. 第二行的位为Source2的数据表示。 The second row is Source2 bit data representation. 第三行的位为Result的压缩数据表示。 Third in line for the Result of compressed data representation. 每一数据元素位下面的数字是该数据元素的号码。 Each data element position following figures are the number of data elements. 例如,Source1数据元素3是100000002。 For example, Source1 data element 3 is 100000002.

[123] Source100101010 01010101 01010101 11111111 10000000 01110000 10001111 10001000 [123] Source100101010 01010101 01010101 11111111 10000000 01110000 10001111 10001000

[124] 3 2 0 [124] 320

[125] 1 [125] 1

[126] Source2 00000000 00000000 11000000 00000000 11110011 0000000010001110 10001000 [126] Source2 00000000 00000000 11000000 00000000 11110011 0000000010001110 10001000

[127] 3 2 0 [127] 320

[128] 1 [128] 1

[129] Rcsult00000000 00000000 00000000 100010000 01010101 11111111 01110000 100010000 [129] Rcsult00000000 00000000 00000000 100010000 01010101 11111111 01110000 100010000

[130] 7 6 5 4 3 2 1 0 [130] 76543210

[131] 表2 [131] Table 2

[132] 表3表示饱和带符号双字压缩操作的寄存器内表示。 [132] Table 3 shows the saturation within DOUBLE SIGNED register indicates the compression operation.

[133] Source1 00101010 01010101 01010101 11111111 10000000 01110000 10001111 10001000 [133] Source1 00101010 01010101 01010101 11111111 10000000 01110000 10001111 10001000

[134] 1 0 [134] 10

[135] Source2 00000000 00000000 11000000 000000001110011 00000000 10001110 10001000 [135] Source2 00000000 00000000 11000000 000000001110011 00000000 10001110 10001000

[136] 1 0 [136] 10

[137] Result11000000 00000000 10000000 00000000 01111111 11111111 10000000 00000000 [137] Result11000000 00000000 10000000 00000000 01111111 11111111 10000000 00000000

[138] 3 2 1 0表3 [138] 3210 Table 3

[139] 压缩电路 [139] compression circuit

[140] 在本发明的一个实施例中,为有效地执行压缩操作,使用并行方法。 [140] In one embodiment of the present invention, the compression operation is performed efficiently, using the parallel approach. 图8a和图8b表示能够对压缩数据执行压缩操作的一个电路的实施例。 Figure 8a and Figure 8b shows a circuit capable of performing the compression operation of the embodiment of the compressed data. 该电路可选执行饱和压缩操作。 The circuit Optional perform saturation compression operation.

[141] 图8a和图8b的电路包括操作控制电路800,结果寄存器852,结果寄存器853,8个16位到8位的饱和测试电路,和4个32位到16位的饱和测试电路。 Circuit [141] Figures 8a and 8b, the control circuit 800 includes an operation result register 852, a result register 853,8 16-8 saturation test circuit, and 4 32-16 saturation test circuit.

[142] 操作控制电路800从解码器202接收信息以允许压缩操作。 [142] operation control circuit 800 receives information from the decoder 202 to allow for the compression operation. 操作控制电路800使用饱和值允许对每一饱和测试电路进行饱和测试。 Operation control circuit 800 allows the use of saturation values for each test circuit saturation saturation test. 如果源压缩数据的大小为字压缩数据503,则输出许可信号831由操作控制电路800置位。 If the source data is compressed size of the compressed data word 503, the output enable signal 831 by the operation control circuit 800 is set. 这就允许输出寄存器852输出。 This allows the output register 852 outputs. 如果源压缩数据的大小是双字压缩数据504,则输出许可信号832由操作控制电路800置位。 If the size of the source of the compressed data is compressed data double word 504, then the output enable signal 832 by the operation control circuit 800 is set. 这就允许输出寄存器853输出。 This allows the output register 853 outputs.

[143] 每一饱和测试电路可以选择测试饱和。 [143] can be selected for each test circuit saturation test saturation. 如果饱和测试被禁止,则每一饱和测试电路仅仅把低阶位传送给一个结果寄存器的相应位置。 If the saturation test is disabled, each saturation test circuit only transmits a result of lower order bits to the corresponding location register. 如果饱和测试被许可,则每一饱和测试电路测试高阶位以判定是否应该对结果箝位。 If the saturation test is permitted, then each test circuit saturation test to determine whether the high-order bits of the results should be clamped.

[144] 饱和测试810到饱和测试817有16位输入和8位输出。 [144] saturation saturation test test 810 to 817 has 16 inputs and 8 outputs. 8位输出是输入的低8位,或可选为一个箝位值(080,07F,或0FF)。 8 output is low input 8, or optionally a clamp value (0 80,0 7F, or 0 FF). 饱和测试810接收Source1位15到0而为结果寄存器852输出位7到0。 Saturation test 810 receives Source1 bits 15-0 and 852 output bits result register 7-0. 饱和测试811接收Source1位31到16而为结果寄存器852输出位15到8。 Saturation test 811 receiving Source1 31-16 and 852-bit output bit result register 15-8. 饱和测试812接收Source1位47到32而为结果寄存器852输出位23到16。 Saturation test 812 receiving Source1 bits 47-32 and 852 output bits result register 23-16. 饱和测试813接收Source1位63到48而为结果寄存器852输出位31到24。 Saturation test 813 receiving Source1 63-48 and 852-bit output bit is the result register 31-24. 饱和测试814接收Source2位15到0而为结果寄存器852输出位39到32。 814 receive Source2 saturation test 15-0 and 852-bit output bit is the result registers 39-32. 饱和测试815接收Source2位31到16而为结果寄存器852输出位47到40。 Saturation test 815 receiving Source2 31-16 and 852-bit output bit is the result registers 47-40. 饱和测试816接收Source2位47到32而为结果寄存器852输出位55到48。 Saturation test 816 receiving Source2 47-32 and 852-bit output bit is the result registers 55-48. 饱和测试817接收Source2位63到48而为结果寄存器852输出位63到56。 817 receive Source2 bit saturation test 63-48 and the result register 852 output bits 63-56.

[145] 饱和测试820到823有32位输入和16位输出。 [145] saturation test 820-823 has 32 inputs and 16 outputs. 16位输出是输入的低16位,或可选为一个箝位值(08000,07FFF,或0FFFF)。 16 output is the input of the low 16, or alternatively as a clamp value (0 8000,0 7FFF, or 0 FFFF). 饱和测试820接收Source1位31到0而为结果寄存器853输出位15到0。 Saturation test 820 receives Source1 bits 31-0 and 853 output bits result register 15-0. 饱和测试821接收Source1位63到32而为结果寄存器853输出位31到16。 Saturation test 821 receiving Source1 bits 63-32 and 853 output bits result register 31-16. 饱和测试822接收Source2位31到0而为结果寄存器853输出位47到32。 Saturation test 822 receives Source2 31-0 and 853-bit output bit result register 47-32. 饱和测试823接收Source2位63到32而为结果寄存器853输出位63到48。 Saturation test 823 receiving Source2 63-32 and 853-bit output bit is the result registers 63-48.

[146] 例如在表4中,执行无符号不饱和字压缩操作。 [146] For example, in Table 4, the implementation of an unsigned word unsaturated compression operation. 操作控制电路800许可结果寄存器852输出结果[63:0]860。 800 licensed result register operation control circuit 852 outputs [63: 0] 860.

[147] Source1…… 00001110 0111000000001110 00001000 3 2 0 [147] Source1 ...... 00001110 0111000000001110 00001000 3 2 0

[148] 1 [148] 1

[149] Source2 00001110 1000000100001110 10000001 [149] Source2 00001110 1000000100001110 10000001

[150] 3 2 0 [150] 320

[151] 1 [151] 1

[152] Rcsult…… 10000001 10000001…… 01110000 00001000 7 6 5 4 3 2 1 0 [152] Rcsult ...... 10000001 10000001 ...... 01110000 00001000 7 6 5 4 3 2 1 0

[153] 表4 [153] Table 4

[154] 然而,如果执行无符号不饱和双字压缩操作,则操作控制电路800许可结果寄存器853输出结果[63:0]860。 [154] However, if the implementation of unsigned doubleword unsaturated compression operation, the operation control circuit 800 License result register 853 output [63: 0] 860. 表5表示这一结果。 Table 5 shows the results.

[155] Source1…… 00001110 0100000100001110 00001000 [155] Source1 ...... 00001110 0100000100001110 00001000

[156] 1 0 [156] 10

[157] Source2…… 00001110 00000001 00001110 10000001 [157] Source2 ...... 00001110 00000001 00001110 10000001

[158] 1 0 [158] 10

[159] Result…00001110 10000001… 00001110 00001000 [159] Result ... 00001110 10000001 ... 00001110 00001000

[160] 3 2 0 [160] 320

[161] 表5 [161] Table 5

[162] 拆开操作 [162] open operation

[163] 在一个实施例中,拆开操作交错放置两个源压缩数据的低阶压缩字节、字或者双字以产生结果压缩字节、字或者双字。 [163] In one embodiment, the open source operating interleaved with two low-order compression of compressed data byte, word, or double word to produce a result packed byte, word, or double word.

[164] 图9表示对压缩数据执行拆开操作的方法的实施例。 [164] Figure 9 shows a method for compressing data of the operation performed disassembled embodiment. 该实施例可以在图2中的处理器109中实现。 This embodiment may be processor 109 in Figure 2 is implemented.

[165] 首先执行步骤701和702。 [165] First steps 701 and 702. 在步骤903,解码器202许可功能单元203执行拆开操作。 In step 903, the decoder 202 permit functional unit 203 to perform open operations. 解码器202通过内部总线205传输Source1和Source2中的数据元素的大小。 Decoder 202 via the internal bus 205 size Source1 and Source2 transmission of data elements.

[166] 在步骤910,数据元素的大小决定下一步执行哪一步骤。 [166] In step 910, the size of the data elements which decide on the next steps to perform. 如果数据元素的大小为8位(压缩字节数据501),则功能单元203执行步骤912。 If the size of the data element is 8 bits (byte compressed data 501), then the function unit 203 to step 912. 然而,如果压缩数据中的数据元素的大小为16位(压缩字数据502),则功能单元203执行步骤914。 However, if the size of the compressed data is 16-bit data elements (packed word data 502), then the function unit 203 to step 914. 然而,如果压缩数据中的数据元素的大小为32位(压缩双字数据503),则功能单元203执行步骤716。 However, if the size of the compressed data of the data elements is 32 (packed doubleword data 503), then the function unit 203 to step 716.

[167] 假定源数据元素的大小为8位,则执行步骤912。 Size [167] assumed that the source data element is 8, step 912. 在步骤912,执行下面的内容:Source1位7到0为Result位7到0。 In step 912, the implementation of the contents of the following: Source1 bits 7-0 to 7-0 Result bit. Source2位7到0为Result位15到8。 Source2 bits 7-0 for Result bits 15-8. Source1位15到8为Result位23到16。 Source1 bits 15-8 for Result bits 23-16. Source2位15到8为Result位31到24。 Source2 bits 15-8 for Result bits 31-24. Source1位23到16为Result位39到32。 Source1 bits 23-16 for Result bits 39-32. Source2位23到16为Result位47到40。 Source2 bits 23-16 for Result bits 47-40. Source1位31到24为Result位55到48。 Source1 bits 31-24 for Result bits 55-48. Source2位31到24为Result位63到56。 Source2 bits 31-24 for Result bits 63-56.

[168] 假定源数据元素的大小为16位,则执行步骤914。 [168] assumed that the size of the source data element is 16, step 914. 在步骤914,执行下面的内容:Source1位15到0为Result位15到0。 In step 914, the implementation of the contents of the following: Source1 bits 15-0 to 15-0 Result bit. Source2位15到0为Result位31到16。 Source2 bits 15-0 for Result bits 31-16. Source1位31到16为Result位47到32。 Source1 bits 31-16 for Result bits 47-32. Source2位31到16为Result位63到48。 Source2 bits 31-16 for Result bits 63-48.

[169] 假定源数据元素的大小为32位,则执行步骤916。 Size [169] assumed that the source data elements for 32, step 916. 在步骤916,执行下面的内容:Source1位31到0为Result位31到0。 In step 916, the implementation of the contents of the following: Source1 bits 31-0 to 31-0 Result bit. Source2位31到0为Result位63到32。 Source2 bits 31-0 for Result bits 63-32.

[170] 在一个实施例中,步骤912的拆开操作同时执行。 [170] In one embodiment, step 912 is performed simultaneously open operation. 然而,在另一个实施例中,拆开操作顺序执行。 However, in another embodiment, the sequence of operations performed to open. 在再一个实施例中,拆开操作的一部分同时执行,另一部分顺序执行。 In a further embodiment, the open operation is performed while a part, the other part of the order of execution. 这一讨论也适用于在步骤914和步骤916的拆开操作。 This discussion also applies to the operation of step 914 and step 916 apart.

[171] 在步骤720,Result存储在DEST605寄存器中。 [171] Step 720, Result stored in DEST605 register.

[172] 表6示出字节拆开操作的寄存器内表示。 Expressed in the [172] Table 6 shows the operation of open-byte register.

[173] Source1 00101010 01010101 01010101 11111111 10000000 0111000010001111 10001000 [173] Source1 00101010 01010101 01010101 11111111 10000000 0111000010001111 10001000

[174] 7 6 5 4 3 2 1 0 [174] 76543210

[175] Source2 00000000 00000000 11000000 00000000 11110011 00000000 10001110 10001000 [175] Source2 00000000 00000000 11000000 00000000 11110011 00000000 10001110 10001000

[176] 7 6 5 4 3 2 1 0 [176] 76543210

[177] Result11110011 10000000 00000000 01110000 10001110 10001111 10001000 10001000 [177] Result11110011 10000000 00000000 01110000 10001110 10001111 10001000 10001000

[178] 7 6 5 4 3 2 1 0 [178] 76543210

[179] 表6表7示出字拆开操作的寄存器内表示。 Expressed in the [179] Table 6 Table 7 shows the operation of the register word apart.

[180] Source1 00101010 01010101 01010101 11111111 10000000 01110000 10001111 10001000 [180] Source1 00101010 01010101 01010101 11111111 10000000 01110000 10001111 10001000

[181] 3 2 0 [181] 320

[182] 1 [182] 1

[183] Source200000000 0000000011000000 00000000 11110011 0000000010001110 10001000 [183] Source200000000 0000000011000000 00000000 11110011 0000000010001110 10001000

[184] 3 2 0 [184] 320

[185] 1 [185] 1

[186] Result11110011 0000000010000000 01110000 10001110 10001000 10001111 10001000 [186] Result11110011 0000000010000000 01110000 10001110 10001000 10001111 10001000

[187] 3 2 0 [187] 320

[188] 1 [188] 1

[189] 表7表8示出双字拆开操作的寄存器内表示。 [189] Table 7 Table 8 shows the double-word register indicates open operation.

[190] Source1 00101010 01010101 01010101 11111111 10000000 01110000 10001111 10001000 [190] Source1 00101010 01010101 01010101 11111111 10000000 01110000 10001111 10001000

[191] 1 0 [191] 10

[192] Source2 00000000 00000000 11000000 0000000011110011 00000000 10001110 10001000 [192] Source2 00000000 00000000 11000000 0000000011110011 00000000 10001110 10001000

[193] 1 0 [193] 10

[194] Result 11110011 00000000 10001110 10001000 10000000 01110000 10001111 10001000 [194] Result 11110011 00000000 10001110 10001000 10000000 01110000 10001111 10001000

[195] 1 0表8 [195] 10 Table 8

[196] 拆开电路 [196] open circuit

[197] 在本发明的一个实施例中,为有效地执行拆开操作,使用并行方法。 [197] In one embodiment of the present invention, the open operation is performed efficiently, using the parallel approach. 图10表示能够对压缩数据执行拆开操作的一个电路的实施例。 Figure 10 shows an embodiment of the compressed data can perform an operation to open the circuit.

[198] 图10的电路包括操作控制电路800,结果寄存器1052,结果寄存器1053和结果寄存器1054。 Circuit [198] Figure 10 includes an operation control circuit 800, a result register 1052, register 1053 and the results of the result register 1054.

[199] 操作控制电路800从解码器202接收信息而许可拆开操作。 [199] operation control circuit 800 receives information from the decoder 202 and permit disassembly operation. 如果源压缩数据的大小是字节压缩数据502,则由操作控制电路800置位输出许可信号1032。 If the source of compressed data size is 502 bytes of compressed data, by the operation of the control circuit 800 sets the output enable signal 1032. 这就允许结果寄存器1052输出。 This allows the results of 1052 the output register. 如果源压缩数据的大小为字压缩数据503,则输出许可信号1033由操作控制电路800置位。 If the source data is compressed size of the compressed data word 503, the output enable signal 1033 by the operation control circuit 800 is set. 这就允许输出寄存器1053输出。 This allows the output register 1053 output. 如果源压缩数据的大小是双字压缩数据504,则输出许可信号1034由操作控制电路800置位。 If the size of the source of the compressed data is compressed data double word 504, then the output enable signal 1034 by the operation control circuit 800 is set. 这就允许输出结果寄存器1054输出。 This allows the output register 1054 output.

[200] 结果寄存器1052有下列输入。 [200] The results of the following input register 1052. Source1位7到0为结果寄存器1052的位7到0。 Source1 bits 7-0 1052 as the result register bits 7-0. Source2位7到0为结果寄存器1052的位15到8。 Source2 bits 7-0 for the 1052-bit result register 15-8. Source1位15到8为结果寄存器1052的位23到16。 Source1 bits 15-8 for bit result register 1052 23-16. Source2位15到8为结果寄存器1052的位31到24。 Source2 bits 15-8 1052 as the result register bits 31-24.

[201] Source1位23到16为结果寄存器1052的位39到32。 [201] Source1 bits 23-16 1052 as the result register bits 39-32. Source2位23到16为结果寄存器1052的位47到40。 Source2 bits 23-16 1052 as the result register bits 47-40. Source1位31到24为结果寄存器1052的位55到48。 Source1 bits 31-24 1052 as the result register bits 55-48. Source2位31到24为结果寄存器1052的位63到56。 Source2 bits 31-24 1052 as the result register bits 63-56.

[202] 结果寄存器1053有下列输入。 [202] The results of the following input register 1053. Source1位15到0为结果寄存器1053的位15到0。 Source1 bits 15-0 1053 as the result register bits 15-0. Source2位15到0为结果寄存器1053的位31到16。 Source2 bits 15-0 1053 as the result register bits 31-16. Source1位31到16为结果寄存器1053的位47到32。 Source1 bits 31-16 bits 47-32 result register 1053. Source2位31到16为结果寄存器1053的位63到48。 Source2 bits 31-16 bits 63-48 result register 1053.

[203] 结果寄存器1054有下列输入。 [203] The results of the following input register 1054. Source1位31到0为结果寄存器1054的位31到0。 Source1 bits 31-0 for the 1054-bit result register 31-0. Source2位31到0为结果寄存器1054的位63到32。 Source2 bits 31-0 for bits 63-32 result register 1054.

[204] 例如,在表9中,执行一个字拆开操作。 [204] For example, in Table 9, the implementation of a word open operation. 操作控制电路800将允许结果寄存器1053输出结果[63:0]860。 The operation control circuit 800 will allow the register 1053 outputs the result [63: 0] 860.

[205] 表9 [205] Table 9

[206] Source1…… 00001110 01110000 00001110 00001000 [206] Source1 ...... 00001110 01110000 00001110 00001000

[207] 3 2 0 [207] 320

[208] 1 [208] 1

[209] Source2…… 00001110 00000001 00001110 10000001 [209] Source2 ...... 00001110 00000001 00001110 10000001

[210] 3 2 0 [210] 320

[211] 1 [211] 1

[212] Rcsult00001110 00000001 00001110 01110000 00001110 10000001 00001110 00001000 [212] Rcsult00001110 00000001 00001110 01110000 00001110 10000001 00001110 00001000

[213] 3 2 0 [213] 320

[214] 1 [214] 1

[215] 然而,如果执行双字拆开操作,则操作控制电路800将允许结果寄存器1054输出结果[63:0]860。 [215] However, if you perform a double word open operation, the operation control circuit 800 will allow the results of register 1054 output [63: 0] 860. 表10表示这一结果。 Table 10 shows the results.

[216] Source1 …00001110 01000001 00001110 00001000 [216] Source1 ... 00001110 01000001 00001110 00001000

[217] 1 0 [217] 10

[218] Source2… 00001110 00000001 00001110 10000001 [218] Source2 ... 00001110 00000001 00001110 10000001

[219] 1 0 [219] 10

[220] Result00001110 00000001 00001110 10000001 00001110 01000001 00001110 00001000 [220] Result00001110 00000001 00001110 10000001 00001110 01000001 00001110 00001000

[221] 1 0 [221] 10

[222] 表10 [222] Table 10

[223] 因此,移动、压缩和拆开操作可以操作多个数据元素。 [223] Accordingly, move, compress and open operations may operate on multiple data elements. 在现有技术的处理器中,为执行这些类型的操作,需要多个单独的操作来执行单一压缩数据移动、压缩或者拆开操作。 In prior art processors, to perform these types of operations, a plurality of separate operations required to perform a single compressed data move, compress or open operation. 在一个实施例中,用于压缩数据操作的数据线都带有相关的数据。 In one embodiment, the operations for compressing the data associated with the data lines of data. 它将提高计算机系统的性能。 It will improve the performance of computer systems.

Classifications
International ClassificationG06F9/30, G06F9/315, G06F9/302, G06F9/318
Cooperative ClassificationG06F9/30192, G06F9/30145, G06F9/30036, G06F7/49921, G06F9/30025, G06F9/30109, G06F9/30167, G06F9/3013, G06F9/30181, G06F9/30032, G06F9/30196, G06F9/30149
European ClassificationG06F9/30A1A1, G06F9/30X, G06F9/30A1F, G06F9/30T4T, G06F9/30A1M, G06F9/30A1P, G06F9/30R4A, G06F9/30R5D
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