CN107112354A - 包括超晶格和替换金属栅极结构的半导体装置和相关方法 - Google Patents

包括超晶格和替换金属栅极结构的半导体装置和相关方法 Download PDF

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CN107112354A
CN107112354A CN201580071385.3A CN201580071385A CN107112354A CN 107112354 A CN107112354 A CN 107112354A CN 201580071385 A CN201580071385 A CN 201580071385A CN 107112354 A CN107112354 A CN 107112354A
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substrate
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CN107112354B (zh
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R·J·梅尔斯
刘金储宰
武内英树
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Atomera Inc
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Abstract

一种半导体装置可以包括：在其中具有沟道凹陷部的衬底，在所述衬底中的多个间隔开的浅沟槽隔离(STI)区，以及在所述衬底中间隔开并在一对STI区之间的源极和漏极区。超晶格沟道在所述衬底的沟道凹陷部中并在源极和漏极区之间延伸，所述超晶格沟道包括多个堆叠的层组，并且所述超晶格沟道的每个层组包括限定基础半导体部分的堆叠的基础半导体单层和约束在相邻的基础半导体部分的晶格内的至少一个非半导体单层。替换栅极可以在超晶格沟道之上。

Description

包括超晶格和替换金属栅极结构的半导体装置和相关方法
相关申请
本申请基于2014年11月25日提交的在先提交的临时申请序列No.62/083,994和2015年11月23日提交的专利申请序列No.14/948,547；这些申请的公开内容通过引用整体地并入本文中。
技术领域
本申请涉及半导体领域，并且更具体地，涉及包含超晶格的半导体装置和相关方法。
背景技术
已经提出了结构和技术来增强半导体装置的性能，比如通过增强电荷载流子的迁移率来增强半导体装置的性能。例如，Currie等人的美国专利申请No.2003/0057416公开了硅的应变材料层、硅-锗以及松弛硅并且还包括无杂质区域(否则将会引起性能退化)。上部硅层中产生的双轴应变改变载流子迁移率，从而允许较高速和/或较低功耗装置。Fitzgerald等人的已公布的美国专利申请No.2003/0034529公开了同样基于类似应变硅技术的CMOS反相器。
Takagi的美国专利No.6,472,685B2公开了一种半导体装置，该半导体装置包括夹于硅层间的硅碳层，以使得第二硅层的导带和价带受到拉伸应变。具有较小的有效质量并且已被施加到栅极电极的电场感应的电子被限制在第二硅层中，因此，可以肯定n沟道MOSFET具有更高的迁移率。
Ishibashi等人的美国专利No.4,937,204公开了一种超晶格，其中多层(少于8个单层，且包含部分或双金属半导体层或二元化合物半导体层)交替地并且外延地生长。主电流流动方向垂直于超晶格层。
Wang等人的美国专利No.5,357,119公开了具有通过减少超晶格中的合金散射获得的较高迁移率的硅-锗短周期超晶格。按照这些原则，Candelaria的美国专利No.5,683,934公开了包括沟道层的增强迁移率MOSFET，该沟道层包含硅和在硅晶格中以一定比例替代性出现的第二材料的合金，这将沟道层置于拉伸应力下。
Tsu的美国专利No.5,216,262公开了包括两个势垒区和夹于势垒之间的薄外延生长的半导体层的量子阱结构。每个势垒区包括厚度通常在2到6个单层范围内的交替的SiO2/Si层。硅的更厚部分夹于势垒之间。
同样Tsu于2000年9月6日在Appllied Physics and Materials Science&Processing的第391-402页在线发表的题目为“Phenomena in silicon nanostructuredevices”的文章公开了硅和氧的半导体-原子超晶格(SAS)。Si/O超晶格被公开为在硅量子以及发光装置中是有用的。具体地，构建和测试了绿色电致发光二极管结构。二极管结构中电流流动是垂直的，即垂直于SAS层。公开的SAS可以包括由吸附物(诸如氧原子、以及CO分子)分开的半导体层。在吸收的氧单层上硅的生长被描述为具有相当低缺陷密度的外延。一个SAS结构包括1.1nm厚的硅部分(即，大约8个硅原子层)以及具有两倍于此硅厚度的另一个结构。Luo等人在Physics Review Letters,Vol.89,No.7(2002年8月12日)发表的题目为“Chemical Design of Direct-Gap Light-Emitting Silicon”的文章进一步讨论了Tsu的发光SAS结构。
Wang、Tsu和Lofgren的已公开的国际申请WO 02/103,767A1公开了薄硅和氧、碳、氮、磷、锑、砷或者氢的势垒构成块，从而使垂直地流过晶格的电流降低了超过四个量级。绝缘层/势垒层允许低缺陷外延硅接着沉积到绝缘层。
Mears等人的已公开的英国专利申请2,347,520公开了非周期性光子带隙(APBG)结构的原理可能适合于电子带隙工程。具体地，该申请公开了可以设定材料参数(例如，能带极小值的位置、有效质量等等)来产生具有期望的能带结构特性的新非周期性材料。还公开了可以对材料进行设计的其它参数(诸如电导率、热导率和介电常数或者磁导率)。
尽管由这些结构提供了优势，但是用于在各种半导体装置中集成先进半导体材料的进一步的发展可能是希望的。
发明内容
一种用于制备半导体装置的方法可以包括：在衬底中形成多个间隔开的浅沟槽隔离(STI)区，在一对STI区之间的衬底上形成虚设栅极，在所述虚设栅极的相对侧并在所述一对STI区之间的衬底中形成源极和漏极区，以及在衬底上形成围绕所述虚设栅极的电介质层。该方法可以进一步包括去除所述虚设栅极和所述虚设栅极下面的衬底的部分以限定在所述源极和漏极区之间的衬底中的沟道凹陷部，以及在所述沟道凹陷部中形成包括多个堆叠的层组的超晶格沟道。所述超晶格沟道的每个层组可以包括限定基础半导体部分的多个堆叠的基础半导体单层和约束在相邻的基础半导体部分的晶格内的至少一个非半导体单层。该方法还可以包括在所述超晶格沟道之上形成替换栅极并去除所述电介质层。
更具体地，该方法可以进一步包括在所述一对STI区之间的衬底中执行阱注入。此外，形成所述替换栅极包括在所述超晶格沟道之上形成高K电介质层，并在所述高K电介质层之上形成金属栅极电极。
举例来说，每个基础半导体部分可以包含硅、锗等。还举例来说，所述至少一个非半导体单层可以包含选自包括氧、氮、氟和碳-氧的组的非半导体。
此外，所述超晶格沟道可以进一步包括在最上面的层组上的基础半导体帽层。此外，来自相对的基础半导体部分的至少一些半导体原子通过其间的所述至少一个非半导体单层被化学地束缚在一起。
一种相关的半导体装置可以包括：在其中具有沟道凹陷部的衬底，在所述衬底中的多个间隔开的浅沟槽隔离(STI)区，以及在所述衬底中间隔开并在一对STI区之间的源极和漏极区。超晶格沟道可以在所述衬底的沟道凹陷部中并在源极和漏极区之间延伸，所述超晶格沟道包括多个堆叠的层组，并且所述超晶格沟道的每个层组包括限定基础半导体部分的多个堆叠的基础半导体单层和约束在相邻的基础半导体部分的晶格内的至少一个非半导体单层。替换栅极可以在所述超晶格沟道之上。
附图说明
图1是根据本发明的用于在半导体装置中使用的超晶格的高倍放大的示意性截面图。
图2是图1中示出的超晶格的一部分的透视示意性原子图。
图3是根据本发明的超晶格的另一个实施例的高倍放大的示意性截面图。
图4A是对现有技术中的体硅和图1-2中示出的4/1Si/O超晶格两者从伽马点(G)计算的能带结构的图表。
图4B是对现有技术中的体硅和图1-2中示出的4/1Si/O超晶格两者从Z点计算的能带结构的图表。
图4C是对现有技术中的体硅和图3中示出的5/1/3/1Si/O超晶格两者从伽马点和Z点计算的能带结构的图表。
图5是根据示例实施例的包括覆在超晶格沟道层上的替换金属栅极的半导体装置的截面图。
图6-图13是例示制备图5的半导体装置的方法的一系列截面图。
图14是对应于图5-图13中例示的方法的流程图。
具体实施方式
现在将参考附图在下文中更完整地描述本发明，附图中示出了本发明的优选实施例。然而，本发明可以以多种不同形式来体现并且不应该解释为局限于本文阐述的实施例。相反，提供这些实施例以使得本公开将是透彻且完整的，并且将向本领域技术人员完整地传达本发明的范围。同样的附图标记始终指代同样的要素，并且主要符号被用来指示不同实施例中的类似要素。
本发明涉及在原子或分子层面控制半导体材料的性质。进一步地，本发明涉及用于在半导体装置中使用的改进材料的确定、创造以及使用。
申请人从理论上阐明(但不希望束缚于此)本文描述的特定超晶格降低了电荷载流子的有效质量，并且这从而导致更高的电荷载流子迁移率。在文献中，用各种定义来描述有效质量。作为有效质量的改进的测量，申请人分别针对电子和空穴使用“电导率倒数有效质量张量(conductivity reciprocal effective mass tensor)”Me -1和Mh -1，对于电子定义为：
以及对于空穴定义为：
其中f是费米狄拉克分布，EF是费米能级，T是温度，E(k，n)是电子在与波矢k和第n个能带对应的态中的能量，下标i和j指的是笛卡尔坐标系x、y、z，在布里渊区(B.Z.)进行积分，并且分别对于电子和空穴的能量在费米能级以上或以下的能带进行求和。
申请人对电导率倒数有效质量张量的定义使得材料的电导率的张量分量比电导率倒数有效质量张量的相应分量的较大值更大。再次，申请人从理论上阐明(但不希望束缚于此)本文描述的超晶格设置电导率倒数有效质量张量的值以便增强材料的导电性质(诸如一般针对电荷载流子输运的优选方向)。适当张量参数元(appropriate tensorelement)的逆也被称为电导率有效质量。换句话说，为了表征半导体材料结构，使用如上描述并在预期的载流子输运方向上计算的电子/空穴的电导率有效质量来区分改进的材料。
申请人已经确认了用于在半导体装置中使用的改进的材料或结构。更具体地，申请人已经确认了具有电子和/或空穴的适当的电导率有效质量比硅的相应值小得多的能带结构的材料或结构。除这些结构的增强的迁移率特性之外，如将会在下面进一步讨论的，还可以以它们提供压电、热电、和/或铁电的性质这样的方式来形成或使用它们，这些性质对于用在很多不同类型的装置中是有益的。
现在参照图1和图2，材料或结构以超晶格25的形式，超晶格25的结构被在原子或分子层面控制，并且可以使用已知的原子或分子层沉积的技术来形成。超晶格25包括以堆叠关系布置的多个层组45a-45n，也许具体参考图1的示意性截面图能最好理解。
超晶格25的每个层组45a-45n例示性地包括限定相应的基础半导体部分46a-46n的多个堆叠的基础半导体单层46和其上的能带修改层50。为了清晰地例示，通过图1中的点画指示能带修改层50。
能带修改层50例示性地包括约束在相邻的基础半导体部分的晶格内的一个非半导体单层。“约束在相邻的基础半导体部分的晶格内”意味着：来自相对的基础半导体部分46a-46n的至少一些半导体原子通过其间的非半导体单层50被化学地束缚在一起，如图2所示。如下面将进一步讨论的，一般来说，通过原子层沉积技术来控制沉积在半导体部分46a-46n上的非半导体材料的量以使得不是所有可用的半导体键合位点(即，小于全部或100％覆盖)被到非半导体原子的键占据，可以实现这种配置。因此，随着半导体材料的另外单层46沉积在非半导体单层50上或之上，新沉积的半导体原子将会占据在非半导体单层之下的半导体原子的其余空位键合位点。
在其它实施例中，可以是多于一个这样的非半导体单层。应该注意，在此对非半导体或半导体单层的引述意味着：用于该单层的材料以体形成则会是非半导体或半导体。也就是说，本领域技术人员将意识到，诸如硅的材料的单个单层可能并不必然展现出与它形成为体或相对厚的层的情况下的相同的性质。
申请人从理论上阐明(但不希望束缚于此)：能带修改层50和相邻的基础半导体部分46a-46n使得超晶格25在平行层的方向上对于电荷载流子具有比以其它方式出现的低的适当电导率有效质量。以另一种方式考虑，该平行方向与堆叠方向是正交的。能带修改层50还可以使得超晶格25具有常见能带结构，同时还有益地起在垂直地位于超晶格之上和之下的层或区之间的绝缘体的作用。
此外，该超晶格结构还可以有益地作为对在垂直地位于超晶格25之上和之下的层之间的掺杂剂和/或材料扩散的阻挡物。本领域技术人员将意识到，这些性质可以因此有益地允许超晶格25提供针对高K电介质的界面，该界面不仅减少高K材料扩散进入沟道区，而且还可以有益地降低不期望的散射效应并且改进装置迁移率。
还可以从理论上阐明，包括超晶格25的半导体装置基于比以其它方式存在的更低的电导率有效质量，可以享有更高的电荷载流子迁移率。在一些实施例中，作为由本发明获得的能带工程的结果，超晶格25可以进一步具有基本上直接带隙，这例如对光电装置尤其有益。
超晶格25还例示性地包括在上部层组45n上的帽层52。该帽层52可以包含多个基础半导体单层46。帽层52可以具有2到100个基础半导体的单层，并且，更优选地具有10到50个单层。
每个基础半导体部分46a-46n可以包含选自包括IV族半导体、III-V族半导体以及II-VI族半导体的组的基础半导体。当然，本领域技术人员将意识到，术语“IV族半导体”还包括IV-IV族半导体。更具体地，例如，基础半导体可以包括硅和锗中的至少一种。
例如，每个能带修改层50可以包含选自包括氧、氮、氟、碳和碳-氧的组的非半导体。该非半导体通过下一层的沉积仍然是合乎期望地热稳定的，从而促进制造。在其它实施例中，非半导体可以是与给定半导体工艺相兼容的另外的无机或有机的元素或化合物，如本领域技术人员将意识到的。更具体地，例如，基础半导体可以包含硅和锗中的至少一种。
应该注意的是，术语“单层”意在包括单原子层以及单分子层。还需注意的是，由单个单层提供的能带修改层50也意在包括其中不是所有可能的位点都被占据(即，少于全部或100％覆盖)的单层。例如，特别参考图2的原子图示，例示了用于硅作为基础半导体材料和氧作为能带修改材料的4/1重复结构。在例示的示例中，用于氧的可能位点只有一半被占据。
在其它实施例和/或以不同的材料，这种一半占据将不一定会是本领域技术人员将会意识到的情况。事实上，甚至在这个示意图中也可以看到，给定单层中的个别氧原子并没有如原子沉积领域的普通技术人员将意识到的那样精确地沿着平面对齐。举例来说，优选的占据范围是从可能的氧位点被占满的大约八分之一到一半，尽管在其它特定实施例中可以使用其它数字。
当前在传统半导体工艺中广泛使用硅和氧，并且因此，制造商们很容易能够使用本文描述的这些材料。原子或单层沉积现在同样被广泛使用。因此，本领域技术人员将意识到，根据本发明的包含超晶格25的半导体装置可以非常容易被采纳和实施。
申请人从理论上阐明(但不希望被束缚于此)，对于超晶格(诸如Si/O超晶格)，例如，硅单层的数量理想地应该是7或者更小以便超晶格的能带始终是一致或者相对均匀的，以获得期望的优点。图1和图2中示出的Si/O的4/1重复结构已经被模型化来指示电子和空穴在X方向的增强的迁移率。例如，电子的计算的电导率有效质量(对于体硅，各向同性)是0.26，且对于4/1Si/O超晶格它在X方向上是0.12，得到了0.46的比率。类似地，对于空穴的计算，对体硅产生了0.36的值以及对4/1Si/O超晶格产生0.16的值，得到了0.44的比率。
尽管这种方向性优选特征在某些半导体装置中可能是期望的，但是其它装置可能得益于在任何平行于层组的方向上的迁移率更加均匀地增加。本领域技术人员将意识到，具有对于电子或空穴两者或者仅仅这些类型的电荷载流子的一种的迁移率的增大也可以是有益的。
对于超晶格25的4/1Si/O实施例的较低电导率有效质量可以比以其它方式发生的电导率有效质量的2/3小，并且这适用于电子和空穴两者。当然，本领域技术人员将意识到，超晶格25可以进一步包含至少一种类型的导电性掺杂剂。
事实上，现在附加地参考图3，现在描述根据本发明的具有不同性质的超晶格25’的另一个实施例。在这个实施例中，例示了3/1/5/1的重复模式。更具体地，最低的基础半导体部分46a’具有三个单层，并且第二低的基础半导体部分46b’具有5个单层。在超晶格25’中始终以这个模式重复。能带修改层50’各自可以包括单个单层。对于这样的包括Si/O的超晶格25’，电荷载流子迁移率的增强独立于在层平面的取向。图3中未特别提到的那些其它项与以上参照图1讨论的项类似，并且不需要在此进一步的讨论。
在一些装置实施例中，超晶格的所有基础半导体部分可以是相同数量的单层那样厚。在其它实施例中，至少一些基础半导体部分可以是不同数量的单层那样厚。在另外的其它实施例中，所有的基础半导体部分可以是不同数量的单层那样厚。
在图4A-图4C中，呈现了使用密度泛函理论(DFT)计算的能带结构。在本领域众所周知，DFT低估了带隙的绝对值。因此带隙之上的所有能带可以被移动适当的“剪刀修正(scissors correction)”。然而，已知能带的形状是可靠得多的。应该考虑此来解释垂直能量轴。
图4A示出了对体硅(由连续线表示)和图1示出的4/1Si/O超晶格25(由虚线表示)从伽马点(G)计算的能带结构。各方向涉及4/1Si/O结构的单元晶胞而不是传统的硅晶胞，尽管图中的(001)方向确实对应于传统硅单元晶胞的(001)方向，并因此，示出了硅导带最小值的期望位置。图中的(100)和(010)方向对应于传统硅单元晶胞的(110)和(-110)方向。本领域技术人员将会意识到，图中硅的能带被折叠以将它们表示在4/1Si/O结构的适当倒格子方向上。
可以看到，4/1Si/O结构的导带最小值位于的伽马点处，与体硅(Si)形成对照，而价带最小值发生在(001)方向上布里渊区的边缘(我们称之为Z点)处。还应该注意到，相比于硅导带最小值的曲率，4/1Si/O结构的导带最小值的曲率更大，这是因为由附加的氧层引入的扰动导致的能带分裂。
图4B示出了对体硅(连续线)和4/1Si/O超晶格25(虚线)两者从Z点计算的能带结构。这个图例示了(100)方向上价带的增强的曲率。
图4C示出了对体硅(连续线)和图3的超晶格25’的5/1/3/1Si/O结构(虚线)两者从伽马点和Z点计算的能带结构。由于5/1/3/1Si/O结构的对称性，在(100)和(010)方向计算的能带结构是等价的。因此，预期电导率有效质量和迁移率在平行于层的平面(即，垂直于(001)堆叠方向)中是各向同性的。注意，在5/1/3/1Si/O示例中，导带最小值和价带最大值两者都在Z点处或者靠近Z点。
尽管增大的曲率是降低的有效质量的指示，但是也可以通过电导率倒数有效质量张量的计算来取得合适的对比和区别。这使得申请人进一步从理论上阐明：5/1/3/1超晶格25’应该大体上是直接带隙的。本领域技术人员将会理解，光跃迁的合适的矩阵元是直接和非直接带隙行为之间差别的另一个指示。
使用上述手段，可以为特定的目的选择具有改进的能带结构的材料。如图5所示，一个这样的示例是半导体装置100中的超晶格材料层125，在半导体装置100中超晶格材料定位在替换栅极105下面的沟道凹陷部104中。当在半导体装置100的沟道区中利用时，上述超晶格材料层125的量子限制性质可以提供显著的优点，诸如偏置温度不稳定性(BTI)可靠性的改进和载流子迁移率提升(以及相应的NMOS性能的改进)以及提供“后沟道”集成选择，“后沟道”集成选择意味着沟道在形成源极/漏极和虚设栅极之后形成，如以下将进一步讨论的。此外，还如上所述的，超晶格材料还可以帮助减小沟道区中的泄露。
在例示的示例中，半导体装置100是平面MOSFET装置，其可以用于例如NMOS、PMOS或CMOS装置中。然而，应当注意，图5所示的超晶格/栅极结构也可以用在其它配置中，诸如垂直装置(例如，FINFET等)中。半导体装置100例示性地包括硅衬底106、在衬底中间隔开的源极和漏极区107、108以及在衬底的沟道凹陷部104中定位在源极和漏极区之间的超晶格材料层125。如本领域技术人员将意识到的，可以包括浅沟槽隔离(STI)区109以将源极和漏极区107、108与衬底106上的其它装置隔离。在例示的示例中，栅极105是包括金属栅极电极110和高K电介质层111的高K替换金属栅极，并且如示出的横向地在源极和漏极区107、108之间、定位在超晶格沟道层125之上。装置100的沟道可以完全地或部分地限定在超晶格沟道层125内，或者在一些实施例中，它还可以在超晶格沟道层下面延伸。
现将参考图6-图14描述用于制备半导体装置100的示例方法。可以在块201-块202执行STI和阱模块制备以形成起始衬底或晶片(图6)，如本领域技术人员将意识到的。然后可以在块203(图6)处在衬底106上形成“虚设栅极”113，“虚设栅极”113覆在将变成沟道区的位置上。更具体地，虚设栅极113形成可以包括在衬底106和STI区109(图7)之上形成毯状多晶硅半导体层112(例如，多晶硅)，然后图案化多晶硅层以限定虚设栅极(图8)。然后在块204(图9)处，虚设栅极113可以用于对准源极和漏极107、108注入。
可以将电介质层114(例如，SiO2)形成为覆在源极和漏极区107、108以及STI区109上并围绕虚设栅极113，如图10所示。然后可以去除虚设栅极113(块205)以由替换金属栅极105取代。此外，蚀刻虚设栅极113可以向下延伸到衬底106中以产生沟道凹陷部104，如图11所示。然后在块206处，如图12所示，可以使用上述技术和配置在沟道凹陷部104中形成超晶格层125。然后如本领域技术人员将意识到的，如图13所示(块207)，可以通过沉积高K电介质层111和金属栅极电极110形成替换金属栅极105。然后如本领域技术人员将意识到的，可以针对给定的装置类型适当地执行进一步的半导体装置处理。例如，可以去除电介质层114，并可以形成相应的源极/漏极触件127、128，例如如图5所示。
上述金属栅极实现可以相应地不仅提供上述BTI可靠性改进和载流子迁移率提升的优点，还可以提供在栅极形成和沟道集成方面的集成灵活性。如上所述，超晶格沟道层125可以有利地在源极和漏极107、108形成之后形成，这可能在超晶格沟道层不经历与源极/漏极形成和虚设栅极113处理相关的各种处理步骤方面是期望的。此外，上述步骤可以重新排序以提供“前栅极”选择，而不是以上阐述的示例性“后栅极”方式。这种处理灵活性可能例如对于32nm节点或以下的CMOS实现是有利的，但是本文描述的配置也可以与其它装置尺寸一起使用。
得益于前面描述和相关附图呈现的教导，本领域技术人员会想到多种修改和其它实施例。因此，应该理解，本发明不限制于所公开的具体实施例，并且意图将那些修改和实施例包括在本公开和以下权利要求的范围内。

Claims (22)

1.一种用于制备半导体装置的方法，所述方法包括：
在衬底中形成多个间隔开的浅沟槽隔离STI区；
在一对STI区之间的衬底上形成虚设栅极；
在所述虚设栅极的相对侧并在所述一对STI区之间的衬底中形成源极和漏极区；
在所述衬底上形成围绕所述虚设栅极的电介质层；
去除所述虚设栅极和所述虚设栅极下面的衬底的部分以限定在所述源极和漏极区之间的衬底中的沟道凹陷部；
在所述沟道凹陷部中形成包括多个堆叠的层组的超晶格沟道，所述超晶格沟道的每个层组包括限定基础半导体部分的多个堆叠的基础半导体单层和约束在相邻的基础半导体部分的晶格内的至少一个非半导体单层；以及
在所述超晶格沟道之上形成替换栅极并去除所述电介质层。
2.根据权利要求1所述的方法，进一步包括在所述一对STI区之间的衬底中执行阱注入。
3.根据权利要求1所述的方法，其中形成所述替换栅极包括在所述超晶格沟道之上形成高K电介质层，并在所述高K电介质层之上形成金属栅极电极。
4.根据权利要求1所述的方法，其中每个基础半导体部分包含硅。
5.根据权利要求1所述的方法，其中每个基础半导体部分包含锗。
6.根据权利要求1所述的方法，其中所述至少一个非半导体层包含氧。
7.根据权利要求1所述的方法，其中所述至少一个非半导体单层包含选自包括氧、氮、氟和碳-氧的组的非半导体。
8.根据权利要求1所述的方法，其中所述超晶格沟道进一步包括在最上面的层组上的基础半导体帽层。
9.根据权利要求1所述的方法，其中来自相对的基础半导体部分的至少一些半导体原子通过其间的所述至少一个非半导体单层被化学地束缚在一起。
10.一种半导体装置，包括：
在其中具有沟道凹陷部的衬底，
在所述衬底中的多个间隔开的浅沟槽隔离STI区；
在所述衬底中间隔开并在一对STI区之间的源极和漏极区；以及
超晶格沟道，在所述衬底的沟道凹陷部中并在所述源极和漏极区之间延伸，所述超晶格沟道包括多个堆叠的层组，所述超晶格沟道的每个层组包括限定基础半导体部分的多个堆叠的基础半导体单层和约束在相邻的基础半导体部分的晶格内的至少一个非半导体单层；以及
在所述超晶格沟道之上的替换栅极。
11.根据权利要求10所述的半导体装置，进一步包括在所述一对STI区之间的衬底中的阱注入。
12.根据权利要求10所述的半导体装置，其中所述替换栅极包括：
在所述超晶格沟道之上的高K电介质层；和
在所述高K电介质层之上的金属栅极电极。
13.根据权利要求10所述的半导体装置，其中每个基础半导体部分包含硅。
14.根据权利要求10所述的半导体装置，其中每个基础半导体部分包含锗。
15.根据权利要求10所述的半导体装置，其中所述至少一个非半导体层包含氧。
16.根据权利要求10所述的半导体装置，其中所述至少一个非半导体单层包含选自包括氧、氮、氟和碳-氧的组的非半导体。
17.根据权利要求10所述的半导体装置，其中所述超晶格沟道进一步包括在最上面的层组上的基础半导体帽层。
18.根据权利要求10所述的半导体装置，其中来自相对的基础半导体部分的至少一些半导体原子通过其间的所述至少一个非半导单层被化学地束缚在一起。
19.一种半导体装置，包括：
在其中具有沟道凹陷部的衬底；
在所述衬底中的多个间隔开的浅沟槽隔离STI区；
在所述衬底中间隔开并在一对STI区之间的源极和漏极区；
超晶格沟道，在所述衬底的沟道凹陷部中并在所述源极和漏极区之间延伸，所述超晶格沟道包括多个堆叠的层组，所述超晶格沟道的每个层组包括限定基础硅部分的多个堆叠的硅单层和约束在相邻的基础硅部分的晶格内的至少一个氧单层；以及
替换栅极，包括在所述超晶格沟道之上的高K电介质层和在所述高K电介质层之上的金属栅极电极。
20.根据权利要求19所述的半导体装置，进一步包括在所述一对STI区之间的衬底中的阱注入。
21.根据权利要求19所述的半导体装置，其中所述超晶格沟道进一步包括在最上面的层组上的基础硅帽层。
22.根据权利要求19所述的半导体装置，其中来自相对的基础硅部分的至少一些半导体原子通过其间的所述至少一个氧单层被化学地束缚在一起。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112074959A (zh) * 2018-04-12 2020-12-11 阿托梅拉公司 用于制造包括超晶格的倒t形沟道场效应晶体管(itfet)的器件和方法
CN113228300A (zh) * 2018-11-16 2021-08-06 阿托梅拉公司 包括源极和漏极区域与掺杂剂扩散阻挡超晶格层以减小接触电阻的finfet和相关方法
CN113228296A (zh) * 2018-11-16 2021-08-06 阿托梅拉公司 制造具有减小的接触电阻的finfet的方法

Families Citing this family (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9812323B2 (en) * 2014-09-08 2017-11-07 Internaitonal Business Machines Corporation Low external resistance channels in III-V semiconductor devices
US9941359B2 (en) 2015-05-15 2018-04-10 Atomera Incorporated Semiconductor devices with superlattice and punch-through stop (PTS) layers at different depths and related methods
US9721790B2 (en) 2015-06-02 2017-08-01 Atomera Incorporated Method for making enhanced semiconductor structures in single wafer processing chamber with desired uniformity control
WO2017197108A1 (en) 2016-05-11 2017-11-16 Atomera Incorporated Dram architecture to reduce row activation circuitry power and peripheral leakage and related methods
US9893070B2 (en) 2016-06-10 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and fabrication method therefor
US10249745B2 (en) 2016-08-08 2019-04-02 Atomera Incorporated Method for making a semiconductor device including a resonant tunneling diode structure having a superlattice
US10107854B2 (en) 2016-08-17 2018-10-23 Atomera Incorporated Semiconductor device including threshold voltage measurement circuitry
US11088033B2 (en) * 2016-09-08 2021-08-10 International Business Machines Corporation Low resistance source-drain contacts using high temperature silicides
CN110832641B (zh) 2017-05-16 2023-05-30 阿托梅拉公司 包括作为吸收层的超晶格的半导体装置和方法
US10636879B2 (en) 2017-06-13 2020-04-28 Atomera Incorporated Method for making DRAM with recessed channel array transistor (RCAT) including a superlattice
US10109479B1 (en) 2017-07-31 2018-10-23 Atomera Incorporated Method of making a semiconductor device with a buried insulating layer formed by annealing a superlattice
CN111247640B (zh) 2017-08-18 2023-11-03 阿托梅拉公司 包括与超晶格sti界面相邻的非单晶纵梁的半导体器件和方法
US10461118B2 (en) 2017-12-15 2019-10-29 Atomera Incorporated Method for making CMOS image sensor including photodiodes with overlying superlattices to reduce crosstalk
US10529757B2 (en) 2017-12-15 2020-01-07 Atomera Incorporated CMOS image sensor including pixels with read circuitry having a superlattice
US10608027B2 (en) 2017-12-15 2020-03-31 Atomera Incorporated Method for making CMOS image sensor including stacked semiconductor chips and image processing circuitry including a superlattice
US10355151B2 (en) 2017-12-15 2019-07-16 Atomera Incorporated CMOS image sensor including photodiodes with overlying superlattices to reduce crosstalk
US10396223B2 (en) 2017-12-15 2019-08-27 Atomera Incorporated Method for making CMOS image sensor with buried superlattice layer to reduce crosstalk
US10367028B2 (en) 2017-12-15 2019-07-30 Atomera Incorporated CMOS image sensor including stacked semiconductor chips and image processing circuitry including a superlattice
US10615209B2 (en) * 2017-12-15 2020-04-07 Atomera Incorporated CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlattice
US10276625B1 (en) 2017-12-15 2019-04-30 Atomera Incorporated CMOS image sensor including superlattice to enhance infrared light absorption
US10361243B2 (en) 2017-12-15 2019-07-23 Atomera Incorporated Method for making CMOS image sensor including superlattice to enhance infrared light absorption
US10304881B1 (en) 2017-12-15 2019-05-28 Atomera Incorporated CMOS image sensor with buried superlattice layer to reduce crosstalk
US10529768B2 (en) 2017-12-15 2020-01-07 Atomera Incorporated Method for making CMOS image sensor including pixels with read circuitry having a superlattice
US10608043B2 (en) 2017-12-15 2020-03-31 Atomera Incorporation Method for making CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlattice
WO2019173668A1 (en) 2018-03-08 2019-09-12 Atomera Incorporated Semiconductor device including enhanced contact structures having a superlattice and related methods
US10727049B2 (en) 2018-03-09 2020-07-28 Atomera Incorporated Method for making a semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice
US10468245B2 (en) 2018-03-09 2019-11-05 Atomera Incorporated Semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice
EP3776073A1 (en) 2018-04-12 2021-02-17 Atomera Incorporated Semiconductor device and method including vertically integrated optical and electronic devices and comprising a superlattice
US10566191B1 (en) 2018-08-30 2020-02-18 Atomera Incorporated Semiconductor device including superlattice structures with reduced defect densities
US10811498B2 (en) 2018-08-30 2020-10-20 Atomera Incorporated Method for making superlattice structures with reduced defect densities
US20200135489A1 (en) * 2018-10-31 2020-04-30 Atomera Incorporated Method for making a semiconductor device including a superlattice having nitrogen diffused therein
US10580867B1 (en) 2018-11-16 2020-03-03 Atomera Incorporated FINFET including source and drain regions with dopant diffusion blocking superlattice layers to reduce contact resistance
US10840336B2 (en) 2018-11-16 2020-11-17 Atomera Incorporated Semiconductor device with metal-semiconductor contacts including oxygen insertion layer to constrain dopants and related methods
US10854717B2 (en) 2018-11-16 2020-12-01 Atomera Incorporated Method for making a FINFET including source and drain dopant diffusion blocking superlattices to reduce contact resistance
US10580866B1 (en) 2018-11-16 2020-03-03 Atomera Incorporated Semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance
US10840335B2 (en) 2018-11-16 2020-11-17 Atomera Incorporated Method for making semiconductor device including body contact dopant diffusion blocking superlattice to reduce contact resistance
US10847618B2 (en) 2018-11-16 2020-11-24 Atomera Incorporated Semiconductor device including body contact dopant diffusion blocking superlattice having reduced contact resistance
US10593761B1 (en) 2018-11-16 2020-03-17 Atomera Incorporated Method for making a semiconductor device having reduced contact resistance
US10818755B2 (en) 2018-11-16 2020-10-27 Atomera Incorporated Method for making semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance
US11329154B2 (en) 2019-04-23 2022-05-10 Atomera Incorporated Semiconductor device including a superlattice and an asymmetric channel and related methods
US11183565B2 (en) 2019-07-17 2021-11-23 Atomera Incorporated Semiconductor devices including hyper-abrupt junction region including spaced-apart superlattices and related methods
US10868120B1 (en) 2019-07-17 2020-12-15 Atomera Incorporated Method for making a varactor with hyper-abrupt junction region including a superlattice
US10825902B1 (en) 2019-07-17 2020-11-03 Atomera Incorporated Varactor with hyper-abrupt junction region including spaced-apart superlattices
US10825901B1 (en) 2019-07-17 2020-11-03 Atomera Incorporated Semiconductor devices including hyper-abrupt junction region including a superlattice
US10879357B1 (en) 2019-07-17 2020-12-29 Atomera Incorporated Method for making a semiconductor device having a hyper-abrupt junction region including a superlattice
US10937868B2 (en) 2019-07-17 2021-03-02 Atomera Incorporated Method for making semiconductor devices with hyper-abrupt junction region including spaced-apart superlattices
US10840388B1 (en) 2019-07-17 2020-11-17 Atomera Incorporated Varactor with hyper-abrupt junction region including a superlattice
US10937888B2 (en) 2019-07-17 2021-03-02 Atomera Incorporated Method for making a varactor with a hyper-abrupt junction region including spaced-apart superlattices
US11437487B2 (en) 2020-01-14 2022-09-06 Atomera Incorporated Bipolar junction transistors including emitter-base and base-collector superlattices
US11302823B2 (en) 2020-02-26 2022-04-12 Atomera Incorporated Method for making semiconductor device including a superlattice with different non-semiconductor material monolayers
US11177351B2 (en) 2020-02-26 2021-11-16 Atomera Incorporated Semiconductor device including a superlattice with different non-semiconductor material monolayers
US11075078B1 (en) 2020-03-06 2021-07-27 Atomera Incorporated Method for making a semiconductor device including a superlattice within a recessed etch
KR20210134445A (ko) 2020-04-29 2021-11-10 삼성전자주식회사 반도체 소자
US11469302B2 (en) * 2020-06-11 2022-10-11 Atomera Incorporated Semiconductor device including a superlattice and providing reduced gate leakage
US11569368B2 (en) 2020-06-11 2023-01-31 Atomera Incorporated Method for making semiconductor device including a superlattice and providing reduced gate leakage
US11848356B2 (en) 2020-07-02 2023-12-19 Atomera Incorporated Method for making semiconductor device including superlattice with oxygen and carbon monolayers
US11742202B2 (en) 2021-03-03 2023-08-29 Atomera Incorporated Methods for making radio frequency (RF) semiconductor devices including a ground plane layer having a superlattice
US11923418B2 (en) 2021-04-21 2024-03-05 Atomera Incorporated Semiconductor device including a superlattice and enriched silicon 28 epitaxial layer
US11810784B2 (en) 2021-04-21 2023-11-07 Atomera Incorporated Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial layer
US11728385B2 (en) 2021-05-26 2023-08-15 Atomera Incorporated Semiconductor device including superlattice with O18 enriched monolayers
US11682712B2 (en) 2021-05-26 2023-06-20 Atomera Incorporated Method for making semiconductor device including superlattice with O18 enriched monolayers
US11631584B1 (en) 2021-10-28 2023-04-18 Atomera Incorporated Method for making semiconductor device with selective etching of superlattice to define etch stop layer
US11721546B2 (en) 2021-10-28 2023-08-08 Atomera Incorporated Method for making semiconductor device with selective etching of superlattice to accumulate non-semiconductor atoms

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005018005A1 (en) * 2003-06-26 2005-02-24 Rj Mears, Llc Semiconductor device including mosfet having band-engineered superlattice
CN101253632A (zh) * 2005-07-15 2008-08-27 梅尔斯科技公司 含有位于应力层上的应变超晶格的半导体器件及其相关方法
US20080258134A1 (en) * 2007-04-23 2008-10-23 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (sti) regions with maskless superlattice deposition following sti formation and related structures
CN101438415A (zh) * 2006-05-05 2009-05-20 梅尔斯科技公司 包括具有超晶格沟道的浮栅存储单元的半导体器件及相关方法
CN101997032A (zh) * 2009-08-24 2011-03-30 索尼公司 半导体器件及半导体器件制造方法
CN103137488A (zh) * 2011-12-01 2013-06-05 中国科学院微电子研究所 半导体器件及其制造方法
CN103582930A (zh) * 2011-04-14 2014-02-12 国际商业机器公司 具有凹陷沟道膜和突变结的mosfet

Family Cites Families (128)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4485128A (en) 1981-11-20 1984-11-27 Chronar Corporation Bandgap control in amorphous semiconductors
JPH0656887B2 (ja) 1982-02-03 1994-07-27 株式会社日立製作所 半導体装置およびその製法
US4594603A (en) 1982-04-22 1986-06-10 Board Of Trustees Of The University Of Illinois Semiconductor device with disordered active region
GB8328474D0 (en) 1983-10-25 1983-11-23 Plessey Co Plc Diamond heatsink assemblies
US4590399A (en) 1984-02-28 1986-05-20 Exxon Research And Engineering Co. Superlattice piezoelectric devices
JPS6127681A (ja) 1984-07-17 1986-02-07 Res Dev Corp Of Japan 超格子構造のチヤネル部をもつ電界効果トランジスタ
US4882609A (en) 1984-11-19 1989-11-21 Max-Planck Gesellschaft Zur Forderung Der Wissenschafter E.V. Semiconductor devices with at least one monoatomic layer of doping atoms
JPS61145820A (ja) 1984-12-20 1986-07-03 Seiko Epson Corp 半導体薄膜材料
JPS61210679A (ja) 1985-03-15 1986-09-18 Sony Corp 半導体装置
JPS61220339A (ja) 1985-03-26 1986-09-30 Nippon Telegr & Teleph Corp <Ntt> 半導体材料特性の制御方法
JPS62219665A (ja) 1986-03-20 1987-09-26 Fujitsu Ltd 超格子薄膜トランジスタ
US4908678A (en) 1986-10-08 1990-03-13 Semiconductor Energy Laboratory Co., Ltd. FET with a super lattice channel
US5081513A (en) 1991-02-28 1992-01-14 Xerox Corporation Electronic device with recovery layer proximate to active layer
US5216262A (en) 1992-03-02 1993-06-01 Raphael Tsu Quantum well structures useful for semiconductor devices
JPH0643482A (ja) 1992-07-24 1994-02-18 Matsushita Electric Ind Co Ltd 空間光変調素子およびその製造方法
US5955754A (en) 1992-10-23 1999-09-21 Symetrix Corporation Integrated circuits having mixed layered superlattice materials and precursor solutions for use in a process of making the same
US5357119A (en) 1993-02-19 1994-10-18 Board Of Regents Of The University Of California Field effect devices having short period superlattice structures using Si and Ge
US5606177A (en) 1993-10-29 1997-02-25 Texas Instruments Incorporated Silicon oxide resonant tunneling diode structure
US5466949A (en) 1994-08-04 1995-11-14 Texas Instruments Incorporated Silicon oxide germanium resonant tunneling
US5627386A (en) 1994-08-11 1997-05-06 The United States Of America As Represented By The Secretary Of The Army Silicon nanostructure light-emitting diode
US5561302A (en) 1994-09-26 1996-10-01 Motorola, Inc. Enhanced mobility MOSFET device and method
US5577061A (en) 1994-12-16 1996-11-19 Hughes Aircraft Company Superlattice cladding layers for mid-infrared lasers
FR2734097B1 (fr) 1995-05-12 1997-06-06 Thomson Csf Laser a semiconducteurs
DE69631098D1 (de) 1995-08-03 2004-01-29 Hitachi Europ Ltd Halbleiterstrukturen
US6344271B1 (en) 1998-11-06 2002-02-05 Nanoenergy Corporation Materials and products using nanostructured non-stoichiometric substances
EP0843361A1 (en) 1996-11-15 1998-05-20 Hitachi Europe Limited Memory device
JPH10173177A (ja) 1996-12-10 1998-06-26 Mitsubishi Electric Corp Ｍｉｓトランジスタの製造方法
WO1998026316A1 (en) 1996-12-13 1998-06-18 Massachusetts Institute Of Technology Tunable microcavity using nonlinear materials in a photonic crystal
US5994164A (en) 1997-03-18 1999-11-30 The Penn State Research Foundation Nanostructure tailoring of material properties using controlled crystallization
US6255150B1 (en) 1997-10-23 2001-07-03 Texas Instruments Incorporated Use of crystalline SiOx barriers for Si-based resonant tunneling diodes
US6376337B1 (en) 1997-11-10 2002-04-23 Nanodynamics, Inc. Epitaxial SiOx barrier/insulation layer
JP3443343B2 (ja) 1997-12-03 2003-09-02 松下電器産業株式会社 半導体装置
JP3547037B2 (ja) 1997-12-04 2004-07-28 株式会社リコー 半導体積層構造及び半導体発光素子
US6608327B1 (en) 1998-02-27 2003-08-19 North Carolina State University Gallium nitride semiconductor structure including laterally offset patterned layers
JP3854731B2 (ja) 1998-03-30 2006-12-06 シャープ株式会社 微細構造の製造方法
US6888175B1 (en) 1998-05-29 2005-05-03 Massachusetts Institute Of Technology Compound semiconductor structure with lattice and polarity matched heteroepitaxial layers
RU2142665C1 (ru) 1998-08-10 1999-12-10 Швейкин Василий Иванович Инжекционный лазер
US6586835B1 (en) 1998-08-31 2003-07-01 Micron Technology, Inc. Compact system module with built-in thermoelectric cooling
JP3592981B2 (ja) 1999-01-14 2004-11-24 松下電器産業株式会社 半導体装置及びその製造方法
JP3225948B2 (ja) * 1999-02-17 2001-11-05 日本電気株式会社 電解効果トランジスタ及びその製造方法
WO2000052796A1 (fr) 1999-03-04 2000-09-08 Nichia Corporation Element de laser semiconducteur au nitrure
GB9905196D0 (en) 1999-03-05 1999-04-28 Fujitsu Telecommunications Eur Aperiodic gratings
US6993222B2 (en) 1999-03-05 2006-01-31 Rj Mears, Llc Optical filter device with aperiodically arranged grating elements
GB2385940B (en) 1999-03-05 2003-10-22 Nanovis Llc Aperiodically poled non-linear material
US6350993B1 (en) 1999-03-12 2002-02-26 International Business Machines Corporation High speed composite p-channel Si/SiGe heterostructure for field effect devices
US6281532B1 (en) 1999-06-28 2001-08-28 Intel Corporation Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering
US6570898B2 (en) 1999-09-29 2003-05-27 Xerox Corporation Structure and method for index-guided buried heterostructure AlGalnN laser diodes
US6501092B1 (en) 1999-10-25 2002-12-31 Intel Corporation Integrated semiconductor superlattice optical modulator
RU2173003C2 (ru) 1999-11-25 2001-08-27 Септре Электроникс Лимитед Способ образования кремниевой наноструктуры, решетки кремниевых квантовых проводков и основанных на них устройств
KR100675316B1 (ko) 1999-12-22 2007-01-26 엘지.필립스 엘시디 주식회사 세정장비 일체형 에치/스트립 장치
DE10025264A1 (de) 2000-05-22 2001-11-29 Max Planck Gesellschaft Feldeffekt-Transistor auf der Basis von eingebetteten Clusterstrukturen und Verfahren zu seiner Herstellung
US7902546B2 (en) 2000-08-08 2011-03-08 Translucent, Inc. Rare earth-oxides, rare earth -nitrides, rare earth -phosphides and ternary alloys with silicon
US7301199B2 (en) 2000-08-22 2007-11-27 President And Fellows Of Harvard College Nanoscale wires and related devices
US6638838B1 (en) 2000-10-02 2003-10-28 Motorola, Inc. Semiconductor structure including a partially annealed layer and method of forming the same
US6521549B1 (en) 2000-11-28 2003-02-18 Lsi Logic Corporation Method of reducing silicon oxynitride gate insulator thickness in some transistors of a hybrid integrated circuit to obtain increased differential in gate insulator thickness with other transistors of the hybrid circuit
US20020100942A1 (en) 2000-12-04 2002-08-01 Fitzgerald Eugene A. CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6673646B2 (en) 2001-02-28 2004-01-06 Motorola, Inc. Growth of compound semiconductor structures on patterned oxide films and process for fabricating same
US6690699B2 (en) 2001-03-02 2004-02-10 Lucent Technologies Inc Quantum cascade laser with relaxation-stabilized injection
US6646293B2 (en) 2001-07-18 2003-11-11 Motorola, Inc. Structure for fabricating high electron mobility transistors utilizing the formation of complaint substrates
EP1428262A2 (en) 2001-09-21 2004-06-16 Amberwave Systems Corporation Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
WO2003079415A2 (en) 2002-03-14 2003-09-25 Amberwave Systems Corporation Methods for fabricating strained layers on semiconductor substrates
US6816530B2 (en) 2002-09-30 2004-11-09 Lucent Technologies Inc. Nonlinear semiconductor light sources
US7023010B2 (en) 2003-04-21 2006-04-04 Nanodynamics, Inc. Si/C superlattice useful for semiconductor devices
US20070020833A1 (en) 2003-06-26 2007-01-25 Rj Mears, Llc Method for Making a Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer
US7531850B2 (en) 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a memory cell with a negative differential resistance (NDR) device
US7227174B2 (en) 2003-06-26 2007-06-05 Rj Mears, Llc Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US20040266116A1 (en) 2003-06-26 2004-12-30 Rj Mears, Llc Methods of fabricating semiconductor structures having improved conductivity effective mass
US20070063186A1 (en) 2003-06-26 2007-03-22 Rj Mears, Llc Method for making a semiconductor device including a front side strained superlattice layer and a back side stress layer
US20060292765A1 (en) 2003-06-26 2006-12-28 Rj Mears, Llc Method for Making a FINFET Including a Superlattice
US20060011905A1 (en) 2003-06-26 2006-01-19 Rj Mears, Llc Semiconductor device comprising a superlattice dielectric interface layer
US20050282330A1 (en) 2003-06-26 2005-12-22 Rj Mears, Llc Method for making a semiconductor device including a superlattice having at least one group of substantially undoped layers
US7491587B2 (en) 2003-06-26 2009-02-17 Mears Technologies, Inc. Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer
US7531829B2 (en) 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
US7446002B2 (en) 2003-06-26 2008-11-04 Mears Technologies, Inc. Method for making a semiconductor device comprising a superlattice dielectric interface layer
US7153763B2 (en) 2003-06-26 2006-12-26 Rj Mears, Llc Method for making a semiconductor device including band-engineered superlattice using intermediate annealing
US20060263980A1 (en) 2003-06-26 2006-11-23 Rj Mears, Llc, State Of Incorporation: Delaware Method for making a semiconductor device including a floating gate memory cell with a superlattice channel
US7514328B2 (en) 2003-06-26 2009-04-07 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween
US7586165B2 (en) 2003-06-26 2009-09-08 Mears Technologies, Inc. Microelectromechanical systems (MEMS) device including a superlattice
US7229902B2 (en) 2003-06-26 2007-06-12 Rj Mears, Llc Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction
US20060231857A1 (en) 2003-06-26 2006-10-19 Rj Mears, Llc Method for making a semiconductor device including a memory cell with a negative differential resistance (ndr) device
US20070010040A1 (en) 2003-06-26 2007-01-11 Rj Mears, Llc Method for Making a Semiconductor Device Including a Strained Superlattice Layer Above a Stress Layer
US20060223215A1 (en) 2003-06-26 2006-10-05 Rj Mears, Llc Method for Making a Microelectromechanical Systems (MEMS) Device Including a Superlattice
US7598515B2 (en) 2003-06-26 2009-10-06 Mears Technologies, Inc. Semiconductor device including a strained superlattice and overlying stress layer and related methods
US20060273299A1 (en) 2003-06-26 2006-12-07 Rj Mears, Llc Method for making a semiconductor device including a dopant blocking superlattice
US7586116B2 (en) 2003-06-26 2009-09-08 Mears Technologies, Inc. Semiconductor device having a semiconductor-on-insulator configuration and a superlattice
US7045377B2 (en) 2003-06-26 2006-05-16 Rj Mears, Llc Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US20070015344A1 (en) 2003-06-26 2007-01-18 Rj Mears, Llc Method for Making a Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions
US6958486B2 (en) 2003-06-26 2005-10-25 Rj Mears, Llc Semiconductor device including band-engineered superlattice
US7045813B2 (en) 2003-06-26 2006-05-16 Rj Mears, Llc Semiconductor device including a superlattice with regions defining a semiconductor junction
US6878576B1 (en) 2003-06-26 2005-04-12 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
US20060289049A1 (en) 2003-06-26 2006-12-28 Rj Mears, Llc Semiconductor Device Having a Semiconductor-on-Insulator (SOI) Configuration and Including a Superlattice on a Thin Semiconductor Layer
US7535041B2 (en) 2003-06-26 2009-05-19 Mears Technologies, Inc. Method for making a semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
US20070012910A1 (en) 2003-06-26 2007-01-18 Rj Mears, Llc Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer
US20060220118A1 (en) 2003-06-26 2006-10-05 Rj Mears, Llc Semiconductor device including a dopant blocking superlattice
US7531828B2 (en) 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions
US20070020860A1 (en) 2003-06-26 2007-01-25 Rj Mears, Llc Method for Making Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related Methods
US20060243964A1 (en) 2003-06-26 2006-11-02 Rj Mears, Llc Method for making a semiconductor device having a semiconductor-on-insulator configuration and a superlattice
US7612366B2 (en) 2003-06-26 2009-11-03 Mears Technologies, Inc. Semiconductor device including a strained superlattice layer above a stress layer
US20040262594A1 (en) 2003-06-26 2004-12-30 Rj Mears, Llc Semiconductor structures having improved conductivity effective mass and methods for fabricating same
US20070063185A1 (en) 2003-06-26 2007-03-22 Rj Mears, Llc Semiconductor device including a front side strained superlattice layer and a back side stress layer
US20050279991A1 (en) 2003-06-26 2005-12-22 Rj Mears, Llc Semiconductor device including a superlattice having at least one group of substantially undoped layers
US7202494B2 (en) 2003-06-26 2007-04-10 Rj Mears, Llc FINFET including a superlattice
US20060267130A1 (en) 2003-06-26 2006-11-30 Rj Mears, Llc Semiconductor Device Including Shallow Trench Isolation (STI) Regions with a Superlattice Therebetween
WO2005034325A1 (ja) 2003-09-30 2005-04-14 Sanken Electric Co., Ltd. スイッチング電源装置
KR100549008B1 (ko) 2004-03-17 2006-02-02 삼성전자주식회사 등방성식각 기술을 사용하여 핀 전계효과 트랜지스터를제조하는 방법
AU2006270126A1 (en) 2005-07-15 2007-01-25 Mears Technologies, Inc. Semiconductor device including a channel with a non-semiconductor monolayer and associated methods
US7517702B2 (en) 2005-12-22 2009-04-14 Mears Technologies, Inc. Method for making an electronic device including a poled superlattice having a net electrical dipole moment
TW200746237A (en) 2005-12-22 2007-12-16 Mears R J Llc Method for making an electronic device including a poled superlattice having a net electrical dipole moment
US7718996B2 (en) 2006-02-21 2010-05-18 Mears Technologies, Inc. Semiconductor device comprising a lattice matching layer
US7625767B2 (en) 2006-03-17 2009-12-01 Mears Technologies, Inc. Methods of making spintronic devices with constrained spintronic dopant
US20080012004A1 (en) 2006-03-17 2008-01-17 Mears Technologies, Inc. Spintronic devices with constrained spintronic dopant
US7781827B2 (en) 2007-01-24 2010-08-24 Mears Technologies, Inc. Semiconductor device with a vertical MOSFET including a superlattice and related methods
US7928425B2 (en) 2007-01-25 2011-04-19 Mears Technologies, Inc. Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods
US7863066B2 (en) 2007-02-16 2011-01-04 Mears Technologies, Inc. Method for making a multiple-wavelength opto-electronic device including a superlattice
US7880161B2 (en) 2007-02-16 2011-02-01 Mears Technologies, Inc. Multiple-wavelength opto-electronic device including a superlattice
JP2009054705A (ja) 2007-08-24 2009-03-12 Toshiba Corp 半導体基板、半導体装置およびその製造方法
JP5159413B2 (ja) 2008-04-24 2013-03-06 株式会社東芝 半導体装置及びその製造方法
JP4770885B2 (ja) * 2008-06-30 2011-09-14 ソニー株式会社 半導体装置
US7804130B1 (en) * 2008-08-26 2010-09-28 Taiwan Semiconductor Manufacturing Co., Ltd. Self-aligned V-channel MOSFET
US20110215299A1 (en) * 2010-03-08 2011-09-08 Mears Technologies, Inc. Semiconductor device including a superlattice and dopant diffusion retarding implants and related methods
JPWO2011135963A1 (ja) 2010-04-28 2013-07-18 日本碍子株式会社 エピタキシャル基板およびエピタキシャル基板の製造方法
JP5708187B2 (ja) 2011-04-15 2015-04-30 サンケン電気株式会社 半導体装置
KR101865754B1 (ko) * 2011-07-01 2018-06-12 삼성전자주식회사 반도체 장치 및 그 제조 방법
US8994002B2 (en) 2012-03-16 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET having superlattice stressor
US8497171B1 (en) 2012-07-05 2013-07-30 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET method and structure with embedded underlying anti-punch through layer
EP3072158A1 (en) 2013-11-22 2016-09-28 Atomera Incorporated Vertical semiconductor devices including superlattice punch through stop layer and related methods
US9406753B2 (en) 2013-11-22 2016-08-02 Atomera Incorporated Semiconductor devices including superlattice depletion layer stack and related methods
US9953874B2 (en) * 2016-04-28 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and methods of forming FinFETs

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005018005A1 (en) * 2003-06-26 2005-02-24 Rj Mears, Llc Semiconductor device including mosfet having band-engineered superlattice
CN101253632A (zh) * 2005-07-15 2008-08-27 梅尔斯科技公司 含有位于应力层上的应变超晶格的半导体器件及其相关方法
CN101438415A (zh) * 2006-05-05 2009-05-20 梅尔斯科技公司 包括具有超晶格沟道的浮栅存储单元的半导体器件及相关方法
US20080258134A1 (en) * 2007-04-23 2008-10-23 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (sti) regions with maskless superlattice deposition following sti formation and related structures
CN101997032A (zh) * 2009-08-24 2011-03-30 索尼公司 半导体器件及半导体器件制造方法
CN103582930A (zh) * 2011-04-14 2014-02-12 国际商业机器公司 具有凹陷沟道膜和突变结的mosfet
CN103137488A (zh) * 2011-12-01 2013-06-05 中国科学院微电子研究所 半导体器件及其制造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112074959A (zh) * 2018-04-12 2020-12-11 阿托梅拉公司 用于制造包括超晶格的倒t形沟道场效应晶体管(itfet)的器件和方法
CN113228300A (zh) * 2018-11-16 2021-08-06 阿托梅拉公司 包括源极和漏极区域与掺杂剂扩散阻挡超晶格层以减小接触电阻的finfet和相关方法
CN113228296A (zh) * 2018-11-16 2021-08-06 阿托梅拉公司 制造具有减小的接触电阻的finfet的方法

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