CN1064805C - 可用于脉宽调制显示系统的数字视频信号存储器 - Google Patents

可用于脉宽调制显示系统的数字视频信号存储器 Download PDF

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CN1064805C
CN1064805C CN95109222A CN95109222A CN1064805C CN 1064805 C CN1064805 C CN 1064805C CN 95109222 A CN95109222 A CN 95109222A CN 95109222 A CN95109222 A CN 95109222A CN 1064805 C CN1064805 C CN 1064805C
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CN1115936A (zh
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保罗·M·乌尔巴努斯
杰弗里·B·桑普塞尔
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Texas Instruments Inc
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    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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    • H04N5/7458Projection arrangements for image reproduction, e.g. using eidophor involving the use of a spatial light modulator, e.g. a light valve, controlled by a video signal the modulator being an array of deformable mirrors, e.g. digital micromirror device [DMD]
    • H04N2005/7466Control circuits therefor

Abstract

用空间光调制器电路(68)代替电视中的标准调谐单元可改进观察者看到的分辨度。本发明提供了一种系统结构(240)和它的单个部件和技术,使得在保持高系统速度时使成组数据速率为最小。所形成的系统在易于控制的数据速度和带宽下能提供较好的分辨度。

Description

可用于脉宽调制显示系统的数字视频信号存储器
本申请是申请日为920331、申请号为92102359.6、上述相同发明名称申请的分案申请。
本发明涉及光调制器,尤其涉及使用这些调制器系统的寻址和定时技术。
二进制光调制器具有两个状态,一个状态对应于“零”,它不发送光;另一状态对应于“1”,它对任何系统都发送最大光强的光。总之,这些调制器要么处于“断”、要么处于“通”状态。结果,从观察者眼睛看仅有两个不连续的光平,黑的和最大亮度。像素通/断状态变化时的中间光平因为它们的时间相当短而忽略。为了获得观察者能觉察的中间(模拟量)光平,可使用脉宽调制(PWM)技术。
基本的PWM方案如下。确定能向观察者显示模拟图像的速度,根据这速度建立帧速度(频率)和对应的帧时间。在标准的电视系统中,例如图像以每秒30传送,则每帧持续约33.3毫秒。
对帧或图像中的构成图形的像元(像素)的每个采样点进行光强的量化。设量化用6位(二进制)来表示,则量化每级为1/64,其中的63级为非零。在这例子中,33.3毫秒的帧时间分成63个相等的时间片。产生的时间片或是最低有效位(LSB)时间等于33.3/63毫秒或是528.6微秒。
建立了这些时间片后,凡观察者能够看见的所有模拟像素的光强度将被标定和量化,使黑色为0个时间片而最大亮度为63个时间片。由标定和量化的光强束设定像素的“通”(ON)时间以便接通对应数目的LSB时间。在最简单情况下,量化值大于零的所有像素在帧时间开始时转到ON,且在对应于它们的相对模拟光强的LSB时间由仍然维持ON。观察者的眼睛将对最大光强点积分,使它看起来如同这些点具有不变的模拟光平。
对于使用这种方案的二进制调制器的高清晰度电视(HDTV)显示,其要求的最大成组传送带宽可计算如下。在最坏情况下,即所给定帧的所有像素具有黑色和最大亮度之间的各强度值,所有像素必须在下一帧开始时发生变化。则LSB时间可计算如下:
水平像素数H=1920
垂直像素数V=1080
光强等级I=64
帧速度F=30帧/秒
每帧色彩数R=3(每个像素顺序显示每种色彩)
Figure 9510922200041
所以对这些值,LSB时间为176.3微秒。在这时间中,必须要装载2,073,600个像素(1920×1080)。该数据速度由下式给出:
该数据速度等于每秒11.76千兆位。建立这样系统的成本将高得惊人。
有许多方式能使PWM降低实际的数据速度。数据可以高度并行的方式输入到像素。例如,能够应用一种输入移位寄存器,每个寄存器包括8个像素,每个移位寄存器具有不在芯片上的数据输入端。对于1920个像素将有240个移位寄存器,它们共享一个公共的时钟。这240个移位寄存器能仅用8个时钟脉冲装载一行数据。数据速度减少240倍或减到49.1兆位/秒。
接下来用每个移位寄存器的输出来驱动一个并行数据锁存器。该数据锁存器在输入移位寄存器填满后用来存贮它们的内容。这样允许输入移位寄存器接受新的行数据,同时先前锁存的数据则存贮到像素阵列中一个选定的行中。因此,像素阵列可以低于输入电路运行速度8倍的速度进行寻址,从而限制了像素芯片所需要的高速电路。
输入移位寄存器/并行锁存器的组合电路可同时加在像素阵列的顶部和底部。这样允许设备的顶半部和底半部被同时寻址。现在每组寄存器/锁存器仅需在给定的帧时间中读一半数据。所以数据速度又可以减少2倍。新的输入数据速度为24.55兆位/秒,但引脚数为480个。
虽然这些以增加引脚数为代价的结构变化大大减少了对像素阵列中每个引脚输入的数据速度,他们也对像素的寻址方法施加了限制。单端输入方法可进行直接存取,而这种修改的结构只能对像素每次寻址一行。
本发明的目的和优点是很明显的,且部分地出现在下面的描述中。本发明通过提供一种存贮单元来完成本发明的目的。
该存贮单元,包含:
可对空间光调制器阵列用的视频数据进行格式转换的分割处理器;
至少两个连接于所述分割处理器的输入移位寄存器,每个所述输入移位寄存器经选择可从所述分割处理器接收格式转换后的视频数据;
每个所述输入移位寄存器至少连接一个存贮单元阵列,每个所述存贮单元阵列用于存贮从所述输入移位寄存器接收到的格式转换后的视频数据;
每个所述存贮单元阵列至少连接一个输出移位寄存器,每个所述输出移位寄存器用于从所述存贮单元阵列接收格式转换后的视频数据;
连接各所述输出移位寄存器的空间光调制器,所述空间光调制器用于从所述输出移位寄存器接收所述格式转换后的视频数据。
现在结合附图进行下面的描述以便完全理解本发明及其优点。
图1表示电视系统的方框图;
图2表示分割处理器;
图3a、3b和3c表示某些帧存贮器的方案;
图4表示可变形镜面装置(DMD)的集成电路装置;
图5表示块清除结构的一种实现方法;
图6a表示使用十-二进制数据的PWM寻址的定时图;
图6b表示块清除结构的定时图;
图7表示使用块清除结构的位时间(bit-period)共享寻址的定时图;
图8表示全面寻址复位寻址的定时图;
图9表示带有集成电路装置的DMD超级基片图;
图10表示DMD集成电路装置的部件分解图;
图11表示对强制数据和多行同时寻址的增强结构的实例;
图12表示对强制数据寻址的增强型结构的另一种方式。
图1表示本发明所描述的较佳实施例电视系统的方框图。接收机20接收某个标准格式的电视信号并把它传递给调谐器单元22。调谐器单元22将信号分离为音频和视频分量。信号的音频部分不再进一步研究。调谐器22将视频信号传送给信号处理单元23,该信号处理单元23进行模-数转换和其它的放大。该步骤仅在调谐器单元22输出模拟视频信号时才是必须的。放大了的数字信号24送给投射系统26,该系统包含:分割(decimation)处理器28、帧存贮器32和可变形镜面装置电路36。分割处理器28将信号变换为存贮器所需的格式,并提供输出信号30。该变换过的信号30再传送给帧存贮电路,在那里收集并存贮每帧完整的帧数据。完整的帧数据存满之后,将数据34传给DMD电路36,该电路通过光学装置38产生图像给观察者40。
适当的分割处理器28的例子更详细地显示在图2中。已放大的数字数据按照为输入寄存器27所选定的样品(采样)数例如6位样品输入该处理器。为了说明的目的,所示系统为6位,其最高有效位(MSB)是位5而最低有效位(LSB)是位0。不难理解:这些电路能很容易设置成处理任意所需要的位数。
然后6位样品(采样)送入一个1920×6位的移位寄存器42。在移位寄存器42填满1920个数据样品之后,移位寄存器中的数据传送给一个直接相连的影子存贮器(shadow memory)43,它也是1920×6位。该影子存贮器43是个6行阵列,每行包含1920位。任一给定行中存贮的数据位具有相等的二进制权值。例如影子存贮器的行1可以包含来自1920个输入样品的位0的全部数据,行2有全部样品的位1信号等。影子存贮器43的每一行可通过一个1∶6的译码器44的输出有选择地读出。所需要的行由输入到译码器的3位选择信号46来指定。然后,来自影子存贮器43的所选定行的1920个位加到数据总线48,从那里它们被送到240个8∶1多路转换器阵列52的输入端。一个选择水平位置的3位控制信号50同时送给所有的8∶1多路转换器,于是8∶1多路转换器产生一个240位的数据流30。所有8个水平位置均由控制信号50顺序地进行选择。
一种代替8∶1多路转换器的实施例可包含240个具有公共时钟51b和公共装入控制51a的8位移位寄存器。在这种情况下,标号52是代替多路转换器阵列的移位寄存器阵列。来自影子存贮器43的所选行的1920个位加给总线48,从那里它们送给240个8∶1移位寄存器52的阵列的数据输入端。装入控制51a确保将数据总线48的内容存入由240个8位移位寄存器构成的阵列52。然后,8个连续的脉冲加给51b使得移位寄存器中的数据输出到数据总线30。每个水平位置的数据流30传送给帧存贮器。
在上述两种实施例中,分割处理器28完成一种逆变换(inversemapping)的功能。每一个由6位组成的1920个输入样品以这样的方式存贮,即这些样品可作为6个1920位的输出样品进行存取。6个输出样品的每一个又被多路输出使与分割处理器的输出连接数达最少。这种多路输出也给DMD的输入数据格式提供了相匹配的数据格式。上述实施例是单色系统的情况,为了实现彩色系统,该分割处理器也可根据需要进行复制。
图3a表示单色显示时帧存贮器32的构成。当信号24经分割处理器28变换并以信号30的方式传送给帧存贮器之后,它被导向两个帧存贮器56a和56b中的一个。如果当前56a处于显示,则数据流30由开关54导向帧存贮器56b中的存贮单元。数据流30存入存贮单元阵列60b中的那些存贮单元由地址指示器58b分配。存贮单元阵列60b由若干单个的子阵列构成,61b是其中的一个。凡存贮在存贮单元阵列60b中的在同一帧中具有相同的权值(位值)的所有数据位存贮在同一子阵列中。当系统已完成存贮器56a的显示内容时,存贮器56b的内容就经过存贮单元阵列60b的输出总线63b和开关64送给系统。为了得到彩色,本方案也如分割处理器那样可根据需要复制。
单个子阵列61b的部件分解图示于图3b中。该子阵列61b分成更小单元的行。一组行57a或57b构成一个视频数据行。在本实施例中,每个时候只有1920×1080阵列的一半被寻址,57a代表行1,而57b代表行540。单元59a接纳行1、像素0的数据。单元62a接纳行1、像素7的数据。同列中处于它们之间的单元接纳行1的像素1-6的数据。同样,单元59b接纳行1、像素8的数据,单元59c接纳行1、像素1940的数据,而单元59d接纳行1、像素1912的数据。行1中的最后一个像素1919保存在单元62b中。数据经总线63b通过开关64送到DMD阵列。对于图3a中所示的每个单个的子阵列而言,不管系统中有多少视频行存在,都是该方案的重复。
图3c表示另一个彩色系统的实施例。视频信号经线24a、24b和24c馈入3个分割处理器28a、28b和28c。分割处理器28a、28b和28c沿着线30a、30b和30c把变换后的数据送给总线65。总线65上的数据装入由地址指示器58指定的存贮单元中。然后指示器58对存贮单元阵列60进行彩色加载。顶部1/3的存贮单元子阵列64a用于彩色1,第二个1/3的存贮单元64b用于彩色2,而底部1/3的存贮单元64c用于彩色3。单个子阵列67与图中所示的其它的子阵列相同,类似于图3b中的描述,以这种方式处理的数据能顺序地把全部3种彩色送入DMD电路。
图4显示了DMD集成电路的一个实施例。来自帧存贮电路32的数据经图1中的总线34传送给集成电路装置68。总线34实际上可分成两个总线34a和34b。总线34a传导DMD阵列的上半部数据,而总线34b传导阵列镜面的下半部数据。数据送给移位寄存器70a。当寄存器装满时,则数据送给并行锁存器74a。线组72a用于控制移位寄存器和并行锁存器的加载。数据锁存之后,继而传送到实际可变形镜面装置80的1920×1080阵列的上半部分。镜面寻址电路的行由行选择线78a通过行译码器76a进行选择。同时,相同的操作出现在阵列的下半部分。然后阵列的镜面被寻址且偏转产生图像,该图像通过光学装置送给观察者。
在这里,DMD显示装置由DMD像素阵列、输入移位寄存器和锁存器、以及行选择译码器组成。如图5方框所示,上述结构现已修改为允许在短时间内使DMD所选方框中的所有像素转换到“断”状态。并行存贮锁存器74已改为包括图5中的一根清除线92。需要时,该清除线能使驱动DMD阵列中各个列的数据设置到相当于像素位置的切断状态。另外,行选择译码器76在修改时添加了许多选择线,它们能使如90a那样一个方框内的行90a同时被选择。
为了把一个框内的像素设为“断”状态,需要使用并行存贮锁存器74的清除线92。其次,还需要把控制像素行的方框选择线84转变到“断”状态。最后,将一个复位脉冲加给单光束的镜面,并使该镜偏向“断”状态。虽然图5只示出了8个行框,但由于在所给的框中各行是连续的,没有理由限于使用这一种结构。框的数量可在1和设计者所需量之间变化。方框中的像素行也可以隔行交错(或其它)形式连接来替代依次连续的形式。
图6a中,显示了标准寻址方案的定时图。线94表示一帧时间。线96表示时间段,它们对应于数据中每个不同的二进制权值的时间量。时间段98是显示系统的最高有效位(MSB)的时间期。在该例中,由于是6位系统,所以最高有效位MSB是位5、时间段98拥有32个最低有效位LSB时间的显示时间。时间段100是显示下一位位4的时间期,该位4有一个16个LSB时间的显示时间。同样,时间段102属于位3,具有8个LSB时间。时间段104属于位2,具有4个LSB时间。时间段106属于位1,具有2个LSB时间。而最后,位0的时间用时间段108表示,它具有1个LSB时间。
上述时间段的镜面状态用线110表示。数据加载脉冲表示在线112上,光束复位脉冲表示在线114上,它们被加到光束的金属上以便将它们设置到由刚刚加载的各个数据位所指定的下一个状态。镜面状态116由下述处理过程得到。在加载脉冲118所示时间期间,数据加载到位5的电极上。通过复位脉冲120将镜面重新置位,以便显示数据加载脉冲118期间加载的新数据,从而开始帧时间。当位5显示到31个LSB时间116时,位4的数据在时间122期间加载。在数据加载时间122结束时,也即位5显示时间结束的同时,复位脉冲124将镜面置位到它们的新状态。于是显示时间126开始。这种过程对位3、2、1和0重复进行。加载和显示一个完整的帧的时间是常数。该例中,帧时间94分成63个LSB时间(32+16+8+4+2+1),所以每个LSB时间为整个帧时间的1/63。
最小的峰值数据速率由最短的时间间隔确定,在该时间间隔内某一给定有效位的所有位值必须都加载到DMD阵列上。图6a中,一个给定有效位的全部数据的加载时间是一个LSB时间。对一个给定帧中具有相同二进制权值的所有数据位的收集称为一个位帧(abit-frame)。对于6位系统,每帧有6个位帧数据。我们需要减低峰值数据速率,但很可能要牺牲DMD显示系统的某些其它性能。图6b显示怎样通过应用图5的框图结构来实现上述的要求。
图6b中,帧时间用线128表示。线组130构成显示在图5中第一个框结构如框90a的定时图。线132表示镜面状态;线134是镜面复位脉冲。线136指寻址清除脉冲和线140为数据加载脉冲。注意:当线132处于低状态时,如时间段156,所有镜面处于“断”状态。寻址清除脉冲线140代表先前已在图5中讨论的“清除”线以及框选择序列这种表示法也适用于图6a、6b和7。镜面显示状态138是通过加载时间140期间对方框90a加载最高有效数据位5和用置位脉冲142把镜面置位到新数据来获得的。起动时间138后的一个LSB时间,框90b的数据MSB的位5已被加载。框90b的线146上镜面144的状态变成恰好在复位脉冲后所加载的数据的状态。同样,框90c-90h的数据加载和显示也都移相一个LSB时间。
在时间间隔为31个LSB时间处,框90a的数据值4在时间148期间加载。时间148期间加载的数据对应于镜面显示状态150。光束复位脉冲152使镜面改变到对应于状态150的数据上。镜面状态150保持16个LSB时间。这一过程继续到镜面状态154为止,该状态为框90a的位2。因为那脉冲的权值仅有4个LSB时间,而加载整个装置需8个LSB时间,(每个框一个LSB时间),所以对方框90e-90h位2的数据还不能加载。为适应这种情况,切断框90a中的镜面一段4个LSB时间的期间,该期间在90a中用线段156表示。为了得到这种“断”状态,产生寻址清除信号脉冲160和产生光束复位脉冲162使镜面复位到“断”状态。镜面保持“断”4个LSB时间。3个LSB时间后,在时间164期间框90a的位1数据被加载。对这个位及其下一位重复上述过程,对于位1“断”时间增加到6个LSB时间,对于位0则为7个LSB时间。因此,加载和显示一个帧的数据的总时间为从上面讨论的标准寻址方案所需的63个LSB时间、加上4个“断”LSB时间、加上6个“断”LSB时间、加上7个“断”LSB时间,总共80个LSB时间。因为帧时间为常数,该例中LSB时间为总的帧时间的1/80,从而使该例中的LSB时间比图6a的LSB时间更短。图6b所示寻址方案使峰值数据速率在名义上减小了8倍。这是由于在图6b中一个LSB时间内所加载的像素数仅有图6a中一个LSB时间内所加载的像素数的1/8那么多。然而,虽则图6a和图6b中的帧时间相等,它们相应的LSB时间仍然不等。在图6a中,LSB时间为帧时间的1/63,而图6b中LSB时间为帧时间的1/80。由于LSB时间的差异,使用图6b寻址方案替代图6a的寻址方案时,实际的数据速率减少为8∶1×(63/80)≈6.3∶1。
虽然图6b寻址方案已大大减少了峰值数据速率,但它是以牺牲光效率为代价的。图6a中,如果像素为最大亮度,它接通和断开都为63个LSB时间,具有100%的寻址效率。而使用图6b的寻址方案,如果像素为最大亮度,则它接通63个LSB时间而断开为80个LSB时间,由于像素有17个LSB时间总是断开的,结果光效率约79%。
提高图6b寻址方案的光效率同时保持给DMD低的瞬时数据速度是需要的。提高图6b方案的光效率的一种方法是当镜面处于断状态时减少LSB时间的数量。图7是对图6b稍作修改的方案,它能完成上述目的。一个附加的好处是,它还稍微减小了图6b方案的峰值数据速率。在图7中,帧时间用线166表示。线组130仍代表框1的有效信号。线132还是镜面状态;线134为光束复位;线136为寻址清除;和线140为数据加载线。在该方案中,位5数据即MSB在时间168被加载,镜面用脉冲172复位且数据在镜面状态170期间显示8个LSB时间。进入显示期7个LSB时间后,位1数据在时间174期间被加载,并用复位脉冲176接通镜面。在镜面状态时间178有数据显示,该时间实现了位1所需的2个LSB时间。然后位5数据再一次加载在时间180的镜面上,该镜面状态是由复位脉冲182使其回到位5状态的。位5数据在镜面状态时间184被显示,该时间等于16个LSB时间。所以此时位5数据已显示了24个LSB时间,相当总需要量的3/4。位0数据用脉冲202加载且显示一个LSB时间186,完成了对位0的要求。然后位5数据在时间204期间再一次被加载且在镜面状态时间188期间显示,显示了8个LSB时间,将它的总显示时间提高到32个LSB时间,因此完成了由它的二进制权值所规定的需要。镜面显示时间190用于位4;显示时间192用于位3;而显示时间194用于位2。这样,就完成了按照它们的二进制权值对所有位显示它们特定时间量的要求。
框90a-90d的定时图除了他们有相移外是相同的。但方框90a-90d与方框90e-90h相比则不尽然。方框90e的定时图用线组206表示。因为数据的加载和显示方式与所有其它方框的是相同的,所以这里仅讨论线207。镜面显示时间208用于位5,它显示8个LSB时间。与框1类同,位1数据加载显示一个2LSB时间的时间210,由此完成它的要求。时间段212再一次用于显示位5,它为24个LSB时间,它完成了位5的需要。注意这与框1的不同点,图上时间222是显示位4的总时间。位4在时间段214中显示4个LSB时间,然后位0数据加载并显示一个LSB时间。位4重新加载并在时间段218中显示它所需要的12个LSB时间。结果是:时间222为17个LSB时间而不是标准的16个。这更长的时间是由处在加载脉冲221和223之间(分别在框90d和90e上)的间隙220引起的。该间隙在框90a-90c中也有。观察框90a,在时间段192和194之间也能看到间隙196。这是由于等到位3完全加载后位2才能加载。由于在显示位4数据期间加载位0的数据因而在框5中产生间隙,所以直到过了8个LSB时间后框8中的位3才能加载。所形成的总显示时间为71个LSB时间,它比图6b中讨论的方案时间上要短,故而它比图6a的方案有更低的数据速率,与该方法相关的是,复位脉冲的数量也大得多。
在给定的帧时间中使用大量复位脉冲可能引起潜在效应,所以需要一种避免这种潜在效应的对DMD寻址的方法。图8显示了这样一种方法,称为全面寻址复位(TAR)法。本方法与上面讨论的位时间(bit-period)共享方法之间有三个主要的不同点。
首先,在TAR法中,在复位脉冲加给像素之前,对整个DMD用一特定位的位帧(bit-frame)数据加载,而位时间方法只加载部分DMD(一个框),然后加上复位脉冲。其次,在TAR方法中,整个装置用8个LSB时间加载。而在前面的方法中,整个装置用8段时间加载,每次加载一个位帧。二者的数据加载总时间是相同的。
图8中,线228代表观察者看到的镜面状态。观察者看到“位5”230a接通一段等于32个LSB时间的时间期,后随的“位4”230b接通时间为位5的一半。该图形连续下去直至达到“位2”230d和“位1”230e之间的时间点为止。在这一时间点上,实际上存在一个所有镜面处于“断”的时期。当然,由于该时期是一种比人们眼睛的临界闪烁频率高得多的频率,实际上观察者不能看到它。在适当的时间量之后,“位0”230f被显示。
线232是数据加载定时线。加载时间的每一个,232a-232f,等于8个LSB时间。“位5”232a恰好在线228所示位5的显示时间之前被加载。同样,所有的位都恰好在线228上的显示时间之前加载。每一位的加载时间是相同的。线234是地址复位线,线236是光束复位线。送给光速的复位脉冲的数量有相当大的减少。这样消除了光束机械部件的磨损和损坏。
使上面讨论的过程得以实现的结构示于图9中。图4中简单的DMD芯片68已变成超级基片(superstrate)240的一部分。线34a和34b经多路分配器(8∶128)242a和242b进入电路。所形成的信号以16位线送给先进先出(FIFO)缓存器244a至244d和244b至244c。各FIFO的输出经线246a和246b传输给DMD芯片。控制信号经线78(线选择)和线248(帧复位)进入DMD芯片。
DMD装置68的部件分解图示于图10。来自总线246a和246b的数据经多路分配器(1∶8×128)250a和250b进入镜面阵列80a和80b。线选择信号78分成进入下面阵列译码器76b的下线选择和进入上面阵列译码器76a的上线选择。线248上的帧复位信号也分为存取下面镜面阵列80b和存取上面镜面阵列80a。这种修改后的结构能支持上面讨论的不同寻址方案,加上许多其它改进,使该装置更灵活多用。
对上述结构可增强些结构来增加速度。一种增强是具有数据输入结构,这样使得不仅正常输入数据可被选择,而且常数输入数据也可被选择。这种结构的增加如图11所示,对于正常数据输入,数据为单值的,输入数据经过线254a至254c馈送到多路转换器252a至252b,后者的输出被用来选择驱动阵列的列。对强制性的数据输入,数据为常数,线256a和256b上的强制数据将加到列中。数据的选择由多路转换器258a和258b来完成。这样,常数数据便可以这样的速度加给DMD镜面阵列(图中为下阵列80b中的各个列,该速度仅受限于强制数据多路转换器和带有输入线260的行选择译码器16b,这输入线260上的控制信号是用来决定多路或是单路行选择的。
另一种增强是通过改变译码器的结构使多行同时被寻址,包括所有行同时寻址或分组进行寻址。这种分组应这样安排,以便为给定的应用带来最大的好处。例如,这种分组可以把行的任何数目和组合作为一个组进行寻址,且可定义任何数量的组数。这种对组的定义规定了译码器的结构。
虽然这里对显示系统和它的结构的特定实施例作了描述,这样的具体说明不能认为是本发明范围的限定,其限定如下面权利要求书中所述。

Claims (2)

1.一种数字视频信号存贮器,其特征在于,包含:
具有输入缓存器的分割处理器,对空间光调制器阵列用的视频数据进行格式转换并将格式转换后的视频数据输出到总线;
至少两个通过所述总线连接于所述分割处理器的输入移位寄存器,每个所述输入移位寄存器经选择可从所述分割处理器接收格式转换后的视频数据;
每个所述输入移位寄存器至少连接一个存贮单元阵列,每个所述存贮单元阵列用于存贮从所述输入移位寄存器接收到的格式转换后的视频数据;
每个所述存贮单元阵列至少连接一个输出移位寄存器,每个所述输出移位寄存器用于从所述存贮单元阵列接收格式转换后的视频数据;
连接各所述输出移位寄存器的空间光调制器,所述空间光调制器用于从所述输出移位寄存器接收所述格式转换后的视频数据。
2.如权利要求1所述的数字视频信号存贮器,其特征在于,系统中,每种彩色有一输入移位寄存器,每种彩色的数据存贮在分开的存贮单元阵列中,使所述输出寄存器依序接收每种彩色数据。
CN95109222A 1991-04-01 1995-08-11 可用于脉宽调制显示系统的数字视频信号存储器 Expired - Fee Related CN1064805C (zh)

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EP0261897B1 (en) * 1986-09-20 1992-08-19 THORN EMI plc Display device

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Publication number Publication date
EP0689343A2 (en) 1995-12-27
CN1115936A (zh) 1996-01-31
KR920020249A (ko) 1992-11-20
US5523803A (en) 1996-06-04
EP0689345A3 (en) 1996-05-15
EP0689343A3 (en) 1996-05-15
US5339116A (en) 1994-08-16
CN1115935A (zh) 1996-01-31
CN1068232A (zh) 1993-01-20
KR100253106B1 (ko) 2000-05-01
CN1064804C (zh) 2001-04-18
TW226513B (zh) 1994-07-11
CN1040493C (zh) 1998-10-28
US5745193A (en) 1998-04-28
EP0689345B1 (en) 2002-07-10
JPH05183851A (ja) 1993-07-23
CA2063744A1 (en) 1992-10-02
EP0689344A3 (en) 1996-05-15
CA2063744C (en) 2002-10-08
EP0507270A1 (en) 1992-10-07
DE69220998D1 (de) 1997-09-04
EP0507270B1 (en) 1997-07-23
DE69232676D1 (de) 2002-08-14
DE69220998T2 (de) 1998-01-22
EP0689345A2 (en) 1995-12-27
EP0689344A2 (en) 1995-12-27
DE69232676T2 (de) 2003-02-06
US5278652A (en) 1994-01-11

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