CN105405771A - Method of mounting chip on printed circuit board - Google Patents
Method of mounting chip on printed circuit board Download PDFInfo
- Publication number
- CN105405771A CN105405771A CN201410460704.7A CN201410460704A CN105405771A CN 105405771 A CN105405771 A CN 105405771A CN 201410460704 A CN201410460704 A CN 201410460704A CN 105405771 A CN105405771 A CN 105405771A
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- chip
- circuit board
- printed circuit
- pcb
- recess
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29139—Silver [Ag] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Abstract
The invention discloses a method of mounting a chip on a printed circuit board. The method comprises the steps of providing a chip having a plurality of bonding pads and a printed circuit board having a concave portion and a plurality of connecting portions; gluing the concave portion; placing the chip into the concave portion; and forming a circuit pattern to connect the associated bonding pads and the connecting portions. The concave portion has a substantially flat bottom and a shape approximating but larger than the shape of the chip, so that the chip can be fixed to the inside of the concave portion after the gluing step.
Description
Technical field
The present invention about a kind of method of chip, particularly about the method for a kind of chip on printed circuit board (PCB).
Background technology
Silicon or integrated circuit are the core components of electronic equipment, usually occur with the form of encapsulation.Along with the development of manufacturing technology and the demand of light and handy design are popularized on end product, various method for packing is also invented thereupon, to meet this demand.In most of the time, silicon is sealed in protective material, among such as epoxy resin.Have some situation, particularly when silicon is sensor device, such as during identification of fingerprint chip, this silicon needs to be installed on substrate, and must expose the surface of certain part.In addition, for fingeprint distinguisher, the thickness of encapsulated sensor must be thin as much as possible.Therefore, the technology that silicon joins substrate to plays a very important role.This engages the circuit connection needing to guarantee that period is good, and enough hardness maintains fingerprint Identification sensor does not apply shearing impact by finger.
Flip Chip is a kind of method being suitable for better interconnection between crystal grain and printed circuit board (PCB).Cover brilliant processing procedure and be similar to common integrated circuit production, only increase the step that some are extra.Ask for an interview Fig. 1.Close to the end of manufacturing process, the pad 2 of the attachment of a chip 1 carries out metallizing to make their more acceptant solders, and this is normally made up of several process.The soldered ball 3 of little point-like is then deposited on each metallization pad 2, and chip 1 then normally cuts out by wafer.In order to paste on chip 1 to printed circuit board (PCB) 4 that overturns, chip (or crystal grain) 1 is inverted, the connecting portion 5 making soldered ball 3 down below it on this printed circuit board (PCB) 4.Then normally used is that hot ultrasonic waves engages or solder reflow process, then melting soldered ball 3 is to produce electrical connection, and this also leaves the erection bay of little space under chip circuit and its.In most of the cases, a kind of electrical insulating property bonding agent 6 then can fill bottom, connects to provide stronger mechanicalness.
A challenge of Flip Chip is the heat radiation carried out for the thermal stress in chip 1.Bonding agent 6 is used as heat bridge and connects, and guarantees that soldered ball 3 is not subject to stress because of thermal difference between chip 1 and printed circuit board (PCB) 4.Thermal expansion mismatch between bonding agent 6 spreading chip 1 and printed circuit board (PCB) 4, prevents stress from concentrating on soldered ball 3, causes premature failure.Become more and more small when the fan-out of chip logic lock increases and is correlated with for the pad welded, the heat dissipation like this for the bonding agent of soldered ball just becomes bad.In other words, because the bonding agent of finite quantity application takes away not enough heat, small soldered ball is easily injured causes open fault.Meanwhile, for fingerprint Identification sensor chip, the joint capacity between chip and printed circuit board (PCB), may be not enough to resist the power applied by finger.
A good solution being used for addressing this problem may be United States Patent (USP) the 5th, 045, No. 921.Ask for an interview Fig. 2, this figure illustrates installation one electric board array carrier integrated device electronics 10 on printed circuit board (PCB).It has thin and " band shape " substrate 11 for softness, and this substrate 11 has many vestiges 12.Substrate 11 can bear larger horizontal mechanical displacement.One integrated-circuit die 13 be installed near or just on the substrate 11.There is soldered ball 15 outer end 14 of substrate vestige 12, in order to produce the connection with printed circuit board (PCB).One packaging body 16 is containing having covered this crystal grain 13.In addition, a carrier structure can be provided near the periphery 17 of substrate 11, so that in process, and test and increase rigidity when installing, but this also may provide the function of face-off.This is thin and the substrate 11 of softness can in sizable encapsulation region, the mechanical displacement of the transverse direction that absorptance is larger or longitudinal direction, this can hold few to 20 or nearly 500 or more connection.Before or after carrying out encapsulation printed circuit board (PCB) step, soldered ball 15 can be connected to the perforation 18 through this substrate 11, and this perforation 18 is filled with electric conducting material at least in part, detects to allow rear side.In addition, a heat radiating fin structure 19 directly can be attached to the crystal grain 13 in electric board array carrier integrated device electronics 10.Though United States Patent (USP) the 5th, 045, No. 921 provide belt base plate to the joint between crystal grain and printed circuit board (PCB), are a kind of inventions of innovation, but are also that this belt base plate causes the complexity of installation and extra cost.
Therefore, for chip to printed circuit board (PCB) improve one's methods real for needed for.Particularly, the binding characteristic between chip and printed circuit board (PCB) should be able to resist the external force be added on chip.
Summary of the invention
This section of Word Input and compiling some feature of the present invention.Other features will be exposed in subsequent paragraph.Its object in the spirit and scope containing additional claim, various amendment and similar arrangement.
Because existing chip is to the method for printed circuit board (PCB), effectively can not provide the binding characteristic between chip and printed circuit board (PCB), to resist the external force be added on chip, particularly shear stress, namely object of the present invention is in the method providing an improvement.
According to a kind of aspect of the present invention, the method for a kind of chip on printed circuit board (PCB) comprises step: provide a chip with multiple joint sheet and a printed circuit board (PCB) with a recess and multiple connecting portion; Gluing is in this recess; Placing this chip enters in this recess; And form joint sheet and the connecting portion of circuit pattern join dependency.The bottom substantial planar of this recess, the shape approximation of this recess is comparatively large in the shape of this chip, so that this chip after gumming step, can be fixed on this recess inner.
According to the present invention, this gumming step is reached by a conducting resinl.One auxiliary non-conductive adhesive coats on this conducting resinl and the gap sealed between this chip and printed circuit board (PCB) further.This formation circuit pattern step is reached by ink jet printing or silk screen printing, and an electrically conductive ink or conductive paste can be used for this ink jet printing or silk screen printing.According to this case conception, this printed circuit board (PCB) has 3 conductive layers and 2 insulating barriers that are at least staggered to form, and this formation circuit pattern step is by forming one deck copper and etching not the needing part of this layer of copper and reach.This chip is an imageing sensor, and further, this imageing sensor can be a fingerprint Identification sensor.
During enforcement, after this chip of this placement enters this recess step, the jump of a upper face height of this chip and the height of this printed circuit board (PCB) is less than 0.1mm.
According to the present invention, the method comprises a step further: form a protective layer on chipless region, this protective layer is manufactured by organic-containing materials.
Due to the performance pining down and glue together power of recess external form, chip can effectively be fixed in groove, and the circuit between chip with printed circuit board (PCB) is connected, then rely on electrically conductive ink or conductive paste.Aforesaid problem can be effectively solved according to the inventive method.
Accompanying drawing explanation
Fig. 1 is used for illustrating that the known crystalline substance that covers processes;
Fig. 2 shows the electric board array carrier integrated device electronics in case before (Fig. 1);
Fig. 3 is the flow chart of the method for chip on printed circuit board (PCB) of one embodiment of the invention;
Fig. 4 to Fig. 9 is the schematic diagram of each step describing Fig. 3;
Figure 10 is after the method for chip on printed circuit board (PCB) of application above-described embodiment, the top view of chip and printed circuit board (PCB).
Description of reference numerals: 1-chip; 2-pad; 3-soldered ball; 4-printed circuit board (PCB); 5-connecting portion; 6-bonding agent; 10-electric board array carrier integrated device electronics; 11-substrate; 12-vestige; 13-crystal grain; 14-outer end; 15-soldered ball; 16-packaging body; 17-periphery; 18-bores a hole; 19-heat radiating fin structure; 100-printed circuit board (PCB); 110-first conductive layer; 120-first insulating barrier; 130-second conductive layer; 140-second insulating barrier; 150-the 3rd conductive layer; 160-recess; 200-conducting resinl; 210-assists non-conductive adhesive; 300-chip; 340-joint sheet; 400-circuit pattern; 500-protective layer; S01 ~ S05-step.
Embodiment
The present invention more specifically describes by with reference to following embodiment.
For an embodiment is described, refer to Fig. 3 to Figure 10.Fig. 3 is the flow chart of the method for chip on printed circuit board (PCB) according to one embodiment of the invention.Fig. 4 to Fig. 9 is the schematic diagram of each step describing Fig. 3.Figure 10 is after application the method, the top view of a chip 300 and a printed circuit board (PCB) 100.
First step of method of the present invention is to provide chip 300 and a printed circuit board (PCB) 100 (i.e. Fig. 3 step S01).According to the present invention, this chip 300 exists with granular form, instead of the integrated circuit of an encapsulation.Do not have the packed part of conventional package integrated circuit, chip 300 can have and carries out assembling thinner thickness, and can reduce the thickness of these chip 300 final products of application.In application, chip 300 is preferably an imageing sensor, because it there is no need by parcel protection.On the contrary, imageing sensor itself part must be exposed to external environment condition, makes them work orderly.In addition, some in them can run into the strength of extra applying, and the protection of friction resistant power should want more well-done.Such as, chip 300 is the fingerprint Identification sensor chip of a granular form in the present embodiment.Before the further processing procedure of the inventive method applies, its last layer design protection should first be got ready.Please first refer to Figure 10.From the top view of chip 300, clearly find out that the homonymy of chip 300 has a sensing part 320 and several joint sheet 340.In the present embodiment, for illustrative purposes, 15 joint sheets 340 are used.During enforcement, the number of joint sheet 340 is not limited to 15.According to the design of different fan-outs, this number can be more, and such as tens to hundreds of.Joint sheet 340 is fanned out to outside circuit for connecting.
Printed circuit board (PCB) 100 can be any form, except soft printed circuit board.According to the present invention, preferably there are at least three layers of conductive layer and two layer insulatings that are staggered to form.Refer to Fig. 4.This printed circuit board (PCB) 100 has one first conductive layer 110,1 first insulating barrier 120,1 second conductive layer 130,1 second insulating barrier 140 and one the 3rd conductive layer 150.Each conductive layer forms a specific circuit.Many perforation (not illustrating) can be used, fill with electric conducting material, such as copper.Perforation can be used for conduction current between two or three conductive layers, and the first insulating barrier 120 and the second insulating barrier 140 essence stop the electrical connection of two adjacent conductive interlayers.Because each conductive layer may can not fully be formed or expand, to occupy spaces whole between the first insulating barrier 120 and the second insulating barrier 140, part first insulating barrier 120 and the second insulating barrier 140 is had to be connected with each other.For the purpose of illustrating, dotted line is used for separation two insulating barrier.In fact, this interface is so not clear and definite.
Be understandable that, in the explanation that printed circuit board (PCB) 100 compares with other assemblies, all diagrams are not drawn according to actual ratio.In order to understand the present invention better, the length of printed circuit board (PCB) 100 and width, comparatively shrink compared to other assembly.During enforcement, come wider shown in the comparable Fig. 4 to Fig. 9 of printed circuit board (PCB) 100, the claim do not thereby not limited the invention.Printed circuit board (PCB) 100 has a recess 160, and this recess 160 can be formed by a part of first insulating barrier 120 of excision.The bottom substantial planar of recess 160, and formed by the second conductive layer 130.The shape approximation of recess 160 is comparatively large in the shape of chip 300, so that this chip 300 after next step gluing, can be fixed on this recess 160 inner.First conductive layer 110 has several part, is used for connecting to relevant joint sheet 340, so that the complete circuit acting as a transducer can realize after being connected to form between those parts and joint sheet 340.
Next step is that gluing is in this recess 160 (i.e. Fig. 3 step S02).Ask for an interview Fig. 5.One conducting resinl 200 is for gumming step.Best situation is this conducting resinl 200 is silver paste.The reason that conducting resinl 200 uses is that chip 300 needs be fixed and must conduct therebetween with printed circuit board (PCB) 100.In fact, the amount of conducting resinl 200 may not be certain as illustrated so much, as long as printed circuit board (PCB) 100 and chip 300 can be binded all right.Then, chip placement 300 is to (i.e. Fig. 3 step S03) in recess 160.Ask for an interview Fig. 6.Be positioned over after on conducting resinl 200 at this chip 300, some spaces may fill up by conducting resinl 200.This space forms a gap between chip 300 and printed circuit board (PCB) frontside edge.One auxiliary non-conductive adhesive 210 can be used for coating on conducting resinl 200 further, and seals this gap.Refer to Fig. 7.Preferably use heat-conducting glue as this auxiliary non-conductive adhesive 210, suggestion uses epoxy resin.
It should be noted that after step S03 can not be applied to step S02, before fixing, need the conducting resinls such as time 200 and develop maximum stickiness at once.It should be noted that after step S03, a upper face height of chip 300 may essence close to the height of this printed circuit board (PCB) 100 upper face.This is because two upper faces must be quite close, be beneficial to next step and perform, so that the circuit formed on both surfaces also can not be damaged because being formed at a large jump (or height fall) therebetween.In fact, after step S03, the height jump of chip 300 upper face height and printed circuit board (PCB) 100 upper face should be less than 0.1mm.Because chip 300 may be surrounded by a housing (not illustrating), but sensing part 320 must be exposed to opening, chip 300 can a little more than printed circuit board (PCB) 100.
Next step forms circuit pattern 400, and joint sheet 340 and the connecting portion 140 (i.e. Fig. 3 step S04) of join dependency, be illustrated in Fig. 8.This step is reached by ink jet printing or silk screen printing.But the ink of printing will limit, and electrically conductive ink can be used in ink jet printing or silk screen printing.Electrically conductive ink comprises electric conducting material.After it becomes dry, circuit can be formed by the electric conducting material remained and connect, as circuit pattern 400.Circuit pattern 400 can be formed by other method, such as, by forming one deck copper and etching not the needing part of this layer of copper and reach.In addition, if further fixture is used to the upper of joint sheet 340, electrically conductive ink can replace by the conductive paste.
The installation of chip 300 on printed circuit board (PCB) 100 can complete after the above step.But according to spirit of the present invention, the method can comprise a step further to form a protective layer 500 (i.e. Fig. 3 step S05) on chipless region and non-visual sensing area.Refer to Fig. 9.This is because residual electrically conductive ink (cream) electric conducting material may not be wear-resisting.In order to protective circuit pattern 400, there is protective layer 500.Best situation is that protective layer 500 is made by organic-containing materials.
From the above-mentioned explanation of the present embodiment, comparing of some feature of the present invention and conventional method can be understood.First, the recess 160 in printed circuit board (PCB) 100 only needs large can hold chip 300 and conducting resinl 200.After gluing, chip 300 can be firmly fixed in printed circuit board (PCB) 100.Chip 300 can be resisted by finger applied force amount, with by the assistance of conducting resinl 200 and printed circuit board (PCB) 100 reaction force provided, obtains fingerprint pattern.The second, described by the circuit of chip 300 with printed circuit board (PCB) 100 to be formed without applying welding, do not give birth to the problem of more heat radiations.
Although the present invention discloses as above with embodiment; so itself and be not used to limit the present invention, have in any art and usually know the knowledgeable, not departing from the spirit and scope of this creation; when a little change and retouching can be done, all fall within the scope of protection of the present invention.
Claims (13)
1. the method for chip on printed circuit board (PCB), is characterized in that, comprise step:
One chip with multiple joint sheet and a printed circuit board (PCB) with a recess and multiple connecting portion are provided;
Gluing is in this recess;
Placing this chip enters in this recess; And
Form the described joint sheet of circuit pattern join dependency and described connecting portion,
The wherein bottom flat of this recess, the shape approximation of this recess is comparatively large in the shape of this chip, so that this chip after gumming step, can be fixed on this recess inner.
2. the method for chip on printed circuit board (PCB) as claimed in claim 1, it is characterized in that, this gumming step is reached by a conducting resinl.
3. the method for chip on printed circuit board (PCB) as claimed in claim 2, is characterized in that, an auxiliary non-conductive adhesive coats on this conducting resinl and the gap sealed between this chip and printed circuit board (PCB).
4. the method for chip on printed circuit board (PCB) as claimed in claim 1, it is characterized in that, this formation circuit pattern step is reached by ink jet printing or silk screen printing.
5. the method for chip on printed circuit board (PCB) as claimed in claim 4, is characterized in that, an electrically conductive ink is used for this ink jet printing or silk screen printing.
6. the method for chip on printed circuit board (PCB) as claimed in claim 4, is characterized in that, a conductive paste is used for this ink jet printing or silk screen printing.
7. the method for chip on printed circuit board (PCB) as claimed in claim 1, it is characterized in that, this printed circuit board (PCB) has three conductive layers and two insulating barriers that are at least staggered to form.
8. the method for chip on printed circuit board (PCB) as claimed in claim 1, is characterized in that, this formation circuit pattern step is by forming one deck copper and etching not the needing part of this layer of copper and reach.
9. the method for chip on printed circuit board (PCB) as claimed in claim 1, it is characterized in that, this chip is an imageing sensor.
10. the method for chip on printed circuit board (PCB) as claimed in claim 9, it is characterized in that, this imageing sensor is a fingerprint Identification sensor.
The method of 11. chip as claimed in claim 1 on printed circuit board (PCB), is characterized in that, after this chip of this placement enters this recess step, the jump of a upper face height of this chip and the height of this printed circuit board (PCB) is less than 0.1mm.
The method of 12. chip as claimed in claim 1 on printed circuit board (PCB), is characterized in that, also comprise a step: form a protective layer on chipless region.
The method of 13. chip as claimed in claim 1 on printed circuit board (PCB), it is characterized in that, this protective layer is manufactured by organic-containing materials.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410460704.7A CN105405771B (en) | 2014-09-11 | 2014-09-11 | Chip is in the method on printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410460704.7A CN105405771B (en) | 2014-09-11 | 2014-09-11 | Chip is in the method on printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105405771A true CN105405771A (en) | 2016-03-16 |
| CN105405771B CN105405771B (en) | 2018-11-27 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410460704.7A Expired - Fee Related CN105405771B (en) | 2014-09-11 | 2014-09-11 | Chip is in the method on printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105405771B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111970417A (en) * | 2019-05-20 | 2020-11-20 | 三星电机株式会社 | Camera module |
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| CN103579171A (en) * | 2013-10-11 | 2014-02-12 | 三星半导体(中国)研究开发有限公司 | Semiconductor packaging piece and manufacturing method thereof |
| CN103886299A (en) * | 2014-03-27 | 2014-06-25 | 成都费恩格尔微电子技术有限公司 | Packaging structure of capacitive fingerprint sensor |
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| US5157475A (en) * | 1988-07-08 | 1992-10-20 | Oki Electric Industry Co., Ltd. | Semiconductor device having a particular conductive lead structure |
| US20080164543A1 (en) * | 2007-01-04 | 2008-07-10 | Stmicroelectronics S.R.L. | Package, in particular for MEMS devices and method of making same |
| US20120091594A1 (en) * | 2010-10-18 | 2012-04-19 | Christof Landesberger | Method of Producing a Chip Package, and Chip Package |
| CN103400826A (en) * | 2013-06-21 | 2013-11-20 | 三星半导体(中国)研究开发有限公司 | Semiconductor package and preparation method thereof |
| CN103579171A (en) * | 2013-10-11 | 2014-02-12 | 三星半导体(中国)研究开发有限公司 | Semiconductor packaging piece and manufacturing method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111970417A (en) * | 2019-05-20 | 2020-11-20 | 三星电机株式会社 | Camera module |
| US11252311B2 (en) | 2019-05-20 | 2022-02-15 | Samsung Electro-Mechanics Co., Ltd. | Camera module |
| US11706510B2 (en) | 2019-05-20 | 2023-07-18 | Samsung Electro-Mechanics Co., Ltd. | Camera module |
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| CN105405771B (en) | 2018-11-27 |
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