CN105244272A - Method for monitoring annealing equipment - Google Patents
Method for monitoring annealing equipment Download PDFInfo
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- CN105244272A CN105244272A CN201410274033.5A CN201410274033A CN105244272A CN 105244272 A CN105244272 A CN 105244272A CN 201410274033 A CN201410274033 A CN 201410274033A CN 105244272 A CN105244272 A CN 105244272A
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Abstract
The invention provides a method for monitoring annealing equipment, which comprises the steps of providing a semiconductor substrate; carrying out ion implantation on the substrate; acquiring the thickness of an amorphous semiconductor layer in the substrate after ion implantation; carrying out low temperature thermal annealing, and acquiring the thickness of the left amorphous semiconductor layer at the annealing temperature; acquiring a solid state epitaxy rate at the annealing temperature; and judging whether the solid state epitaxy rate is within a threshold range or not. The method provided by the invention is visual and effective, and can reuse a wafer through high temperature annealing.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of method for supervising of annealing device.
Background technology
In the preparation process of cmos device, in a lot of technique, thermal annealing can be used.Such as, when forming contact, in order to improve the contact effect of source and drain, the much more general silicide process that adopts reduces contact resistance, and specifically first deposit layer of metal is as, Ti, Ni etc., and then pass through the method for low temperature short annealing, form the silicide of metal and silicon, in whole process, the temperature of short annealing controls very crucial to the formation of silicide, the requirement that all can not meet technique too high or too low for temperature, therefore, annealing device is wanted accurately to control the temperature of short annealing.
Current industrial quarters mainly adopts Square resistance measurement method to monitor the state of short annealing equipment, be specially, by carrying out high annealing to the sample after rigid condition ion implantation, then the temperature of impurity is characterized with the square resistance of the method measurement sample of four point probe, if the temperature of annealing device is drifted about, square resistance also can correspondingly change.
But, for the method, in order to ensure that the impurity injected is activated and can measures, the temperature of annealing is generally more than 700 degree, and the temperature of actual silicide anneal is only about 400 degree, therefore this method effectively can not reflect the technological ability of annealing device low temperature process, on the other hand, namely sample after implantation annealing is scrapped and can not be reused, and cost consumption is very large.
Summary of the invention
Object of the present invention is intended at least solve one of above-mentioned technological deficiency, provides the method for supervising of a kind of direct reflection annealing device annealing temperature and technique.
For this reason, the invention provides following technical scheme:
A method for supervising for annealing device, comprising:
Semiconductor substrate is provided;
Ion implantation is carried out to substrate;
Obtain the thickness of the substrate noncrystal semiconductor layer after injecting;
Carry out Low Temperature Thermal annealing, and remain the thickness of noncrystal semiconductor layer under obtaining this annealing temperature;
Obtain the solid phase epitaxy speed under this annealing temperature;
Judge this solid phase epitaxy speed whether in threshold range.
Optionally, ion implantation is neutral ion.
Optionally, described neutral ion is Ge ion, Ar or Xe ion.
Optionally, the energy range of ion implantation is 150-200KeV, and dosage is 1E14-1E16cm
-2.
Optionally, optical film thickness meter is adopted to measure, to obtain the thickness of noncrystal semiconductor layer.
Optionally, remain the thickness of noncrystal semiconductor layer under this annealing temperature of acquisition after, also step is comprised:
Carry out high-temperature thermal annealing, with make noncrystal semiconductor layer again crystallization for crystalline state.
The method for supervising of the annealing device that the embodiment of the present invention provides, utilize Semiconductor substrate can form unformed amorphous characteristic on surface after ion implantation, by the thickness of the thickness and residue noncrystal semiconductor layer after annealing that obtain this amorphous noncrystal semiconductor layer, obtain the solid phase epitaxy speed under this annealing temperature, by judging this solid phase epitaxy speed whether in threshold range, can learn whether annealing device is in normal condition.
In addition, after monitoring, carry out high temperature high-temperature thermal annealing, with make noncrystal semiconductor layer again crystallization for crystalline state, this wafer can be reused, cost-saving.
Accompanying drawing explanation
The present invention above-mentioned and/or additional aspect and advantage will become obvious and easy understand from the following description of the accompanying drawings of embodiments, wherein:
Fig. 1 is the schematic flow sheet of the method for supervising of annealing device according to the embodiment of the present invention.
Embodiment
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the embodiment be described with reference to the drawings, only for explaining the present invention, and can not limitation of the present invention being interpreted as.
In the present invention, the method for supervising of the annealing device provided, judge that whether annealing device is abnormal by obtaining solid phase epitaxy speed, the method is directly perceived, effective, and can be reused by wafer by high annealing.
For a better understanding of the present invention, be described in detail below with reference to flow chart 1 pair of specific embodiment.
First, Semiconductor substrate is provided.
The well-regulated crystalline state of described Semiconductor substrate tool.Described Semiconductor substrate can be Si substrate, Ge substrate, SiGe substrate, SOI (silicon-on-insulator, SiliconOnInsulator) or GOI (germanium on insulator, GermaniumOnInsulator) etc.In other embodiments, described Semiconductor substrate can also be the substrate comprising other elemental semiconductors or compound semiconductor, such as GaAs, InP or SiC etc., it can also be laminated construction, such as Si/SiGe etc., can also other epitaxial structures, such as SGOI (silicon germanium on insulator) etc.In the present embodiment, described Semiconductor substrate is body silicon substrate.
Then, ion implantation is carried out to substrate.
Before not carrying out ion implantation, Semiconductor substrate is the crystalline state of rule, after carrying out ion implantation, can form amorphous semiconductor in the substrate, i.e. noncrystal semiconductor layer.
Neutral ion can be adopted to inject, and in the present embodiment, adopt the neutral ions such as Ge ion, Ar or Xe to inject, the energy range of ion implantation is 150-200KeV, and dosage is 1E14-1E16cm
-2, the noncrystal semiconductor layer being roughly 100nm can be formed on the surface of substrate.Adopt neutral ion to inject, can avoid can not polluting cavity because of outdiffusion when annealing process.
Then, the thickness of the substrate noncrystal semiconductor layer after injecting is obtained.
Because crystal is different with the refractive index of amorphous, optical film thickness meter can be adopted to measure, obtain the thickness of noncrystal semiconductor layer in substrate.
Then, carry out Low Temperature Thermal annealing, and remain the thickness of noncrystal semiconductor layer under obtaining this annealing temperature.
In the present invention, Low Temperature Thermal annealing refers to that annealing temperature is lower than 600 DEG C.In the present embodiment, the temperature of annealing is 400 DEG C, and annealing time is 30s.After Low Temperature Thermal annealing, the noncrystal semiconductor layer of part reverts to crystal layer.Then, after annealing under obtaining this annealing temperature, the thickness of the noncrystal semiconductor layer of remainder, similarly, can adopt optical film thickness meter to measure, obtain the thickness of remaining noncrystal semiconductor layer in substrate.
Then, the solid phase epitaxy speed under this annealing temperature is obtained.
Solid phase epitaxy speed, the i.e. thickness of amorphous layer epitaxial recrystalization under lower than the fusing point of this material or eutectic temperature in the unit interval, in the present invention, the thickness being the noncrystal semiconductor layer after ion implantation remains the difference of the thickness of noncrystal semiconductor layer and the ratio of annealing time with annealing is rear.
Solid phase epitaxy is the process of amorphous material re-crystallizes under cold service, solid phase epitaxy speed is relevant to the temperature and time of annealing, temperature is higher, the speed of solid phase epitaxy is faster, therefore directly can be reflected the temperature of annealing by the speed of solid phase epitaxy, thus realize the monitoring to low temperature annealing process and equipment thereof.
Then, this solid phase epitaxy speed is judged whether in threshold range.
By judging this solid phase epitaxy speed whether in threshold range, thus confirm whether annealing device occurs exception, needs to re-start correction.Normally, can be contrasted by the solid phase epitaxy speed that calculates and solid phase epitaxy speed reference value, when the deviation of the two is greater than certain proportion, namely think that this solid phase epitaxy speed exceeds threshold range, the temperature of annealing device may offset, and needs again to correct, when the deviation of the two is less than certain proportion, namely think that this solid phase epitaxy speed is within threshold range, annealing device is in normal condition.
In the present embodiment, solid phase epitaxy speed reference value Vref can empirical value by experiment obtain, and threshold value is Vref ± 3%, when the deviation of the solid phase epitaxy speed calculated and solid phase epitaxy speed reference value is more than 3%, thinks unit exception.
Then, high-temperature thermal annealing can be carried out to this substrate further, with make noncrystal semiconductor layer again crystallization for crystalline state.
In the present invention, high-temperature thermal annealing refers to that annealing temperature is higher than 900 DEG C.
In the present embodiment, adopt the high-temperature thermal annealing of 1000 DEG C, until noncrystal semiconductor layer crystallization again, like this, this wafer can re-use, cost-saving.
Although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention.Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (6)
1. a method for supervising for annealing device, is characterized in that, comprising:
Semiconductor substrate is provided;
Ion implantation is carried out to substrate;
Obtain the thickness of the substrate noncrystal semiconductor layer after injecting;
Carry out Low Temperature Thermal annealing, and remain the thickness of noncrystal semiconductor layer under obtaining this annealing temperature;
Obtain the solid phase epitaxy speed under this annealing temperature;
Judge this solid phase epitaxy speed whether in threshold range.
2. method for supervising according to claim 1, is characterized in that, ion implantation be neutral ion.
3. method for supervising according to claim 2, is characterized in that, described neutral ion is Ge ion, Ar or Xe ion.
4. method for supervising according to claim 3, is characterized in that, the energy range of ion implantation is 150-200KeV, and dosage is 1E14-1E16cm
-2.
5. method for supervising according to claim 1, is characterized in that, adopts optical film thickness meter to measure, to obtain the thickness of noncrystal semiconductor layer.
6. method for supervising according to claim 1, is characterized in that, after remaining the thickness of noncrystal semiconductor layer, also comprises step under this annealing temperature of acquisition:
Carry out high-temperature thermal annealing, with make noncrystal semiconductor layer again crystallization for crystalline state.
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| CN201410274033.5A CN105244272A (en) | 2014-06-18 | 2014-06-18 | Method for monitoring annealing equipment |
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| CN201410274033.5A CN105244272A (en) | 2014-06-18 | 2014-06-18 | Method for monitoring annealing equipment |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112928016A (en) * | 2021-02-01 | 2021-06-08 | 广东省大湾区集成电路与系统应用研究院 | Rapid annealing process for wafer |
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| US20020051481A1 (en) * | 2000-11-02 | 2002-05-02 | Satoshi Shibata | Method for predicting temperature, test wafer for use in temperature prediction, and method for evaluating lamp heating system |
| US20020075936A1 (en) * | 2000-11-02 | 2002-06-20 | Satoshi Shibata | Method for predicting temperature and test wafer for use in temperature prediction |
| JP3305310B1 (en) * | 1998-12-09 | 2002-07-22 | 松下電器産業株式会社 | Temperature measurement method |
| US6475815B1 (en) * | 1998-12-09 | 2002-11-05 | Matsushita Electric Industrial Co., Ltd. | Method of measuring temperature, method of taking samples for temperature measurement and method for fabricating semiconductor device |
| CN1624884A (en) * | 2003-12-05 | 2005-06-08 | 中芯国际集成电路制造(上海)有限公司 | Monitoring low-temp quick thermal annealing process by ion implanted chip |
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2014
- 2014-06-18 CN CN201410274033.5A patent/CN105244272A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6128084A (en) * | 1997-06-11 | 2000-10-03 | Matsushita Electronics Corporation | Evaluation method of semiconductor layer, method for fabricating semiconductor device, and storage medium |
| JP3305310B1 (en) * | 1998-12-09 | 2002-07-22 | 松下電器産業株式会社 | Temperature measurement method |
| US6475815B1 (en) * | 1998-12-09 | 2002-11-05 | Matsushita Electric Industrial Co., Ltd. | Method of measuring temperature, method of taking samples for temperature measurement and method for fabricating semiconductor device |
| US20020051481A1 (en) * | 2000-11-02 | 2002-05-02 | Satoshi Shibata | Method for predicting temperature, test wafer for use in temperature prediction, and method for evaluating lamp heating system |
| US20020075936A1 (en) * | 2000-11-02 | 2002-06-20 | Satoshi Shibata | Method for predicting temperature and test wafer for use in temperature prediction |
| CN1624884A (en) * | 2003-12-05 | 2005-06-08 | 中芯国际集成电路制造(上海)有限公司 | Monitoring low-temp quick thermal annealing process by ion implanted chip |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112928016A (en) * | 2021-02-01 | 2021-06-08 | 广东省大湾区集成电路与系统应用研究院 | Rapid annealing process for wafer |
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Application publication date: 20160113 |