CN105164805A - 具有集成电路芯片和电压调谐器的半导体封装件 - Google Patents

具有集成电路芯片和电压调谐器的半导体封装件 Download PDF

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CN105164805A
CN105164805A CN201380075749.6A CN201380075749A CN105164805A CN 105164805 A CN105164805 A CN 105164805A CN 201380075749 A CN201380075749 A CN 201380075749A CN 105164805 A CN105164805 A CN 105164805A
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绍·Ht·武
安迪·H·甘
李晓宇
马修·H·克莱
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Xilinx Inc
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Abstract

一种半导体封装件是包含中介体(208、326、416、516)以及被设置在所述中介体上而且经由所述中介体相互耦接的多个集成电路(IC)芯片(102-108、232-234、322-324、412-414、512-514)。第一IC芯片(102、232、322、412、512)具有的频率速度等级大于所述IC芯片的另一芯片(104-108、234、324、414、514)的频率速度等级。多个可编程电压调谐器(110-116、202-204、312及316、402-404、502-504)分别耦接至所述多个IC芯片。第一电压调谐器(110、202、312、402、502)耦接至所述第一IC芯片(102、232、322、412、512)，并且所述第一电压调谐器经过编程以降低至所述第一电压调谐器的电压输入的电压位准，并且输出经降低电压至所述第一IC芯片。

Description

具有集成电路芯片和电压调谐器的半导体封装件
技术领域
本揭露内容大致是有关于多芯片半导体封装件，其具有带不同频率速度额定的芯片。
背景技术
具有相同功能及类型的电子装置经常以不同的速度额定(例如，能够在不同的频率频率下运作)来销售。某些此种装置可能具有多个堆栈在一封装件中的具有相同类型及功能的集成电路(IC)芯片。这些具有相同类型的IC芯片可以是已经根据相同的设计规格，但是由于制造的变异，所述芯片可能具有不同的最大可达到的操作频率频率(或是频率速度额定)。
为在封装件中的IC芯片之间维持适当的建立(setup)时间及保持(hold)时间，在针对于所述封装件选择的IC芯片之间的速度上的差异不能过大。因此，所制成的IC芯片可被排序成群组，其中每一个群组具有在针对于每一个群组的适当范围内的速度的IC芯片。所述群组有时被称为类别(bin)。在一类别中的IC芯片可具有许多不同速度，尽管其全部都落在该类别的指定速度范围内。每一个装置或封装件可利用来自特定类别的多个芯片来加以建构。从一类别的IC芯片所建构的封装件可具有的速度等级不同于与从另一类别的IC芯片所建构的封装件的速度等级。
在一类别中的IC芯片的速度范围可允许来自所述类别的IC芯片的任一个能够使用在建构一封装件中，而不危害到适当的建立时间及保持时间。然而，为符合所述封装件的功率额定，来自一类别中的慢速IC芯片(具有较低的频率速度额定的芯片)对于快速IC芯片(具有较高的频率速度额定的芯片)的某一比例可被用在每一个封装件中。例如，一封装件可利用来自一类别中的三个较慢IC芯片及一个较快IC芯片来加以建构。然而，在所述类别中的较慢IC芯片与较快IC芯片的比例可能并不与用于所述封装件的所要比例相称的。若有过多的快速芯片及过少慢速的芯片，则某些快速芯片可能会被报废，此系导致增高的制造成本。
发明内容
一种半导体封装件是包含中介体及被设置在所述中介体上而且经由所述中介体相互耦接的多个集成电路(IC)芯片。所述多个IC芯片的第一IC芯片具有频率速度额定大于所述IC芯片的另一IC芯片的频率速度额定。多个可编程电压调谐器分别耦接至所述多个IC芯片。所述多个电压调谐器的第一电压调谐器耦接至所述第一IC芯片，并且所述第一电压调谐器经过编程以降低至所述第一电压调谐器的电压输入的电压位准，并且输出经降低电压至所述第一IC芯片。
在某些此种半导体封装件中，下列的一或多个可成立：所述多个电压调谐器中的所述第一电压调谐器除外的电压调谐器可被编程，以在无改变下提供所述输入电压至所述相应的IC芯片；所述多个电压调谐器的每一个电压调谐器都可被编程以降低至所述电压调谐器的电压输入，并且输出所述经降低电压至所述相应的IC芯片；所述电压调谐器可被设置在所述中介体中；所述电压调谐器可被设置在所述多个IC芯片中；所述半导体封装件可进一步包括封装基板，其中所述中介体被设置在所述封装基板上并且所述电压调谐器被设置在所述封装基板上，并且其中所述电压调谐器可被引线接合至所述IC芯片；所述IC芯片可以是在功能上等同的；所述IC芯片可以是现场可编程门阵列；且/或所述IC芯片可以是在功能上不同的。
一种建构电子系统的方法亦被提出。所述方法是包含判断多个IC芯片的相应的频率速度额定。所述多个IC芯片的第一IC芯片经过判断为具有频率速度额定大于所述IC芯片的另一IC芯片的频率速度额定。针对于所述多个IC芯片的相应的电压位准是根据所述相应的频率速度额定及所述电子系统的目标功率分布(profile)而加以判断。所述IC芯片被附接至中介体，并且在所述中介体上的IC芯片的每一个耦接至多个电压调谐器的相应的电压调谐器。每一相应的电压调谐器经过编程以供应所述相应的电压位准至所述中介体上的IC芯片中的一个。
在某些此种方法中，下列的一或多个可以成立：所述多个IC芯片的第一IC芯片可具有频率速度额定是大于所述IC芯片的另一IC芯片的频率速度额定，所述IC芯片至相应的电压调谐器的耦接可包含将所述多个电压调谐器的第一电压调谐器耦接至所述中介体上的第一IC芯片，并且所述编程可包含编程所述第一电压调谐器以降低输入电压位准，并且输出经降低电压至所述第一IC芯片；所述编程可包含编程所述多个电压调谐器中的所述第一电压调谐器除外的电压调谐器，以在无改变下提供所述输入电压至所述相应的IC芯片；且/或所述编程可包含编程所述多个电压调谐器中的所述第一电压调谐器除外的每一个电压调谐器以降低输入电压，并且输出所述经降低电压至所述相应的IC芯片。
一种电子系统亦被提出。所述系统包含印刷电路板及安装在所述印刷电路板上的半导体封装件。所述半导体封装件包含封装基板、被设置在所述封装基板上的中介体、及被设置在所述中介体上而且经由所述中介体相互耦接的多个集成电路(IC)芯片。所述多个IC芯片的第一IC芯片具有频率速度等级大于所述IC芯片的另一IC芯片的频率速度等级。多个可编程电压调谐器是设置在所述印刷电路板上，并且分别耦接至所述多个IC芯片。所述多个电压调谐器的第一电压调谐器耦接至所述第一IC芯片，并且所述第一电压调谐器经过编程以降低至所述第一电压调谐器的电压输入的电压位准，并且输出经降低电压至所述第一IC芯片。
从以下的具体实施方式及权利要求书的考虑将会体认到其它特点。
附图说明
所述电路及方法的各种特点及特征在检视以下的具体实施方式及在参考书明书附图后将变为明显的，其中：
图1展示IC封装件，其中所述封装件的每一个IC芯片是具有受到相应的电压调谐器控制的功率；
图2展示具有多个IC芯片的IC封装件的横截面图，并且所述IC芯片的每一个是具有相应的电压调谐器及可编程控制组件；
图3展示具有多个IC芯片的IC封装件的横截面图，并且所述IC芯片的每一个是具有被设置于其中的相应的电压调谐器及可编程的控制组件；
图4展示具有多个IC芯片的IC封装件的横截面图，并且相应的电压调谐器经过附接至封装基板；
图5展示具有多个IC芯片的IC封装件的横截面图，并且相应的电压调谐器是被附接至印刷电路板；
图6一种用于制造具有IC芯片及相关的电压调谐器的半导体封装件的制程的流程图；以及
图7范例可编程逻辑IC的方块图，其可由根据上述教示的一或多个IC芯片所做成的。
具体实施方式
为解决和在一类别中的快速芯片相对于慢速芯片的非所要分布相关的问题，被建构成具有来自所述类别的多个IC芯片的半导体封装件可被做成为包含用于所述IC芯片的相应的电压调谐器。所述电压调谐器对于在封装件中的每一个IC芯片的功率消耗提供控制，相较于原本在无所述电压调谐器下所容许的，其借此容许更多的较快芯片能够被使用在封装件中。例如，若三个较慢IC芯片及一个较快IC芯片将被用在建构IC封装件以满足功率额定，但是在所述类别中有过多的较快芯片及过少的较慢芯片来符合此比例，则来自所述类别的较快芯片可被用来取代在所述封装件中的较慢芯片。在所述封装件中的较快芯片的输入电压可通过所述电压调谐器而被降低，以便于降低那些较快芯片的功率消耗。由于降低所述输入电压会降低IC芯片的功率消耗及操作速度是已知的，因此所述较快芯片可加以控制来运作成为如同较慢芯片。
图1展示IC封装件100，其中所述封装件的每一个IC芯片具有受到相应的电压调谐器控制的功率。所述范例的封装件是包含IC芯片102、104、106及108，其分别具有受到电压调谐器110、112、114及116控制的供应电压。如同通过控制组件118、120、122及124所展示的，每一个电压调谐器是个别可编程的。电源通过电源供应器线130而被提供至所述电压调谐器。
所述IC芯片102、104、106及108可被设置在中介体(未显示)上并且通过所述中介体来相互耦接。尽管四个IC芯片被展示，但将会体认到的是，封装件可根据应用需求而包含更多或是较少的IC芯片。在图1中所示的封装件可代表一个应用，其中为达成所述封装件的所要功率额定，较佳的是三个较慢IC芯片相对于一个较快IC芯片的比例。若所述封装件被建构所来自的类别中有过少的较慢IC芯片及过多的较快IC芯片，则一个较快芯片可替代所要的较慢芯片中的一或多个。例如，假设对于所述应用而言，在所述类别中较慢相对较快的IC芯片的分布较佳是3：1，则所述封装件原本可利用较慢IC芯片的IC芯片102、104和106及较快IC芯片的IC芯片108来加以做成。然而，若在所述类别中较慢相对于较快的IC芯片的分布是1：1，而不是3：1，则不只IC芯片108可以是一较快IC芯片。例如，IC芯片102、104或106中的一或多个亦可以是一较快的IC芯片。耦接至属于较快芯片的IC芯片102、104及106中的一或多个的电压调谐器可被编程以降低至所述一或多个芯片的供应电压，此导致所述封装件具有所要的功率额定。耦接至所述较慢芯片的电压调谐器可被编程，以在无改变下将所述输入供应电压传送至所述相应的IC芯片。
将会体认到的是，所述电压调谐器及控制组件的实施方式可根据应用需求而变化。在范例的实施方式中，每一个电压调谐器可以是一系列的一或多个电阻器，其通过在所述控制组件中的一经编程值来选择。所述控制组件例如可以是PROM、EPROM或EEPROM、或EFUSE。
所述IC芯片彼此在功能上可以是不同的、或在功能上可以是等同的。例如，所述IC芯片可以是不同的特殊应用集成电路(ASIC)芯片、或者可以是现场可编程门阵列(FPGA)芯片的在功能上等同的实例。
若在一类别中并没有较慢IC芯片结合在所述类别中的较快IC芯片来使用时，则所有较快芯片都可被用在制造半导体封装件中。在所述封装件中的所有IC芯片的电压调谐器都可被编程，以降低至所述IC芯片的供应电压到适当位准。
图2展示具有多个IC芯片的IC封装件的横截面图，并且所述IC芯片的每一个是具有相应的电压调谐器及可编程控制组件。电压调谐器202及204被设置在中介体208(或是母芯片)的电路层206中。控制组件210及212也被设置在所述中介体的电路层中。
所述半导体封装件是包含中介体208、子IC芯片232和234、及封装基板218。尽管只有两个IC芯片232及234被展示，但将会体认到的是在不同实施方式中，额外芯片可内含在所述封装件中。所述组件通常被囊封在封装材料(未显示)中。所述半导体封装件通过焊料球格数组(BGA)224而被安装到印刷电路板222。所述球格数组及相关基板及印刷电路板的接触垫提供在所述半导体封装件与外部环境之间的电性及机械式的连接。
通过焊料凸块数组226而被安装到封装基板218的中介体208包含通常是硅的半导体基板，其提供基底给电路层206及形成在所述芯片的面或是底表面上的集成电路。硅通孔(TSV)(例如，TSV228)被形成在硅中，以提供在所述电路层206与位于背面或上表面的接触垫230之间的电性导通。
子IC芯片232及234分别具有集成电路层236及238。每一个子IC芯片的面通常布满有接触垫数组(例如，接触垫240)，其耦接至所述集成电路层。焊料凸块(例如，焊料凸块242)提供在子IC芯片的集成电路与所述中介体208的集成电路之间的电性连接。
所述电压调谐器202及204经由焊料凸块数组226的焊料凸块中的一或多个、封装基板218、凸块数组224的焊料凸块、及印刷电路板222来接收供应电压。所述供应电压可经由所述中介体的电路层206而被散布至所述电压调谐器。电压调谐器202的输出节点(未显示)连接至TSV220，而TSV220通过焊料凸块252及接触垫254耦接至IC芯片232。所述接触垫254连接至IC芯片232的电路层236，而所述接触垫及焊料凸块252可被称为所述IC芯片的电源节点、凸块或是接脚。电压调谐器204的输出节点(未显示)类似地通过TSV262、焊料凸块264及接触垫266耦接至IC芯片234。
所述控制组件210及212例如可通过扫描测试电路、或通过编程EFUSE来加以编程。
图3展示具有多个IC芯片的IC封装件的横截面图，并且所述IC芯片的每一个具有被设置于其中的相应的电压调谐器及可编程控制组件。电压调谐器312和316及可编程控制组件314及318被设置在IC芯片322及324中。所述IC芯片322及324被安装在中介体326上，而所述中介体326被安装在封装基板328上。供应电压通过焊料连接332、TSV334、在数组336中的焊料连接、封装基板328的通孔及绕线(未显示)、在数组338中的焊料连接、及印刷电路板330的通孔及绕线(未显示)而被输入到电压调谐器312。所述IC芯片被附接至所述中介体、所述中介体被附接至所述封装基板、及所述封装基板被附接至所述印刷电路板330所使用的结构可类似于在图2中所示并且于上文所述的彼等者。
所述电压调谐器312及可编程控制组件314被形成在IC芯片322中而作为电路层340的部分。类似地，所述电压调谐器316及可编程的控制组件318被形成在IC芯片324中而作为电路层342的部分。电压调谐器312的输入节点(未显示)从焊料连接332接收所述供应电压，并且所述电压调谐器的输出节点(未显示)耦接至在所述电路层340中的供应电压布线。在所述可编程控制组件318与电压调谐器之间的耦接由所述电路层342中的信号线所提供的。电压调谐器316及可编程控制组件318类似地被设置在IC芯片324中。所述控制组件314及318例如可通过扫描测试电路、或通过编程EFUSE来加以编程。
图4展示具有多个IC芯片的IC封装件的横截面图，并且相应的电压调谐器被附接至封装基板。电压调谐器402和404及可编程控制组件406及408被设置在封装基板410上。IC芯片412及414被安装在中介体416上，而所述中介体416被安装在封装基板410上，所述封装基板410被安装在印刷电路板418上。所述IC芯片被附接至所述中介体、所述中介体被附接至所述封装基板、及所述封装基板被附接至所述印刷电路板418所使用的结构可类似于在图2中所示并且于上文所述的彼等者。
引线420将电压调谐器402的输出节点(未显示)连接至IC芯片412的电源垫422。所述电源垫通过TSV426来连接至IC芯片412的电路层424。电压调谐器404类似地连接至IC芯片414。供应电压通过通孔428、电源线430、通孔432、在数组434中的焊料连接、及印刷电路板418的通孔及绕线(未显示)而被输入到电压调谐器402。供应电压类似地被提供作为电压调谐器404的输入。
所述电压调谐器402和404及可编程控制组件406和408被表面安装到封装基板410。所述控制组件例如可通过扫描测试电路、或通过编程EFUSE来加以编程。
图5展示具有多个IC芯片的IC封装件的横截面图，并且相应的电压调谐器被附接至印刷电路板。电压调谐器502和504及可编程控制组件506和508被设置在印刷电路板510上。IC芯片512及514被安装在中介体516上，而所述中介体516被安装在封装基板518上，封装基板518则被安装在印刷电路板510上。所述IC芯片被附接至所述中介体、所述中介体被附接至所述封装基板、以及所述封装基板被附接至所述印刷电路板510所使用的结构可类似于在图2中所示并且于上文所述的彼等者。
印刷电路线路532将电压调谐器502的输出节点(未显示)连接至焊料连接534。所述供应电压通过印刷电路线路536来连接至所述输入节点(未显示)。印刷电路线路538将电压调谐器504的输出节点(未显示)连接至焊料连接540。所述供应电压通过印刷电路线路542来连接至所述输入节点(未显示)，而印刷电路线路542可通过另一印刷电路线路(未显示)来连接至线路536。
供应电压通过焊料连接544中的一个、通孔(例如，通孔546)、焊料连接548中的一个、在封装基板518中的一或多个通孔及导线(未显示)、及连接至电压调谐器502的输出节点的焊料连接534，而被输入到IC芯片512。供应电压类似地被提供至IC芯片514。
所述电压调谐器502和504及可编程控制组件506和508被表面安装到印刷电路板510。所述控制组件例如可通过扫描测试电路、或通过编程EFUSE来加以编程。
图6是一种用于制造具有IC芯片及相关电压调谐器的半导体封装件的制程的流程图。在区块602，多个IC芯片被制造。在范例应用中，所述芯片可被建构为相同规格。在区块604，每一个芯片的速度等级被判断出。所述速度等级可以是所述IC芯片可据以操作的最大频率速度。在区块606，根据所述芯片的相应速度等级及将被建构的半导体封装件的目标功率分布，判断出用于将被用来制造所述封装件的芯片的所要供应电压位准。所述目标功率分布可指明所述半导体封装件应该消耗的最大功率位准。为符合所述目标功率分布，至所述IC芯片中的一或多个的电压位准可被降低。在区块608，封装件利用堆栈在中介体上的芯片来加以建构，而所述芯片具有耦接至相应的电压调谐器的电源节点。在区块610，所述电压调谐器经过编程以提供所要位准的供应电压至所述IC芯片。
图7是范例的可编程逻辑IC的方块图，其可由根据以上所述教示的一或多个IC芯片所做成的。所述范例的可编程IC是现场可编程的门阵列(FPGA)。然而，在此所述的结构及方法并不限于FPGA或其它可编程逻辑IC，而可被应用至其它IC，其包含非可编程IC、部分可编程IC、或可编程、非可编程或部分可编程IC的任意组合。
FPGA可在数组中包含数种不同类型的可编程逻辑区块。例如，图7例示一种FPGA架构(700)，其包含大量不同的可编程单元片(tile)，其包含数千兆位收发器(MGT701)、可配置逻辑区块(CLB702)、随机存取内存区块(BRAM703)、输入/输出区块(IOB704)、配置及频率逻辑(CONFIG/CLOCKS705)、数字信号处理区块(DSP706)、例如频率埠的专用输入/输出区块(I/O707)、及其它可编程逻辑708，例如数字频率管理器、模拟至数字转换器、系统监视逻辑等等。某些FPGA亦包含专用处理器区块(PROC710)及内部和外部重新配置端口(未显示)。
在某些FPGA中，每一个可编程单元片是包含可编程互连组件(INT711)，其具有标准化联机以往返于每一个相邻单元片中的对应互连组件。因此，所述可编程互连组件一起用以实施用于所举例说明的FPGA的可编程互连结构。所述可编程互连组件711亦包含往返于相同单元片内的可编程逻辑组件的联机，即如同内含在图7的顶端的例子所展示。
例如，CLB702可包含可配置逻辑组件CLE712，其可被编程以实施用户逻辑加上单一可编程互连组件INT711。除了一或多个可编程互连组件以外，一BRAM703还可包含BRAM逻辑组件(BRL713)。通常，内含在单元片中的互连组件的数量是依据所述单元片的宽度而定。在所例示FPGA中，BRAM单元片是具有和五个CLB相同的宽度，但是其它数量(例如，四个)亦可被利用。除了适当数量的可编程互连组件以外，DSP单元片706还可包含DSP逻辑组件(DSPL714)。除了所述可编程的互连组件711的一实例以外，IOB704还可例如包含输入/输出逻辑组件(IOL715)的两个实例。如同对本领域技术人士将会明显的是，例如连接至所述I/O逻辑组件715的实际的I/O垫利用分层堆积在各种例示的逻辑区块上的金属来制造，并且通常并未被局限于所述输入/输出逻辑组件715的区域。
在所例示FPGA中，靠近所述芯片(在图7中以阴影展示)的中心的水平区域被使用于配置、频率、及其它控制逻辑。从此水平区域延伸的垂直区域709被用来横跨所述FPGA的广度以分布所述频率及配置的信号。
利用在图7中所例示架构的某些FPGA包含额外逻辑区块，其中断用以构成所述FPGA的一大部分的规则列结构。所述额外逻辑区块可以是可编程区块及/或专用逻辑。例如，在图7中所示的处理器区块PROC710是跨越数个列的CLB及BRAM。
注意到的是，图7欲仅例示范例的FPGA架构而已。在一列中的逻辑区块的数目、所述列的相对高度、列的数量及顺序、内含在所述列中的逻辑区块类型、所述逻辑区块的相对尺寸、及内含在图7的顶端的互连/逻辑的实施方式纯粹是范例而已。例如，在一实际FPGA中，超过一个相邻列的CLB通常内含在所有出现CLB之处，以使得用户逻辑的有效率实施变得容易。
尽管特点及特征在某些情形中可能是在个别图式中加以描述，但将会体认到的是，来自一个图的特征可和另一图的特征组合，即使所述组合并未被明确地展示、或被明确地叙述为一组合。
所揭露的特征被认为可应用于各种半导体封装件。从所述发明说明的考虑，其它特点及特征对于熟习此项技术人士而言将会是明显的。所欲的是所述发明说明及图式只被视为例子而已，其中本发明的真正范畴是通过以下的权利要求加以指出。

Claims (15)

1.一种半导体封装件，其包括：
中介体；
多个集成电路(IC)芯片，其被设置在所述中介体上而且经由所述中介体相互耦接，所述多个集成电路芯片的第一集成电路芯片具有的频率速度额定大于所述集成电路芯片的另一集成电路芯片的频率速度额定；以及
多个可编程电压调谐器，其分别耦接至所述多个集成电路芯片，其中：
所述多个电压调谐器的第一电压调谐器耦接至所述第一集成电路芯片；且
所述第一电压调谐器经过编程以降低至所述第一电压调谐器的电压输入的电压位准，并且输出经降低电压至所述第一集成电路芯片。
2.根据权利要求1所述的半导体封装件，其中所述多个电压调谐器中的所述第一电压调谐器除外的电压调谐器经过编程，以在无改变下提供所述输入电压至相应的集成电路芯片。
3.根据权利要求1所述的半导体封装件，其中所述多个电压调谐器的每一个电压调谐器经过编程以降低至所述电压调谐器的电压输入，并且输出所述经降低电压至相应的集成电路芯片。
4.根据权利要求1-3中任一项所述的半导体封装件，其中所述电压调谐器被设置在所述中介体中。
5.根据权利要求1-3中任一项所述的半导体封装件，其中所述电压调谐器被设置在所述多个集成电路芯片中。
6.根据权利要求1-3中任一项所述的半导体封装件，其进一步包括：
封装基板；
其中所述中介体被设置在所述封装基板上，并且所述电压调谐器被设置在所述封装基板上。
7.根据权利要求6所述的半导体封装件，其中所述电压调谐器被引线接合至所述集成电路芯片。
8.根据权利要求1-7中任一项所述的半导体封装件，其中所述集成电路芯片在功能上是等同的。
9.根据权利要求1-7中任一项所述的半导体封装件，其中所述集成电路芯片是现场可编程门阵列。
10.根据权利要求1-7中任一项所述的半导体封装件，其中所述集成电路芯片在功能上是不同的。
11.一种建构一电子系统的方法，其包括：
判断多个集成电路芯片的相应的频率速度额定；
根据所述相应的频率速度额定及所述电子系统的目标功率分布以判断用于所述多个集成电路芯片的相应的电压位准；
将所述集成电路芯片附接至中介体；
将在所述中介体上的所述集成电路芯片的每一个耦接至多个电压调谐器的相应的电压调谐器；以及
编程每一个相应的电压调谐器以供应所述相应的电压位准至所述中介体上的所述集成电路芯片中的一者。
12.根据权利要求11所述的方法，其中：
所述多个集成电路芯片的第一集成电路芯片具有的频率速度额定大于所述集成电路芯片的另一集成电路芯片的频率速度额定；
所述集成电路芯片至相应的电压调谐器的耦接包含将所述多个电压调谐器的第一电压调谐器耦接至在所述中介体上的第一集成电路芯片；以及
所述编程包含编程所述第一电压调谐器以降低输入电压位准，并且输出经降低电压至所述第一集成电路芯片。
13.根据权利要求12所述的方法，其中所述编程包含编程所述多个电压调谐器中的所述第一电压调谐器除外的电压调谐器，以在无改变下提供所述输入电压至所述相应的集成电路芯片。
14.根据权利要求12所述的方法，其中所述编程是包含编程所述多个电压调谐器中的所述第一电压调谐器除外的每一个电压调谐器以降低输入电压，并且输出所述经降低电压至所述相应的集成电路芯片。
15.一种电子系统，其包括：
印刷电路板；
半导体封装件，其被安装在所述印刷电路板上，其中所述半导体封装件包含：
封装基板；
中介体，其被设置在所述封装基板上；以及
多个集成电路(IC)芯片，其被设置在所述中介体上而且经由所述中介体相互耦接，所述多个集成电路芯片的第一集成电路芯片具有的频率速度额定大于所述集成电路芯片的另一集成电路芯片的频率速度额定；以及
多个可编程电压调谐器，其被设置在所述印刷电路板上并且分别耦接至所述多个集成电路芯片，其中：
所述多个电压调谐器的第一电压调谐器耦接至所述第一集成电路芯片；且
所述第一电压调谐器经过编程以降低至所述第一电压调谐器的电压输入的电压位准，并且输出经降低电压至所述第一集成电路芯片。
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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9136842B2 (en) 2013-06-07 2015-09-15 Altera Corporation Integrated circuit device with embedded programmable logic
KR102100709B1 (ko) * 2013-11-29 2020-04-16 에스케이하이닉스 주식회사 반도체 칩의 스큐를 튜닝하는 반도체 시스템
US9341668B1 (en) * 2014-04-01 2016-05-17 Xilnix, Inc. Integrated circuit package testing
US10147666B1 (en) * 2014-07-31 2018-12-04 Xilinx, Inc. Lateral cooling for multi-chip packages
US9438244B2 (en) 2014-10-28 2016-09-06 Xilinx, Inc. Circuits for and methods of controlling power within an integrated circuit
US9847323B1 (en) * 2015-08-19 2017-12-19 Xilinx, Inc. Integrated circuit package having voltage regulation circuitry
US9882562B1 (en) * 2016-12-07 2018-01-30 Xilinx, Inc. Rotated integrated circuit die and chip packages having the same
US11282776B2 (en) 2018-02-22 2022-03-22 Xilinx, Inc. High density routing for heterogeneous package integration
US11107751B2 (en) * 2018-03-27 2021-08-31 Intel Corporation Face-to-face through-silicon via multi-chip semiconductor apparatus with redistribution layer packaging and methods of assembling same
US11031373B2 (en) 2019-03-29 2021-06-08 International Business Machines Corporation Spacer for die-to-die communication in an integrated circuit

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001068606A (ja) * 1999-08-30 2001-03-16 Hitachi Ltd 自動車用制御コントロールユニットおよびその製造方法並びにｉｃチップパッケージ
US20080178023A1 (en) * 2007-01-18 2008-07-24 International Business Machines Corporation Method and system for independent processor voltage supply
TW201037834A (en) * 2008-09-23 2010-10-16 Globalfoundries Us Inc Interposer including voltage regulator and method therefor
US20120147567A1 (en) * 2010-12-09 2012-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Networking Packages Based on Interposers

Family Cites Families (103)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6159515A (ja) * 1984-08-31 1986-03-27 Nippon Denso Co Ltd ワンチツプマイクロコンピユ−タ
US4698760A (en) 1985-06-06 1987-10-06 International Business Machines Method of optimizing signal timing delays and power consumption in LSI circuits
US5157618A (en) 1988-03-10 1992-10-20 Cirrus Logic, Inc. Programmable tiles
US5399898A (en) 1992-07-17 1995-03-21 Lsi Logic Corporation Multi-chip semiconductor arrangements using flip chip dies
JP3253389B2 (ja) 1992-03-31 2002-02-04 株式会社東芝 半導体集積回路装置
US5461338A (en) 1992-04-17 1995-10-24 Nec Corporation Semiconductor integrated circuit incorporated with substrate bias control circuit
US5654898A (en) 1993-05-10 1997-08-05 Cascade Design Automation Corporation Timing-driven integrated circuit layout through device sizing
KR0169157B1 (ko) 1993-11-29 1999-02-01 기다오까 다까시 반도체 회로 및 mos-dram
US5504440A (en) 1994-01-27 1996-04-02 Dyna Logic Corporation High speed programmable logic architecture
US5742179A (en) 1994-01-27 1998-04-21 Dyna Logic Corporation High speed programmable logic architecture
US5487033A (en) 1994-06-28 1996-01-23 Intel Corporation Structure and method for low current programming of flash EEPROMS
US5742178A (en) 1994-09-14 1998-04-21 Xilinx, Inc. Programmable voltage stabilizing circuit for a programmable integrated circuit device
US6272668B1 (en) 1994-12-14 2001-08-07 Hyundai Electronics America, Inc. Method for cell swapping to improve pre-layout to post-layout timing
US5612636A (en) 1995-01-19 1997-03-18 Texas Instruments Incorporated Short circuit power optimization for CMOS circuits
US5787011A (en) 1995-01-19 1998-07-28 Texas Instruments Incorporated Low-power design techniques for high-performance CMOS circuits
US5892961A (en) 1995-02-17 1999-04-06 Xilinx, Inc. Field programmable gate array having programming instructions in the configuration bitstream
US6269458B1 (en) 1995-02-21 2001-07-31 Nortel Networks Limited Computer system and method for diagnosing and isolating faults
US5880967A (en) 1995-05-01 1999-03-09 Synopsys, Inc. Minimization of circuit delay and power through transistor sizing
US5682062A (en) 1995-06-05 1997-10-28 Harris Corporation System for interconnecting stacked integrated circuits
US5661685A (en) 1995-09-25 1997-08-26 Xilinx, Inc. Programmable logic device with configurable power supply
US5594367A (en) 1995-10-16 1997-01-14 Xilinx, Inc. Output multiplexer within input/output circuit for time multiplexing and high speed logic
US5815004A (en) 1995-10-16 1998-09-29 Xilinx, Inc. Multi-buffered configurable logic block output lines in a field programmable gate array
US6175952B1 (en) 1997-05-27 2001-01-16 Altera Corporation Technique of fabricating integrated circuits having interfaces compatible with different operating voltage conditions
JPH1079193A (ja) 1996-07-11 1998-03-24 Toshiba Microelectron Corp 半導体装置
US5984510A (en) 1996-11-01 1999-11-16 Motorola Inc. Automatic synthesis of standard cell layouts
US5880598A (en) 1997-01-10 1999-03-09 Xilinx, Inc. Tile-based modular routing resources for high density programmable logic device
US5959466A (en) 1997-01-31 1999-09-28 Actel Corporation Field programmable gate array with mask programmed input and output buffers
US6178542B1 (en) 1997-02-24 2001-01-23 Lucent Technologies Inc. Hardware-software co-synthesis of embedded system architectures using quality of architecture metrics
US5963050A (en) 1997-02-26 1999-10-05 Xilinx, Inc. Configurable logic element with fast feedback paths
US5914616A (en) 1997-02-26 1999-06-22 Xilinx, Inc. FPGA repeatable interconnect structure with hierarchical interconnect lines
US5880620A (en) 1997-04-22 1999-03-09 Xilinx, Inc. Pass gate circuit with body bias control
US5917709A (en) 1997-06-16 1999-06-29 Eastman Kodak Company Multiple circuit board assembly having an interconnect mechanism that includes a flex connector
JP3814385B2 (ja) 1997-10-14 2006-08-30 株式会社ルネサステクノロジ 半導体集積回路装置
JP2870530B1 (ja) 1997-10-30 1999-03-17 日本電気株式会社 スタックモジュール用インターポーザとスタックモジュール
US6620731B1 (en) 1997-12-18 2003-09-16 Micron Technology, Inc. Method for fabricating semiconductor components and interconnects with contacts on opposing sides
JP3777768B2 (ja) 1997-12-26 2006-05-24 株式会社日立製作所 半導体集積回路装置およびセルライブラリを記憶した記憶媒体および半導体集積回路の設計方法
US6150724A (en) 1998-03-02 2000-11-21 Motorola, Inc. Multi-chip semiconductor device and method for making the device by using multiple flip chip interfaces
US6163168A (en) 1998-12-09 2000-12-19 Vantis Corporation Efficient interconnect network for use in FPGA device having variable grain architecture
US6184713B1 (en) 1999-06-06 2001-02-06 Lattice Semiconductor Corporation Scalable architecture for high density CPLDS having two-level hierarchy of routing resources
JP2001015603A (ja) 1999-06-29 2001-01-19 Toshiba Corp 回路動作速度の調整方法
US6590419B1 (en) 1999-10-12 2003-07-08 Altera Toronto Co. Heterogeneous interconnection architecture for programmable logic devices
US6882045B2 (en) 1999-10-28 2005-04-19 Thomas J. Massingill Multi-chip module and method for forming and method for deplating defective capacitors
US6369630B1 (en) 1999-11-24 2002-04-09 Bae Systems Information And Electronic Systems Integration Inc. Single-event upset hardened reconfigurable bi-stable CMOS latch
US6539536B1 (en) 2000-02-02 2003-03-25 Synopsys, Inc. Electronic design automation system and methods utilizing groups of multiple cells having loop-back connections for modeling port electrical characteristics
KR20080031522A (ko) 2000-02-25 2008-04-08 이비덴 가부시키가이샤 다층프린트배선판 및 다층프린트배선판의 제조방법
JP3762856B2 (ja) 2000-05-30 2006-04-05 株式会社ルネサステクノロジ 半導体集積回路装置
US7225423B2 (en) 2000-06-30 2007-05-29 Zenasis Technologies, Inc. Method for automated design of integrated circuits with targeted quality objectives using dynamically generated building blocks
US6577013B1 (en) 2000-09-05 2003-06-10 Amkor Technology, Inc. Chip size semiconductor packages with stacked dies
JP2002083001A (ja) 2000-09-06 2002-03-22 Hitachi Ltd 論理回路の設計方法及びそれに使用するセルライブラリ
WO2002057921A1 (en) 2001-01-19 2002-07-25 Hitachi,Ltd Electronic circuit device
US6630838B1 (en) 2001-01-23 2003-10-07 Xilinx, Inc. Method for implementing dynamic burn-in testing using static test signals
GB0103837D0 (en) * 2001-02-16 2001-04-04 Nallatech Ltd Programmable power supply for field programmable gate array modules
US6720643B1 (en) * 2001-02-22 2004-04-13 Rambus, Inc. Stacked semiconductor module
US6910268B2 (en) 2001-03-27 2005-06-28 Formfactor, Inc. Method for fabricating an IC interconnect system including an in-street integrated circuit wafer via
US6583645B1 (en) 2001-08-27 2003-06-24 Xilinx, Inc. Field programmable optical arrays
US6621325B2 (en) 2001-09-18 2003-09-16 Xilinx, Inc. Structures and methods for selectively applying a well bias to portions of a programmable device
JP2003110024A (ja) * 2001-09-28 2003-04-11 Mitsubishi Electric Corp 特性調停回路
US6721924B2 (en) 2001-09-28 2004-04-13 Intel Corporation Noise and power optimization in high performance circuits
JP2004128063A (ja) 2002-09-30 2004-04-22 Toshiba Corp 半導体装置及びその製造方法
US7367503B2 (en) 2002-11-13 2008-05-06 Sandisk Corporation Universal non-volatile memory card used with various different standard cards containing a memory controller
US6930510B2 (en) 2003-03-03 2005-08-16 Xilinx, Inc. FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same
US6950998B1 (en) 2003-04-22 2005-09-27 Xilinx, Inc. Place-and-route with power analysis
US7337100B1 (en) 2003-06-12 2008-02-26 Altera Corporation Physical resynthesis of a logic design
US7068072B2 (en) 2003-06-30 2006-06-27 Xilinx, Inc. Integrated circuit with interface tile for coupling to a stacked-die second integrated circuit
JP2005049970A (ja) * 2003-07-30 2005-02-24 Renesas Technology Corp 半導体集積回路
KR100537892B1 (ko) 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
US7901983B2 (en) 2004-11-10 2011-03-08 Stats Chippac, Ltd. Bump-on-lead flip chip interconnection
US7400167B2 (en) 2005-08-16 2008-07-15 Altera Corporation Apparatus and methods for optimizing the performance of programmable logic devices
JP4444732B2 (ja) 2004-05-25 2010-03-31 富士通マイクロエレクトロニクス株式会社 ライブラリの生成方法及びライブラリ生成プログラム
US7799699B2 (en) 2004-06-04 2010-09-21 The Board Of Trustees Of The University Of Illinois Printable semiconductor structures and related methods of making and assembling
EP2650906A3 (en) 2004-06-04 2015-02-18 The Board of Trustees of the University of Illinois Methods and devices for fabricating and assembling printable semiconductor elements
US7098070B2 (en) 2004-11-16 2006-08-29 International Business Machines Corporation Device and method for fabricating double-sided SOI wafer scale package with through via connections
US7765686B2 (en) 2005-03-14 2010-08-03 Ricoh Company, Ltd. Multilayer wiring structure and method of manufacturing the same
US7157372B1 (en) 2005-06-14 2007-01-02 Cubic Wafer Inc. Coaxial through chip connection
US7838997B2 (en) 2005-06-14 2010-11-23 John Trezza Remote chip attachment
US7493247B2 (en) 2005-12-07 2009-02-17 Dafca, Inc. Integrated circuit analysis system and method using model checking
US7509608B1 (en) 2006-01-30 2009-03-24 Xilinx, Inc. Integrated system noise management—clock jitter
US7412668B1 (en) 2006-01-30 2008-08-12 Xilinx, Inc. Integrated system noise management—decoupling capacitance
US7814339B2 (en) 2006-06-30 2010-10-12 Intel Corporation Leakage power estimation
US7904864B2 (en) 2006-10-07 2011-03-08 Active-Semi, Inc. Interconnect layer of a modularly designed analog integrated circuit
US8110899B2 (en) 2006-12-20 2012-02-07 Intel Corporation Method for incorporating existing silicon die into 3D integrated stack
US7605458B1 (en) 2007-02-01 2009-10-20 Xilinx, Inc. Method and apparatus for integrating capacitors in stacked integrated circuits
US7816154B2 (en) 2007-06-06 2010-10-19 Renesas Electronics Corporation Semiconductor device, a method of manufacturing a semiconductor device and a testing method of the same
US7518398B1 (en) 2007-10-04 2009-04-14 Xilinx, Inc. Integrated circuit with through-die via interface for die stacking
US7466028B1 (en) 2007-10-16 2008-12-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor contact structure
US7791175B2 (en) 2007-12-20 2010-09-07 Mosaid Technologies Incorporated Method for stacking serially-connected integrated circuits and multi-chip device made from same
US7619441B1 (en) * 2008-03-03 2009-11-17 Xilinx, Inc. Apparatus for interconnecting stacked dice on a programmable integrated circuit
JP2009237972A (ja) 2008-03-27 2009-10-15 Fujitsu Microelectronics Ltd 半導体装置、その設計方法及び設計装置
US20110036396A1 (en) 2008-04-30 2011-02-17 The Regents Of The University Of California Method and apparatus for fabricating optoelectromechanical devices by structural transfer using re-usable substrate
US8010935B2 (en) 2008-05-07 2011-08-30 Lsi Corporation Electronic design automation tool and method for optimizing the placement of process monitors in an integrated circuit
US8060843B2 (en) 2008-06-18 2011-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Verification of 3D integrated circuits
US8130044B2 (en) 2008-06-19 2012-03-06 Altera Corporation Phase-locked loop circuitry with multiple voltage-controlled oscillators
US7800238B2 (en) 2008-06-27 2010-09-21 Micron Technology, Inc. Surface depressions for die-to-die interconnects and associated systems and methods
US8082537B1 (en) 2009-01-28 2011-12-20 Xilinx, Inc. Method and apparatus for implementing spatially programmable through die vias in an integrated circuit
US7989959B1 (en) 2009-01-29 2011-08-02 Xilinx, Inc. Method of forming stacked-die integrated circuit
US8115511B2 (en) 2009-04-14 2012-02-14 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8362622B2 (en) 2009-04-24 2013-01-29 Synopsys, Inc. Method and apparatus for placing transistors in proximity to through-silicon vias
US8390035B2 (en) * 2009-05-06 2013-03-05 Majid Bemanian Massively parallel interconnect fabric for complex semiconductor devices
US8344512B2 (en) * 2009-08-20 2013-01-01 International Business Machines Corporation Three-dimensional silicon interposer for low voltage low power systems
US20110131427A1 (en) * 2009-12-02 2011-06-02 Jorgenson Joel A Power management states
US9015023B2 (en) 2010-05-05 2015-04-21 Xilinx, Inc. Device specific configuration of operating voltage
US8692561B2 (en) * 2011-08-11 2014-04-08 International Business Machines Corporation Implementing chip to chip calibration within a TSV stack
US9753516B2 (en) * 2011-12-22 2017-09-05 Intel Corporation Method, apparatus, and system for energy efficiency and energy conservation by mitigating performance variations between integrated circuit devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001068606A (ja) * 1999-08-30 2001-03-16 Hitachi Ltd 自動車用制御コントロールユニットおよびその製造方法並びにｉｃチップパッケージ
US20080178023A1 (en) * 2007-01-18 2008-07-24 International Business Machines Corporation Method and system for independent processor voltage supply
TW201037834A (en) * 2008-09-23 2010-10-16 Globalfoundries Us Inc Interposer including voltage regulator and method therefor
US20120147567A1 (en) * 2010-12-09 2012-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Networking Packages Based on Interposers

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