CN105140189A - Board-level fan-out chip packaging device and preparation method thereof - Google Patents

Board-level fan-out chip packaging device and preparation method thereof Download PDF

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Publication number
CN105140189A
CN105140189A CN201510398269.4A CN201510398269A CN105140189A CN 105140189 A CN105140189 A CN 105140189A CN 201510398269 A CN201510398269 A CN 201510398269A CN 105140189 A CN105140189 A CN 105140189A
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chip
loading plate
recessed
fan
dielectric layer
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CN105140189B (en
Inventor
郭学平
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Guangdong Fozhixin Microelectronics Technology Research Co ltd
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National Center for Advanced Packaging Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • H01L2924/15156—Side view

Abstract

The embodiment of the invention relates to a board-level fan-out chip packaging device and a preparation method thereof. A recess is formed in one side of a bearing board used for bearing a chip, the size of the recess is matched with the size of the back side of the chip, and the chip is mounted in the recess. When the chip is mounted to the bearing board, the recess in the bearing board exactly accommodates the back side of the chip, so that the chip to be packaged is easy and convenient to put in place. According to the invention, the dependence of fan-out packaging on the format of a chip mounter and chip mounting precision is eliminated, so that the development of the large-format fan-out chip packaging technology is facilitated.

Description

Plate level fan-out-type chip package device and preparation method thereof
Technical field
The present invention relates to the technical field of chip package, more specifically, relate to fan-out-type chip package device and preparation method thereof.
Background technology
Along with the development of information technology and semiconductor technology, the electronic equipments such as mobile phone, PAD, intelligent watch present lightness and the trend that mutually merges of function gradually.This is more and more higher to the integration level necessitates of chip, and then brings unprecedented challenge to the encapsulation of chip.The mismatch of ever-increasing interconnect pitch, add the various chip with difference in functionality and reduce package dimension under same area occupied to increase battery sizes and to extend working time etc. and all open window for innovation embeds encapsulation technology.
Benefit from the exploitation of 3D silicon through hole (TSV) technology, fan-out-type wafer-level packaging (FOWLP) is considered to the movement/wireless market of the most applicable high request at present, and high-performance and undersized market are paid close attention to other, also there is very strong attraction.Fan-out-type wafer-level packaging is the embedded encapsulation of wafer level processing, and it realizes multi-chip that is vertical and horizontal direction in a package without substrate integrated.
In the fan-out-type wafer-level packaging of current main flow, chip by suitable material around, encapsulation area occupied expands to beyond chip by these materials.Chip wafer scale flip-clip embeds in synthetic plastic wafer (restructuring wafer).Then with the insulation of front road and metallization process, with wafer scale photoetching and drafting method, interconnection is fanned out to peripheral region.Again on wafer, apply soldered ball and carry out concurrent testing.Then restructuring wafer is cut into separate unit, carries out packing and shipping.But, the heat management performance of the chip package device made by this fan-out package based on plastic packaging mode on wafer process basis is utilized to have very large restriction, process aspect is also have the deficiencies such as cost is high, complex process in addition, so result in cost height and the not high defect of performance.
The application of the publication CN104241153A of inventor discloses a kind of chip packaging method of plate level fan-out-type structure, the problems such as the warpage that the fan-out-type wafer-level packaging to some extent solving chip easily occurs in the fabrication process, and manufacture efficiency is improved.Chip packaging method disclosed in this patent application, plate level fan-out-type structure needs chip attachment on loading plate (such as Copper Foil).And in actual production, on one in length and breadth direction equal wide cut panel on encapsulate multiple chip simultaneously, form the cutter unit of multiple chip package.But at present a lot of chip mounter (DB equipment) can not meet the continuous increase of present plate level size and the more and more higher demand of required precision, which has limited the reduction with cost that further develops of this technology.
Summary of the invention
In view of this, an object of the present invention is intended to solve the paster problem in the plate level fan-out-type chip package process process of large format.
According to one embodiment of the present invention, provide a kind of plate level fan-out-type chip package device.This plate level fan-out-type chip package device comprises: loading plate, is provided with recessed, and described recessed size is suitable for holding chip; Chip, its back side by adhesive be mounted on described loading plate described recessed in; And the described recessed side of described loading plate, be arranged in dielectric layer on described loading plate and described chip.By loading plate described in pressing and described dielectric layer, in the gap that the material of described dielectric layer can be filled between the described recessed of described loading plate and described chip.
According to another execution mode of the present invention, provide a kind of preparation method of plate level fan-out-type chip package device, this comprises: provide loading plate, described loading plate is provided with recessed, and described recessed size is suitable for holding chip; Utilize adhesive by the back side of described chip attachment with described loading plate described recessed in; In the described recessed side of described loading plate, on described loading plate and described chip, arrange dielectric layer; And by loading plate and described dielectric layer described in pressing, in the gap that the material of described dielectric layer can be filled between the described recessed of described loading plate and described chip.
According to the embodiment of the present invention, provide a kind of method of paster artoregistration, obviate the dependence for patch device such as paster precision, thus obviate the dependence of breadth for chip mounter of plate level, be applicable to the fan-out package technique of large format.In addition, heat management performance for the fan-out package of traditional technique is poor, so the back side of chip to mount on the metal backing of high heat conduction thus can greatly enhance the heat dispersion of chip by embodiments of the present invention, improve the performance of the entirety of chip.In addition, the technique of embodiment of the present invention, mainly based on the process route of encapsulating carrier plate, can be adapted to the technique of substrate, the basis that reduce further technique cost of manufacture also improves the performance of device.
According to the following detailed description of this specification by reference to the accompanying drawings, these and other advantages of the various execution mode of the present invention and feature all will become more obvious.
Accompanying drawing explanation
Fig. 1-Fig. 9 illustrates the step cross-sectional view formed according to the plate level chip packaging device of one embodiment of the present invention.
Embodiment
More completely describe present disclosure hereinafter with reference to accompanying drawing, wherein show the execution mode of present disclosure in the accompanying drawings.But these execution modes multi-formly can realize and should not be construed as limited to execution mode as herein described with many.On the contrary, provide these examples will to be thorough and complete to make present disclosure, and the scope of present disclosure will be expressed all sidedly to those skilled in the art.Although it should be noted that hereafter by the manufacture craft of chip package device relatively complete for description one, the processing step wherein had is optional, and there is the execution mode replaced.
Run through present disclosure, similar Reference numeral represents similar element.Such as, Reference numeral 10 also may represent the Reference numeral 1003,1004,1008,1009 etc. with different suffix.
The core idea of embodiment of the present invention comprises: the one side being used for the loading plate of carries chips when packaged chip arranges recessed, the matching size of this recessed size and chip back; Then by chip attachment in this recessed position.Like this, by chip attachment to loading plate time, the back side of the recessed proper accommodation chip on loading plate, thus make to keep chip in place to be packaged to be more prone to and convenient.Thus, achieve the chip artoregistration when pasting chip, obviate the dependence for patch device such as paster precision, thus obviate the dependence of breadth for chip mounter of plate level, the fan-out package technique of likely carrying out large format is carried out.In addition, according to the embodiment of the present invention, arranging recessed loading plate can be made up of the material of high-termal conductivity, makes the heat dissipation problem of chip be improved to a certain extent.
Below with reference to Fig. 1-Fig. 9, the technological process for the manufacture of plate level fan-out-type chip package device 10 is described.Fig. 1-Fig. 9 illustrates the step cross-sectional view formed according to the chip packaging device of embodiment of the present invention.
In fig. 1 and 2, perform the first step of this technological process, prepare the loading plate 51 and the chip 71 that are used for pasting chip.Loading plate 50 is provided with recessed 52, and recessed 52 have the size matched with the back side of chip 71.
In the example shown in Fig. 1 and Fig. 2, it is trapezoidal recessed 52 that the loading plate 51 of chip attachment has a cross section.Can be identical with the angle on the inclined-plane 78 that the back side of chip 71 makes in the angle of the trapezoidal hypotenuse of recessed 52, and the size of its bottommost can be little with the size of chip 71, thus can carry out in chip attachment process, make chip can contraposition automatically to its accurate position.
In the example shown in Fig. 1 and Fig. 2, the cross section of recessed 52 is trapezoidal, and the cross section of chip 71 is rectangle and chamfering 78 is treated in side, but is to be understood that, according to the embodiment of the present invention, the cross section of recessed 72 also can be rectangle or other are polygonal.Thus, those skilled in the art will understand, the shape of recessed 73 can be such as round platform, cuboid etc., and the present invention does not limit recessed shape.Those skilled in the art also will understand, the cross section of chip 71 also can be rectangle not with chamfering, the suitable shape such as trapezoidal, as long as its back side and recessed 52 matching size.
According to the embodiment of the present invention, loading plate 51 can be made up of the material having high-termal conductivity and be easy to the features such as processing, resin (such as, the BT resin) material etc. of such as metal or high-termal conductivity.According to the embodiment of the present invention, recessed in loading plate 51 can be formed by techniques such as machining, laser processing, chemical etchings.
Although Fig. 1 illustrate only loading plate 51 a part and on recessed 52, should be appreciated that loading plate 51 can be the loading plate of large format on direction in length and breadth, and it can have multiple recessed 52, for once mounting multiple chip 71.
In figs. 3 and 4, perform the second step of this technological process, utilize adhesive 81 to be mounted in recessed 52 of loading plate 51 by chip 71, and utilize the dielectric layer 82 being arranged in the front of chip 71 to carry out dielectric layer pressing.
In the example depicted in fig. 3, carry out the attachment of chip 71, the TIM material 81 of application high-termal conductivity carries out the attachment of chip, in the process of carrying out paster, first sufficient on point in recessed 52 of loading plate adhesive, then applies the chip mounter that can support large plate and carries out paster.
According to an embodiment of the invention, adhesive 81 can be liquid, because mobility is relatively good, makes it possible to meet more smoothly position adjustment time its chip carries out artoregistration.
In the example depicted in fig. 4, carry out the pressing of dielectric layer 81, application high temperature press or vacuum press carry out the pressing of the dielectric layer above chip 71, thus are embedded in loading plate 51 and dielectric layer 81 by chip 71.
In the example depicted in fig. 4, dielectric layer 81 can adopt layer of prepreg (PP sheet).Prepreg adopts glass fabric to do reinforcing material mostly, the upper resin adhesive liquid of treated glass fabric dipping, then is called prepreg through the sheeting that heat treatment preliminary drying is made, and it adds pressure in heating and can soften, and can react solidification after cooling.Dielectric layer also can use the ABF resin bed, FR resin etc. of such as pure colloid.The dielectric layer of concrete use can need according to application and select.
In the example shown in Fig. 3 and Fig. 4, application high temperature press or vacuum film pressing machine carry out the lamination of dielectric layer, the dielectric layers such as the prepreg using it to mount and ABF, FR carry out filling the peripheral clearance 58 of chip, and then it can stabilization package chip 71 betwixt after cooling curing.
In the example shown in Fig. 3 and Fig. 4, chip 71 partly embeds in recessed 52 of loading plate 51, but should be appreciated that chip 71 also can be fully inserted into this in recessed 52 when mounting.When chip 71 is fully inserted in recessed 52, as previously mentioned, by the pressing of dielectric layer, the chip 71 be embedded in loading plate 51 and dielectric layer 81 also can be made to keep stable.
In Figure 5, perform the third step of this technological process, relate to the operation in the front at the chip-packaging structure 1004 formed at present, the boring carrying out blind hole 74 in the front of chip 71 makes, made blind hole 74 aims at the metal salient point 72 of chip 71, and reaches metal salient point 72 through dielectric layer 81.The mode of machine drilling or laser drill can be used to make blind hole in the front of chip 71.
According to an embodiment of the invention, on the metal salient point that blind hole 74 can end in chip or be embedded into 1-5 μm in metal salient point, under this situation, the metal salient point required thickness on chip is at least at 10 μm.
In figure 6 and figure 7, perform the 4th step of this technological process, relate to the operation in the front at the chip-packaging structure 1005 formed at present, metalized blind vias 74, surface lines metal level 54 is formed in the front of the chip-packaging structure formed at present, and carry out fan-out circuit making in the front of the chip-packaging structure formed at present, form metallic circuit pattern 55.
As shown in Figure 6, in the front of encapsulating structure 1005, carrying out plating one deck Seed Layer in blind hole 74, such as electroless copper, and the electroplating technology carrying out blind hole carries out filling out copper in blind hole, formed through copper-plated blind hole 75, then form surface lines layers of copper 55, thus the I/O of chip is drawn out on outer field circuit.
As shown in Figure 7, the making of fan-out circuit 55 is carried out in the front of chip-packaging structure 1006.The making of fan-out circuit can adopt the techniques such as exposure, development, etching to carry out, thus defines the fan-out sandwich circuit 55 that chip draws outward.
In fig. 8, perform the 5th step of this technological process, relate to the operation in the front at the chip-packaging structure 1007 formed at present, make solder mask 56.
In the example depicted in fig. 8, on the fan-out circuit formed, make one deck solder mask 56, such as welding resistance green oil, prevents the oxidation of circuit.Then, solder mask 56 carries out multiple windowing, on the plurality of windowing, make UBM (metallizing under salient point) layer, formed and may be used for the pad 57 of planting ball grid array (BGA) soldered ball at subsequent step.
In fig .9, perform the 6th step of this technological process, relate to the operation in the front at the chip-packaging structure 1008 formed at present, the pad 57 that the 5th step is formed plants BGA ball 59.
By above-mentioned steps, form the preferred plate level fan-out-type chip-packaging structure according to embodiment of the present invention.Be to be understood that, although the foregoing describe the process mounted by a chip 71 with on loading plate 51 recessed 52, but loading plate 51 can have multiple recessed, embodiments of the present invention are applicable to once by multiple recessed on this loading plate of multiple chip attachment.
It should be noted that, embodiments of the present invention mainly relate to the operation of chip back, and the sequence of maneuvers for finally planting BGA ball of the chip front side related in describing above, that the equivalent implementations that those skilled in the art can understand other is also possible for follow-up operation plate level fan-out package structure installment being carried out the electrical connection of fan-out package structure and pcb board to pcb board.
Thus the preparation method of plate level fan-out-type chip package device provided according to the embodiment of the present invention comprises: provide loading plate, be provided with recessed, recessed size is suitable for holding chip; Utilize adhesive by the back side of chip attachment with loading plate recessed in; In the recessed side of loading plate, on loading plate and chip, arrange dielectric layer; And by pressing loading plate and dielectric layer, in the gap that the material of dielectric layer can be filled between the recessed of loading plate and chip.
Structure according to the chip packaging device 10 of embodiment of the present invention is embodied in the introduction of above technological process, its cross section such as shown in Fig. 3-Fig. 9.As shown in Figure 4, plate level fan-out-type chip package device 1004 comprises: loading plate, is provided with recessed, and recessed size is suitable for holding chip; Chip, its back side by adhesive be mounted on loading plate recessed in; And the recessed side of loading plate, be arranged in dielectric layer on loading plate and chip.By pressing loading plate and dielectric layer, in the gap that the material of dielectric layer can be filled between the recessed of loading plate and chip.
The Heterosis of embodiment of the present invention exists:
(1) owing to obviating the dependence of paster precision for patch device of pasting chip on panel, thus go for the application of arbitrary large small panel, the technology acuracy of sealed in unit can not be limited by, and its process costs is lower.The increase of panel can reduce the cost encapsulated chip to a great extent.
(2) loading plate mounted due to chip back can select the material of high-termal conductivity, thus solves the problem of the heat radiation of high-power component to a certain extent, improves the heat management performance of chip-packaging structure.
(3) owing to adopting the mode of metal salient point to be embedded in encapsulation for packaged chip, the mode then by changing copper plating blind hole carries out fan-out, can be good at yield and the reliability of the chip-packaging structure controlling gained in this way.
(4) employing is carried out based on the technique of encapsulating carrier plate, makes it possible to the technique being adapted to substrate, reduce further technique cost of manufacture, also improve the performance of device.
The those skilled in the art benefiting from the instruction provided in aforementioned specification and associated drawings will easily expect many improvement and other execution modes of present disclosure.Therefore, be appreciated that and these are only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement etc., all should be included within protection scope of the present invention.

Claims (10)

1. plate level fan-out-type chip package device (1004), comprising:
Loading plate (51), is provided with recessed (52), and the size of described recessed (52) is suitable for holding chip;
Chip (71), its back side is mounted in described recessed (52) of described loading plate (51) by adhesive (81); And
Described recessed (52) side of described loading plate (51), be arranged in dielectric layer (82) on described loading plate (51) and described chip (71),
Wherein, by loading plate described in pressing (51) and described dielectric layer (82), in the gap that the material of described dielectric layer can be filled between described recessed (52) of described loading plate (51) and described chip (71).
2. plate level fan-out-type chip package device according to claim 1, the cross section of described recessed (52) of wherein said loading plate (51) is trapezoidal, and the back side of described chip (71) is provided with chamfering (78), the gradient of described chamfering is identical with described trapezoidal gradient.
3. plate level fan-out-type chip package device according to claim 1, the size of the bottom of described recessed (52) of wherein said loading plate (51) is slightly less than the size at the back side of described chip (71).
4. the plate level fan-out-type chip package device according to any one of claim 1-3, also comprises:
Be formed in described chip (71) and described loading plate (53) set the front of structure, fan-out circuit layer (55) on described dielectric layer (82).
5. plate level fan-out-type chip package device according to claim 4, wherein forms described fan-out circuit layer (55) and comprising:
In described dielectric layer (82), prepare the blind hole (74) corresponding with the metal salient point (72) of described chip, electroless copper and electroplating processes are carried out to described blind hole and on described dielectric layer (82), forms described fan-out circuit layer (80).
6. a preparation method for plate level fan-out-type chip package device, comprising:
There is provided loading plate (51), described loading plate (51) is provided with recessed (52), the size of described recessed (52) is suitable for holding chip (71);
Adhesive (81) is utilized to be mounted in described recessed (52) of described loading plate (51) by the back side of described chip (71);
In described recessed (52) side of described loading plate (51), on described loading plate (51) and described chip (71), arrange dielectric layer (82); And
By loading plate described in pressing (51) and described dielectric layer (82), in the gap that the material of described dielectric layer can be filled between described recessed (52) of described loading plate (51) and described chip (71).
7. method according to claim 6, the cross section of described recessed (52) of wherein said loading plate (51) is trapezoidal, and the back side of described chip (71) is provided with chamfering (78), the gradient of described chamfering is identical with described trapezoidal gradient.
8. method according to claim 6, the size of the bottom of described recessed (52) of wherein said loading plate (51) is slightly less than the size at the back side of described chip (71).
9. the method according to any one of claim 6-8, also comprises:
In the front of setting structure of described chip (71) and described loading plate (53), on described dielectric layer (82), form fan-out circuit layer (55).
10. method according to claim 9, wherein forms described fan-out circuit layer (55) and comprising:
In described dielectric layer (82), prepare the blind hole (74) corresponding with the metal salient point (72) of described chip, electroless copper and electroplating processes are carried out to described blind hole and on described dielectric layer (82), forms described fan-out circuit layer (80).
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