CN105047553A - Surface treatment method for depositing high-dielectric value gate medium layer - Google Patents
Surface treatment method for depositing high-dielectric value gate medium layer Download PDFInfo
- Publication number
- CN105047553A CN105047553A CN201510532420.9A CN201510532420A CN105047553A CN 105047553 A CN105047553 A CN 105047553A CN 201510532420 A CN201510532420 A CN 201510532420A CN 105047553 A CN105047553 A CN 105047553A
- Authority
- CN
- China
- Prior art keywords
- semiconductor substrate
- layer
- gate dielectric
- depositing
- high dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 53
- 238000000151 deposition Methods 0.000 title claims abstract description 24
- 238000004381 surface treatment Methods 0.000 title claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 62
- 239000000758 substrate Substances 0.000 claims abstract description 61
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 44
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 37
- 239000007789 gas Substances 0.000 claims abstract description 33
- 239000001301 oxygen Substances 0.000 claims abstract description 31
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 31
- 239000001257 hydrogen Substances 0.000 claims abstract description 29
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 29
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 28
- 239000010703 silicon Substances 0.000 claims abstract description 28
- 239000012535 impurity Substances 0.000 claims abstract description 23
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 22
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 22
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 17
- WSLDOOZREJYCGB-UHFFFAOYSA-N 1,2-Dichloroethane Chemical group ClCCCl WSLDOOZREJYCGB-UHFFFAOYSA-N 0.000 claims abstract description 15
- 238000004140 cleaning Methods 0.000 claims abstract description 15
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 claims abstract description 11
- 229910052708 sodium Inorganic materials 0.000 claims abstract description 11
- 239000011734 sodium Substances 0.000 claims abstract description 11
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 8
- 239000000203 mixture Substances 0.000 claims abstract description 4
- 239000003595 mist Substances 0.000 claims description 33
- 239000000463 material Substances 0.000 claims description 15
- 150000002431 hydrogen Chemical class 0.000 claims description 12
- 239000002253 acid Substances 0.000 claims description 11
- 238000004821 distillation Methods 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- NPYPAHLBTDXSSS-UHFFFAOYSA-N Potassium ion Chemical compound [K+] NPYPAHLBTDXSSS-UHFFFAOYSA-N 0.000 claims description 2
- 238000006213 oxygenation reaction Methods 0.000 claims description 2
- 229910001414 potassium ion Inorganic materials 0.000 claims description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 abstract description 13
- 229910021645 metal ion Inorganic materials 0.000 abstract description 10
- ZLMJMSJWJFRBEC-UHFFFAOYSA-N Potassium Chemical compound [K] ZLMJMSJWJFRBEC-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052700 potassium Inorganic materials 0.000 abstract description 9
- 239000011591 potassium Substances 0.000 abstract description 9
- 238000005516 engineering process Methods 0.000 abstract description 8
- 230000003647 oxidation Effects 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 4
- 230000001590 oxidative effect Effects 0.000 abstract description 2
- 239000005416 organic matter Substances 0.000 abstract 1
- 238000006243 chemical reaction Methods 0.000 description 8
- 239000003570 air Substances 0.000 description 5
- 230000008021 deposition Effects 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000035484 reaction time Effects 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- AIOWANYIHSOXQY-UHFFFAOYSA-N cobalt silicon Chemical compound [Si].[Co] AIOWANYIHSOXQY-UHFFFAOYSA-N 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000009833 condensation Methods 0.000 description 1
- 230000005494 condensation Effects 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 229910000041 hydrogen chloride Inorganic materials 0.000 description 1
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000011177 media preparation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 150000003254 radicals Chemical class 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 150000004760 silicates Chemical class 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000005092 sublimation method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02065—Cleaning during device manufacture during, before or after processing of insulating layers the processing being a planarization of insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
The invention provides a surface treatment method for depositing a high-dielectric value gate medium layer. The surface treatment method comprises the following steps: on a cleaned semiconductor substrate, oxidizing the semiconductor substrate with a first mixed gas, wherein the first mixed gas is a mixture of a hydrochloric acid gas, hydrogen and oxygen or a mixture of a dichloroethylene gas, hydrogen and oxygen; and cleaning the obtained semiconductor substrate through an SiCoNi precleaning technology, and sequentially growing a silicon dioxide layer and depositing a high-dielectric value gate medium layer, or sequentially growing a silicon oxynitride layer and depositing the high-dielectric value gate medium layer. According to method, the semiconductor substrate is firstly oxidized, and metal ions of sodium, potassium and the like and organic matter impurities on the surface of a silicon substrate are removed in the oxidation process, so that the effect of reducing the impurity content on the surface of the silicon substrate is reached; an oxidation film is removed after being cleaned by the SiCoNi precleaning technology; the impurity content on the surface of the silicon substrate is reduced previously and thus the purity of the grown silicon dioxide layer or silicon oxynitride layer is improved, so that the reliability of a semiconductor device is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of surface treatment method for depositing high dielectric radio gate dielectric layer.
Background technology
Along with the develop rapidly of very lagre scale integrated circuit (VLSIC) (VLSI, VeryLargeScaleIntegration) and ultra large scale integrated circuit (ULSI, ultralargescaleintegration), the size of MOS device is constantly reducing.In MOS device, grow gate insulation layer on a semiconductor substrate and be used for cover gate, general gate insulator layer material is the oxide of insulation, and common is silicon dioxide, is also gate oxide.For increasing the reaction speed of MOS device, improving the capacity of drive current and storage capacitance, in MOS device, the thickness of gate oxide constantly reduces.But thing followed two problems becomes the key factor hindering integrated circuit to further develop: leak electricity and puncture.When gate oxide thickness lower than
due to quantum tunneling effect, charge carrier can flow through this ultra-thin gate dielectric, and charge carrier tunnelling probability exponentially rises along with the minimizing of the thickness of oxide layer.In MOS device, be positioned at below grid, being used for one deck thin layer of isolated grid and raceway groove is called gate dielectric layer, gate dielectric layer adopts insulating material to make, when metal-oxide half field effect transistor (MOSFET, Metal-Oxide-SemiconductorField-EffectTransistor) works in integrated circuit, electric charge flows through device to be caused producing defect at gate dielectric layer and SiO2/Si interface, when reaching critical defective density, gate dielectric layer punctures, and causes component failure.Under high dielectric radio metal gate silicon process technique below 45 nm technology node, traditional SiON gate medium can not meet the electric leakage of device and puncture requirement, not only because the excessive device that causes that leaks electricity cannot normally work, and time breakdown (TDDB, timedependentdielectricbreakdown) can not meet device reliability requirements.
From the formula of drive current and gate capacitance, gate capacitance is larger, and drive current is larger; And gate dielectric layer dielectric constant is larger, gate capacitance is larger, specific as follows:
I
D～μ/L
g*C
ox(V
DD-V
TH)
2
C
ox＝kA/d
Wherein I
dfor drive current, μ is carrier mobility, L
gfor grid length, C
oxfor gate capacitance, V
dDfor operating voltage, V
tHfor threshold voltage, k is gate dielectric layer dielectric constant, and A is device area, and d is gate dielectric layer thickness.
Therefore, need a kind of alternative gate dielectric layer material, not only will have enough actual (real) thickness to reduce leakage current density and to strengthen time breakdown TDDB reliability requirement, and high grid capacitance can be provided to increase drive current.In order to achieve the above object, the dielectric constant that the gate dielectric layer material substituted has needs the dielectric constant higher than traditional silicon oxynitride (SiON).Therefore below 45 nm technology node, in the urgent need to adopting novel high-dielectric-coefficient grid medium if the oxide of Hf base, Zr or Al is to replace SiON.
Height-k (high dielectric radio) material a kind ofly replaces the material of silicon dioxide as gate medium.It possesses good insulation attribute, can produce higher field effect (i.e. height-k), both desirable attributes of high-performance transistor between grid and silicon bottom passage simultaneously.K (being actually Greek Kappa) is an engineering term, the ability that electric charge possessed by a kind of material is described, in the material, some material can stored charge better than other materials, therefore, have higher " k " value, in addition, because high-g value is thicker than silicon dioxide, remain attribute desirable equally simultaneously, therefore, they significantly can reduce electrical leakage quantity.
The preparation flow that high dielectric radio (i.e. high-k) gate medium is conventional is followed successively by cleaning, ultra-thin Si O
2or the growth of SiON layer, high dielectric radio gate medium deposition.
Because high dielectric radio gate dielectric material is mainly based on metal oxide, must the existence of aerobic in preparation process, and the reaction of oxygen and silicon can form the interface oxide layer of silicon dioxide or silicide between high dielectric radio gate dielectric layer and silicon substrate, the existence due to this interface oxide layer makes reducing of equivalent oxide thickness become difficulty.In order to suppress the generation of interface oxide layer, need the ultra-thin Si O growing one deck high-quality before high dielectric radio gate dielectric layer deposition
2or SiON layer.But because the concentration of metal ions such as the sodium in Semiconductor substrate, potassium and organic impurities content can not reduce, therefore at grow ultra-thin SiO by cleaning process of the prior art
2or during SiON layer, the metal ion in Semiconductor substrate and organic impurities often remain in ultra-thin Si O
2or in SiON layer, Semiconductor substrate is when being exposed in air in addition, can be generated native oxide by the dioxygen oxidation in air, because impurity in air is also more, the impurity in native oxide is also more, causes the ultra-thin Si O of growth for these reasons
2or the purity of SiON layer declines, after follow-up semiconductor technology processing procedure, the ultra-thin Si O that this layer of purity is lower
2or SiON layer can affect the reliability of product, be therefore necessary to improve conventional high dielectric radio gate medium preparation flow, the metal ions such as the sodium in native oxide and Semiconductor substrate, potassium and organic impurities reduced, makes the ultra-thin Si O of growth
2or SiON layer purity improves, thus improve the reliability of semiconductor device.
Summary of the invention
The invention provides a kind of surface treatment method for depositing high dielectric radio gate dielectric layer, namely before the high dielectric radio gate dielectric layer of deposition, mist oxide-semiconductor substrate is used, and use the pre-clear technique of SiCoNi to wash material and the part native oxide of the formation of above-mentioned mist oxide-semiconductor substrate, make the metal ions such as the sodium in native oxide and Semiconductor substrate, potassium and organic impurities reduce like this, make the ultra-thin Si O of growth
2or SiON layer purity improves, thus improve the reliability of semiconductor device.
For achieving the above object, the invention provides a kind of surface treatment method for depositing high dielectric radio gate dielectric layer, in Semiconductor substrate after cleaning, the first mist is used to be oxidized described Semiconductor substrate, described first mist is HCl gas, hydrogen, the mist that oxygen forms or for dichloroethylene gas, hydrogen, the mist that oxygen forms, the described Semiconductor substrate obtained is grown silicon dioxide layer successively after the pre-clear technique cleaning of SiCoNi, deposit high dielectric radio gate dielectric layer or grow silicon oxynitride layer successively, deposit high dielectric radio gate dielectric layer.
As preferably, comprise the following steps:
Step one: described Semiconductor substrate is provided;
Step 2: use acid tank liquor to clean described Semiconductor substrate and impurity is removed;
Step 3: use described first mist to be oxidized described Semiconductor substrate at 650 ~ 900 DEG C, described first mixed gas composition is HCl gas or dichloroethylene gas, hydrogen and oxygen, and oxidization time is 5min ~ 10min;
Step 4: use the Semiconductor substrate that the pre-clear technique cleaning step three of described SiCoNi obtains;
Step 5: grow described silicon dioxide layer or described silicon oxynitride layer successively in the Semiconductor substrate that step 4 is formed, deposit described high dielectric radio gate dielectric layer.
As preferably, the structure of Semiconductor substrate described in step one at least comprises fleet plough groove isolation structure, N well structure and P well structure.
As preferably, the described impurity in step 2 comprises sodium, potassium ion and organic impurities.
As preferably, use rapid thermal process apparatus when being oxidized described Semiconductor substrate in step 3 or described Semiconductor substrate is placed on boiler tube and be oxidized, when described first mist is HCl gas, hydrogen, oxygen, the total flow of described first mist is 0.5 ~ 15slm, wherein the ratio of hydrogen and oxygen is less than 1:1, and the ratio of HCl gas and oxygen is less than 1:5; When described first mist is dichloroethylene gas, hydrogen, oxygen, the total flow of described first mist is 0.5 ~ 15slm, and wherein the ratio of hydrogen and oxygen is less than 1:1, and the ratio of dichloroethylene gas and oxygen is less than 1:10.
As preferably, use original position moisture-generation process in step 5 or use furnace process growth silicon dioxide layer or silicon oxynitride layer.
As preferably, the thickness of described silicon dioxide layer or described silicon oxynitride layer is
As preferably, the pre-clear technique of described SiCoNi is divided into remote plasma to etch and distillation two steps, and the gas of described remote plasma etching is NF
3and NH
3mist.
As preferably, described high dielectric radio gate dielectric layer material is HfO
2or ZrO
2or Al
2o
3.
As preferably, described high dielectric radio gate dielectric layer material thickness is
Compared with prior art, the invention has the beneficial effects as follows: the invention provides a kind of surface treatment method for depositing high dielectric radio gate dielectric layer, in Semiconductor substrate after cleaning, the first mist is used to be oxidized described Semiconductor substrate, described first mist is HCl gas, hydrogen, the mist that oxygen forms or for dichloroethylene gas, hydrogen, the mist that oxygen forms, the described Semiconductor substrate obtained is grown silicon dioxide layer successively after the pre-clear technique cleaning of SiCoNi, deposit high dielectric radio gate dielectric layer or grow silicon oxynitride layer successively, deposit high dielectric radio gate dielectric layer.This surface treatment method, the first mist is first used to be oxidized described Semiconductor substrate, the metal ions such as the sodium in original Semiconductor substrate, potassium are volatilized away with muriatic gaseous form, and organic impurities is also oxidized to volatilize away in the form of a vapor, then this layer of oxide layer is removed after the pre-clear technique cleaning of integrated SiCoNi, in the Semiconductor substrate obtained, then grow silicon dioxide layer or silicon oxynitride layer successively, deposit high dielectric radio gate dielectric layer.Because the metal ion such as sodium, potassium on silicon substrate before and organic impurities content have been lowered, the pre-clear technique of integrated SiCoNi also significantly reduces the thickness of the more native oxide of impurity, therefore grow the silicon dioxide layer that obtains or silicon oxynitride layer purity very high, thus improve the reliability of semiconductor device.
Accompanying drawing explanation
Fig. 1 is surface treatment method flow chart provided by the invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Please refer to Fig. 1, the invention provides a kind of surface treatment method for depositing high dielectric radio gate dielectric layer, comprising the following steps:
Step one: Semiconductor substrate is provided, here Semiconductor substrate can be the pure silicon sheet without circuit, also can be the wafer having circuit, moreover, here semiconductor substrate structure at least comprises fleet plough groove isolation structure, N well structure and P well structure, can certainly be other semiconductor substrate structure common at present.
Use acid tank cleaning Semiconductor substrate that impurity is removed, described acid tank is the first acid tank, the second acid tank and the 3rd acid tank, containing NH in described first acid tank
4oH, H
2o
2and H
2o, containing HCl, H in the second acid tank
2o
2and H
2o, containing HF in the 3rd acid tank.Here impurity is the organic impurities in the metal ion such as sodium, potassium and air;
Step 2: only can not remove metal ion and the organic impurities such as sodium, potassium in Semiconductor substrate by the cleaning of above-mentioned acid tank liquor completely, now need to adopt other method this part residual metal ion such as sodium, potassium and organic impurities to be removed: in Semiconductor substrate after cleaning, the first mist using HCl gas or dichloroethylene gas and vapor permeation hydrogen and oxygen to be formed is oxidized described Semiconductor substrate.
When the first mist is HCl gas, hydrogen and oxygen, in first mist, the total flow of hydrogen, oxygen and HCl gas is 0.5 ~ 15slm, wherein the ratio of hydrogen and oxygen is less than 1:1, the ratio of HCl gas and oxygen is less than 1:5, reaction time is 5min ~ 10min, and technological temperature is 650 ~ 900 DEG C; When the first mist is dichloroethylene gas, hydrogen and oxygen, in first mist, the total flow of hydrogen, oxygen and dichloroethylene gas is 0.5 ~ 15slm, wherein the ratio of hydrogen and oxygen is less than 1:1, the ratio of dichloroethylene gas and oxygen is less than 1:10, reaction time is 5min ~ 10min,, technological temperature is 650 ~ 900 DEG C, and dichloroethylene can generate hydrochloric acid with oxygen or water (being generated by hydrogen and oxygen reaction) in course of reaction.
Oxidizing process can adopt rapid thermal processing system (RTP, rapidthermalprocess), also Semiconductor substrate can be placed in boiler tube and be oxidized.
Step 3: after Semiconductor substrate is oxidized by above-mentioned first mist, generate layer oxide film, cleans the described Semiconductor substrate obtained through the pre-clear technique of SiCoNi, reaches with this effect reducing native oxide.
The pre-clear technique of SiCoNi is the pre-clear technique of a new generation, and belonging to prior art, is a kind of low intensive chemical etching method, for from cobalt silicon and nisiloy surface removal oxide-film, is divided into remote plasma to etch and distillation two steps.
In remote plasma etching, Semiconductor substrate is placed on the base of 35 DEG C, and lower powered plasma is by NF
3and NH
3be transformed into NH
4f and (NH
4) HF
2, fluoride in crystal column surface condensation, and preferential to react with oxide, formation (NH
4)
2siF
6, this silicate can distil in the environment more than 70 DEG C.
In position in annealing process, Semiconductor substrate is moved to the position near heater block, and heat takes on wafer by the hydrogen of flowing, and wafer is heated to more than 100 DEG C in a short period of time, makes (NH
4)
2siF
6be decomposed into the SiF of gaseous state
4, NH
3and HF, and pumped.
Above-mentioned course of reaction chemical formula is as follows:
Etching agent generates: NF
3+ NH
3→ NH
4f+ (NH
4) HF
2
Etching process: NH
4f+SiO
2→ (NH
4)
2siF
6+ H
2o
Sublimation process: (NH
4)
2siF
6→ SiF
4+ NH
3+ HF
After above-mentioned reaction, oxide-film is removed, and being also removed by the native oxide that outside air oxidation is formed on the original top layer of Semiconductor substrate, which enhance purity and the cleanliness factor of Semiconductor substrate upper surface silicon.
Step 4: deposited silicon dioxide layer or silicon oxynitride layer in the Semiconductor substrate that step 3 is formed, original position moisture-generation process (ISSG, in-situstreamgeneration) can be used or in boiler tube, grow silicon dioxide layer or silicon oxynitride layer.
Original position moisture-generation process is a kind of New Low Voltage Quick Oxidation thermal annealing technology, belong to prior art, be mainly used in ultra-thin oxide film growth etc., it adopts the oxygen mixing trace hydrogen as reaction atmosphere, at high temperature hydrogen can produce with oxygen the chemical reaction being similar to burning, generate a large amount of gas-phase activity free radical that main component is elemental oxygen, thus oxidation creates ultra-thin oxide film, usual reaction pressure is between 667Pa ~ 2000Pa.
Preferably, the silicon dioxide layer of generation or the thickness of silicon oxynitride layer are
Step 5: deposit high dielectric radio gate dielectric layer on the silicon dioxide layer or silicon oxynitride layer of step 4 generation, material is HfO
2or ZrO
2or Al
2o
3, preferably, the thickness of deposition is
Obviously, those skilled in the art can carry out various change and modification to invention and not depart from the spirit and scope of the present invention.If these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. one kind for depositing the surface treatment method of high dielectric radio gate dielectric layer, it is characterized in that, in Semiconductor substrate after cleaning, the first mist is used to be oxidized described Semiconductor substrate, described first mist is HCl gas, hydrogen, the mist that oxygen forms or for dichloroethylene gas, hydrogen, the mist that oxygen forms, the described Semiconductor substrate obtained is grown silicon dioxide layer successively after the pre-clear technique cleaning of SiCoNi, deposit high dielectric radio gate dielectric layer or grow silicon oxynitride layer successively, deposit high dielectric radio gate dielectric layer.
2. as claimed in claim 1 for depositing the surface treatment method of high dielectric radio gate dielectric layer, it is characterized in that, comprise the following steps:
Step one: described Semiconductor substrate is provided;
Step 2: use acid tank liquor to clean described Semiconductor substrate and impurity is removed;
Step 3: use described first mist to be oxidized described Semiconductor substrate at 650 ~ 900 DEG C, described first mixed gas composition is HCl gas or dichloroethylene gas, hydrogen and oxygen, and oxidization time is 5min ~ 10min;
Step 4: use the Semiconductor substrate that the pre-clear technique cleaning step three of described SiCoNi obtains;
Step 5: grow described silicon dioxide layer or described silicon oxynitride layer successively in the Semiconductor substrate that step 4 is formed, deposit described high dielectric radio gate dielectric layer.
3. as claimed in claim 2 for depositing the surface treatment method of high dielectric radio gate dielectric layer, it is characterized in that, the structure of Semiconductor substrate described in step one at least comprises fleet plough groove isolation structure, N well structure and P well structure.
4. as claimed in claim 2 for depositing the surface treatment method of high dielectric radio gate dielectric layer, it is characterized in that, the described impurity in step 2 comprises sodium, potassium ion and organic impurities.
5. as claimed in claim 2 for depositing the surface treatment method of high dielectric radio gate dielectric layer, it is characterized in that, use rapid thermal process apparatus when being oxidized described Semiconductor substrate in step 3 or described Semiconductor substrate is placed on boiler tube and be oxidized, when described first mist is HCl gas, hydrogen, oxygen, the total flow of described first mist is 0.5 ~ 15slm, wherein the ratio of hydrogen and oxygen is less than 1:1, and the ratio of HCl gas and oxygen is less than 1:5; When described first mist is dichloroethylene gas, hydrogen, oxygen, the total flow of described first mist is 0.5 ~ 15slm, and wherein the ratio of hydrogen and oxygen is less than 1:1, and the ratio of dichloroethylene gas and oxygen is less than 1:10.
6. as claimed in claim 2 for depositing the surface treatment method of high dielectric radio gate dielectric layer, it is characterized in that, using original position moisture-generation process in step 5 or using furnace process growth silicon dioxide layer or silicon oxynitride layer.
7. as claimed in claim 2 for depositing the surface treatment method of high dielectric radio gate dielectric layer, it is characterized in that, the thickness of described silicon dioxide layer or described silicon oxynitride layer is
8. as claimed in claim 1 or 2 for depositing the surface treatment method of high dielectric radio gate dielectric layer, it is characterized in that, the pre-clear technique of described SiCoNi is divided into remote plasma to etch and distillation two steps, and the gas that described remote plasma etches is NF
3and NH
3mist.
9. as claimed in claim 1 for depositing the surface treatment method of high dielectric radio gate dielectric layer, it is characterized in that, described high dielectric radio gate dielectric layer material is HfO
2or ZrO
2or Al
2o
3.
10. as claimed in claim 1 for depositing the surface treatment method of high dielectric radio gate dielectric layer, it is characterized in that, described high dielectric radio gate dielectric layer material thickness is
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510532420.9A CN105047553A (en) | 2015-08-26 | 2015-08-26 | Surface treatment method for depositing high-dielectric value gate medium layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510532420.9A CN105047553A (en) | 2015-08-26 | 2015-08-26 | Surface treatment method for depositing high-dielectric value gate medium layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105047553A true CN105047553A (en) | 2015-11-11 |
Family
ID=54454001
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510532420.9A Pending CN105047553A (en) | 2015-08-26 | 2015-08-26 | Surface treatment method for depositing high-dielectric value gate medium layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105047553A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107731834A (en) * | 2017-08-30 | 2018-02-23 | 长江存储科技有限责任公司 | A kind of core space layer insulation oxide layer CMP method for 3D NAND |
| CN110265285A (en) * | 2019-04-26 | 2019-09-20 | 芯盟科技有限公司 | The method for oxidation of semiconductor substrate and the manufacturing method of backside-illuminated sensor chip |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4863561A (en) * | 1986-12-09 | 1989-09-05 | Texas Instruments Incorporated | Method and apparatus for cleaning integrated circuit wafers |
| JP2002313787A (en) * | 2001-04-13 | 2002-10-25 | Tokyo Electron Ltd | Method for cleaning quartz product in heat treatment system and heat treatment method |
| CN101740338A (en) * | 2008-11-24 | 2010-06-16 | 中芯国际集成电路制造(北京)有限公司 | Method for removing film |
| CN102403272A (en) * | 2010-09-08 | 2012-04-04 | 北大方正集团有限公司 | Preparation method for high voltage complementary metal oxide semiconductor |
| CN103681288A (en) * | 2013-12-18 | 2014-03-26 | 无锡中微晶园电子有限公司 | High-reliability growth technique for low-temperature gate oxide layer |
| CN103928367A (en) * | 2014-03-20 | 2014-07-16 | 上海华力微电子有限公司 | Furnace tube device and method for reducing Cu pollution in furnace tube process |
| CN104392919A (en) * | 2014-11-19 | 2015-03-04 | 上海华力微电子有限公司 | Silicon base surface treatment method for NMOS element and manufacturing method of NMOS element |
| CN104701240A (en) * | 2015-03-31 | 2015-06-10 | 上海华力微电子有限公司 | Method for preparing high-k dielectric layer |
-
2015
- 2015-08-26 CN CN201510532420.9A patent/CN105047553A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4863561A (en) * | 1986-12-09 | 1989-09-05 | Texas Instruments Incorporated | Method and apparatus for cleaning integrated circuit wafers |
| JP2002313787A (en) * | 2001-04-13 | 2002-10-25 | Tokyo Electron Ltd | Method for cleaning quartz product in heat treatment system and heat treatment method |
| CN101740338A (en) * | 2008-11-24 | 2010-06-16 | 中芯国际集成电路制造(北京)有限公司 | Method for removing film |
| CN102403272A (en) * | 2010-09-08 | 2012-04-04 | 北大方正集团有限公司 | Preparation method for high voltage complementary metal oxide semiconductor |
| CN103681288A (en) * | 2013-12-18 | 2014-03-26 | 无锡中微晶园电子有限公司 | High-reliability growth technique for low-temperature gate oxide layer |
| CN103928367A (en) * | 2014-03-20 | 2014-07-16 | 上海华力微电子有限公司 | Furnace tube device and method for reducing Cu pollution in furnace tube process |
| CN104392919A (en) * | 2014-11-19 | 2015-03-04 | 上海华力微电子有限公司 | Silicon base surface treatment method for NMOS element and manufacturing method of NMOS element |
| CN104701240A (en) * | 2015-03-31 | 2015-06-10 | 上海华力微电子有限公司 | Method for preparing high-k dielectric layer |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107731834A (en) * | 2017-08-30 | 2018-02-23 | 长江存储科技有限责任公司 | A kind of core space layer insulation oxide layer CMP method for 3D NAND |
| CN107731834B (en) * | 2017-08-30 | 2019-01-01 | 长江存储科技有限责任公司 | A kind of core space layer insulation oxide layer CMP method for 3D NAND |
| CN110265285A (en) * | 2019-04-26 | 2019-09-20 | 芯盟科技有限公司 | The method for oxidation of semiconductor substrate and the manufacturing method of backside-illuminated sensor chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR940009597B1 (en) | Forming method of gate oxide film | |
| US6787440B2 (en) | Method for making a semiconductor device having an ultra-thin high-k gate dielectric | |
| TWI250578B (en) | Semiconductor device and manufacturing method therefor | |
| CN101425457B (en) | High dielectric constant grid dielectric material forming method and a semiconductor device | |
| US8598002B2 (en) | Method for manufacturing metal gate stack structure in gate-first process | |
| CN103295891B (en) | The manufacture method of gate dielectric layer, the manufacture method of transistor | |
| JP4277268B2 (en) | Method for manufacturing metal compound thin film, and method for manufacturing semiconductor device including the metal compound thin film | |
| KR101078498B1 (en) | Manufacturing method of insulator thin film | |
| CN104637801A (en) | Method for preparing SiC MOSFET (Metal-Oxide -Semiconductor Field Effect Transistor) grid oxide layer | |
| CN105244326B (en) | The passivation layer structure and its manufacture method of a kind of power device | |
| CN115784774B (en) | Method for improving SiC Mos interface characteristics | |
| JP4095326B2 (en) | Semiconductor device manufacturing method and semiconductor device | |
| CN104103509A (en) | Formation method of interfacial layer and formation method of metal gate transistor | |
| CN103632976B (en) | The forming method of transistor | |
| CN105047553A (en) | Surface treatment method for depositing high-dielectric value gate medium layer | |
| JP2006253440A (en) | Semiconductor device and method of manufacturing the same | |
| JP2008078253A (en) | Manufacturing method of semiconductor device | |
| JP4694769B2 (en) | Manufacturing method of semiconductor device | |
| JP2010016298A (en) | Method of forming thin metal oxide film | |
| US8691636B2 (en) | Method for removing germanium suboxide | |
| CN105304691B (en) | The method for being used to prepare the boundary layer of high-K dielectric layer | |
| CN111681961B (en) | Method for manufacturing semiconductor device | |
| CN104701240A (en) | Method for preparing high-k dielectric layer | |
| CN105206523A (en) | Method for manufacturing high-K dielectric layer | |
| JP2010093170A (en) | Method of manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20151111 |
|
| RJ01 | Rejection of invention patent application after publication |