CN104995732A - 用于具有封装键合元件的微电子封装的结构 - Google Patents

用于具有封装键合元件的微电子封装的结构 Download PDF

Info

Publication number
CN104995732A
CN104995732A CN201380073383.9A CN201380073383A CN104995732A CN 104995732 A CN104995732 A CN 104995732A CN 201380073383 A CN201380073383 A CN 201380073383A CN 104995732 A CN104995732 A CN 104995732A
Authority
CN
China
Prior art keywords
microelectronic element
bonding elements
dielectric block
conducting
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201380073383.9A
Other languages
English (en)
Inventor
贝尔加桑·哈巴
伊利亚斯·穆罕默德
特伦斯·卡斯基
雷纳尔多·柯
埃利斯·周
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Adeia Semiconductor Solutions LLC
Original Assignee
Tessera LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tessera LLC filed Critical Tessera LLC
Publication of CN104995732A publication Critical patent/CN104995732A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125—Reinforcing structures
    • H01L2224/10126—Bump collar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/1191—Forming a passivation layer after forming the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13017—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/13076—Plural core members being mutually engaged together, e.g. through inserts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1405—Shape
    • H01L2224/14051—Bump connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/14135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16104—Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/16105—Disposition relative to the bonding area, e.g. bond pad the bump connector connecting bonding areas being not aligned with respect to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701—Structure
    • H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1705—Shape
    • H01L2224/17051—Bump connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45014—Ribbon connectors, e.g. rectangular cross-section
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45155—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45599—Material
    • H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45624—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45599—Material
    • H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45655—Nickel (Ni) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15322—Connection portion the connection portion being formed on the die mounting surface of the substrate being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10515—Stacked components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

一种结构(10)包括键合元件(24)，键合元件(24)具有联接至第一表面的第一部分处的导电元件(18)以及远离衬底(12)的端面。介质封装元件(40)可覆盖且从第一部分延伸，且填充键合元件(24)之间的空间，以使键合元件(24)相互分离。封装元件(40)具有背离第一表面的第三表面。键合元件(24)的未封装部分由在第三表面处未被封装元件覆盖的端面的至少部分限定。封装元件(40)至少部分限定第一表面的第二部分(210)，第二部分(210)不同于第一部分且具有容纳微电子元件(602)的整个面积的面积。一些导电元件(18)在位于第二部分且用于与这种微电子元件(602)相连接。

Description

用于具有封装键合元件的微电子封装的结构
相关申请的交叉引用
本申请是2012年12月20日提交的美国专利申请No.13/722,189的继续申请，其公开内容通过引用并入本文。
技术领域
本发明涉及用于微电子封装的结构。
背景技术
微电子元件(如半导体芯片)通常设有保护该微电子元件且便于其与较大电路中的其他元件连接的元件。例如，半导体芯片典型地设置成小且平的元件，其具有相对的前表面和后表面，以及在前表面处的触点。触点电连接至一体形成在芯片内的很多电子电路元件。这种芯片通常设置在具有称为衬底的微型电路板的封装内。芯片典型地安装至衬底，芯片的前表面或后表面覆盖该衬底的表面，且该衬底典型地具有其表面处的端子。端子电连接至芯片的触点。典型地，封装也包括这种形式，其在芯片与衬底相对的侧面上覆盖该芯片。这种覆盖用于保护芯片，且在一些情况下，保护芯片与衬底的导电元件之间的连接部。这种封装芯片可通过将衬底的端子连接至导电元件(如较大的电路面板上的触点焊盘)安装至电路面板(如电路板)。
在某些封装中，芯片被安装成其前表面或后表面覆盖衬底的上表面，而端子设置在相对的下表面。由介电材料制成的介电块覆盖芯片，且最典型地，覆盖芯片与衬底的导电元件之间的电连接部。介电块可通过在芯片周围对可流动的介电成分进行注塑而形成，以使介电成分覆盖芯片以及衬底的顶表面的全部或部分。这种封装通常被称为“包胶模(overmolded)”封装，且由介电材料制成的介电块被称为“包胶模(overmold)”。包胶模封装制作经济且因此被广泛应用。
在一些应用中，所期望的是将芯片封装堆叠至另一个的顶部，以使多个芯片可设置在较大的电路面板的表面上的同一空间内。同样，所期望的是有大量的至芯片的输入/输出互联部。某些包胶模封装包括在芯片覆盖的区域外以及典型地由包胶模覆盖的区域外的衬底的顶表面上的堆叠触点。这种封装可通过互连元件(如在堆叠中较低封装的堆叠触点和下一个较高封装的端子之间延伸的焊锡球、细长接线柱、线键合或其他导电连接)堆叠在另一个顶部。在这种布置中，堆叠中的所有封装电连接至堆叠底部的封装上的端子。另外，因为堆叠中较高封装的衬底位于下一个较低封装的介电包胶模上方，故在垂直方向上较高封装的端子和较低封装的堆叠触点之间有明显的间隙。互连元件必须弥合这个间隙。
尽管本领域内已经在可堆叠封装和具有顶表面安装焊盘的其他封装的发展上付出了大量努力，但仍然需要进一步提高。
发明内容
根据一个实施例，结构可包括衬底，该衬底具有相对的第一表面和第二表面，以及在第一表面处的多个导电元件。另外，该结构可包括键合元件，该键合元件具有联接至第一表面的第一部分处的各个导电元件的基，以及远离衬底和基的端面，其中每个键合元件从其基延伸至其端面。进一步地，该结构可包括介质封装元件，该介质封装元件覆盖衬底的第一表面的第一部分且从衬底的第一表面的第一部分延伸，且填充键合元件之间的空间，以使键合元件通过封装元件相互分离，封装元件具有背离衬底的第一表面的第三表面且具有从第三表面向第一表面延伸的边缘表面，其中键合元件的未封装部分由在第三表面处未被封装元件覆盖的键合元件的端面的至少部分限定。封装元件至少部分限定第一表面的第二部分，该第二部分不同于第一表面的第一部分且具有容纳微电子元件的整个面积的面积，而且第一表面处的至少一些导电元件位于第二部分且用于与这种微电子元件相连接。
根据另一个实施例，结构的制作方法可包括在衬底上形成介质封装元件，该衬底具有相对的第一表面和第二表面，以及在第一表面处的多个导电元件，其中键合元件在其基处联接至第一表面的第一部分处的各个导电元件，以及键合元件的端面远离衬底和所述基，每个键合元件从其基延伸至其端面。形成介质封装元件，以覆盖衬底的第一表面的第一部分且从衬底的第一表面的第一部分延伸，且填充键合元件之间的空间，以使键合元件通过封装元件相互分离。封装元件具有背离衬底的第一表面的第三表面且具有从第三表面向第一表面延伸的边缘表面，其中键合元件的未封装部分由在第三表面处未被封装元件覆盖的键合元件的端面的至少部分限定，且其中封装元件至少部分限定第一表面的第二部分，该第二部分不同于第一表面的第一部分具有容纳微电子元件的整个面积的面积，而且第一表面处的至少一些导电元件位于第二部分且用于与这种微电子元件相连接。
根据另一个实施例，结构可包括有源晶元，该有源晶元具有相对的第一表面和第二表面，以及在第一表面处的多个导电元件。另外，结构可包括键合元件，该键合元件具有联接至第一表面的第一部分处的各个导电元件的基，以及远离晶元和基的端面，每个键合元件从其基延伸至其端面。进一步地，该结构可包括介质封装元件，该介质封装元件覆盖晶元的第一表面的第一部分且从晶元的第一表面的第一部分延伸，且填充键合元件之间的空间，以使键合元件通过封装元件相互分离。该封装元件具有背离晶元的第一表面的第三表面且具有从第三表面向第一表面延伸的边缘表面，其中键合元件的未封装部分由在第三表面处未被封装元件覆盖的键合元件的端面的至少部分限定。封装元件可至少部分限定第一表面的第二部分，该第二部分不同于第一表面的第一部分且具有以容纳微电子元件的整个面积的面积，而且第一表面处的至少一些导电元件位于第二部分且用于与这种微电子元件相连接。
根据另一个实施例，结构的制作方法可包括在以晶片级提供的有源晶元上形成介质封装元件。该晶元可具有相对的第一表面和第二表面，以及在第一表面处的多个导电元件，其中键合元件可在其基处联接至第一表面的第一部分处的各个所述导电元件，以及键合元件的端面远离衬底和基，每个键合元件从其基延伸至其端面。形成介质封装元件，以覆盖晶元的第一表面的第一部分且从晶元的第一表面的第一部分延伸，且填充键合元件之间的空间，以使键合元件通过封装元件相互分离。封装元件具有背离晶元的第一表面的第三表面且具有从第三表面向第一表面延伸的边缘表面，其中键合元件的未封装部分由在第三表面处未被封装元件覆盖的键合元件的端面的至少部分限定，且其中封装元件至少部分限定第一表面的第二部分，该第二部分不同于第一表面的第一部分具有容纳微电子元件的整个面积的面积，而且第一表面处的至少一些导电元件位于第二部分且用于与这种微电子元件相连接。
附图说明
图1是根据本发明实施例的在结构的制作方法中所用的衬底的示意性剖视图；
图2是根据本发明实施例的制作操作的后阶段中的衬底和关联元件的示意性剖视图；
图3是根据本发明实施例的利用图1至图2所示中的衬底和关联元件制作的结构的示意性剖视图；
图4A是根据本发明实施例的示例性结构的示意性剖视图；
图4B是制作操作的后阶段中的图4A所示的结构的示意性剖视图；
图4C是根据本发明实施例的另一个示例性结构的示意性剖视图；
图4D是制作操作的后阶段中的图4C所示的结构的示意性剖视图；
图5是根据本发明实施例的另一个示例性结构的示意性剖视图；
图6是根据本发明实施例的另一个示例性结构的示意性剖视图；
图7A是图3所示的结构的示意性俯视图；
图7B至图7C是根据本发明的示例性结构的示意性俯视图；
图7D是图5所示的结构的示意性俯视图；
图7E是根据本发明的示例性结构的示意性俯视图；
图8是根据本发明的包括图3所示的结构的示例性封装组件的示意性剖视图；
图9是根据本发明的包括图3所示的结构的另一个示例性封装组件的示意性剖视图；
图10A是根据本发明的包括图3所示的结构的另一个示例性封装组件的示意性剖视图；
图10B是根据本发明的包括图3所示的结构的另一个示例性封装组件的示意性剖视图；
图11是图10A所示的封装组件的仰视图；
图12是根据本发明的包括图5所示的结构的示例性封装组件的示意性剖视图；
图13是根据本发明的系统的示意性剖视图；
图14是根据本发明实施例的制作结构的后阶段中的有源晶元和关联元件的示意性剖视图；
图15是根据本发明实施例的利用图14所示的晶元和关联元件制作的结构的示意性剖视图；
图16A是根据本发明实施例的包括有源晶元的示例性结构的示意性剖视图；
图16B是制作操作的后阶段中图16A所示的结构的示意性剖视图；
图16C是根据本发明实施例的包括有源晶元的另一个示例性结构的示意性剖视图；
图16D是制作操作的后阶段中图16C所示的结构的示意性剖视图；
图17是根据本发明的包括图15所示的结构的示例性封装组件的示意性剖视图；
图18是根据本发明的包括图15所示的结构的示例性封装组件的示意性剖视图；
图19是根据本发明的包括图15所示的结构的示例性封装组件的示意性剖视图；
图20是根据本发明的包括结构的示例性封装组件的示意性剖视图；以及
图21是根据本发明的包括结构的示例性封装组件的示意性剖视图。
具体实施方式
根据本发明的一个实施例的结构10(参见图3)可包括具有第一表面14和第二表面16的衬底12(参见图1)。衬底12典型地为基本上平坦的介质元件的形式。介质元件可为片状且可以很薄。在特定实施例中，介质元件可包括一层或多层有机介质材料或合成介质材料，例如(但不限于)，聚酰亚胺，聚四氟乙烯(PTFE)，环氧树脂，环氧玻璃，FR-4，BT树脂，热塑性材料或热固塑料材料。第一表面14和第二表面16优选为基本上相互平行，且在垂直于表面14和16的方向上相互间隔开一段距离以限定衬底12的厚度。衬底12的厚度优选为本发明大体可接受厚度范围内。在一个实施例中，第一表面14和第二表面16之间的距离大约为25μm-500μm。为了上述目的，第一表面14可布置成相对于或远离第二表面16。这种描述以及在此使用的元件的相对位置(即这些元件的垂直或水平位置)的任何其他描述仅仅是相对于附图中的元件的位置所作的示意性说明，不用于限定本发明。
可包括触点或焊盘，迹线(trace)或端子的导电元件18在衬底12的第一表面14处。如本文中使用的，导电元件在衬底的表面“处”的描述说明了当衬底没有与任何其他元件组装时，导电元件可以与在垂直于衬底的表面的方向上从衬底外部向衬底的表面移动的理论点接触。因此，在衬底的表面处的端子或其他导电结构可从这样的表面突出；可与这样的表面平齐；或者可相对于这样的表面凹入衬底中的孔或凹入部内。另外，如本文中使用的，导电元件在电路板或微电子元件(例如半导体芯片或类似的元件)的表面“处”的描述说明了当板或元件没有与任何其他元件组装时，导电元件可以与在垂直于面板或元件的表面的方向上从面板或元件外部向面板或元件的表面移动的理论点接触。另外，如本文中使用的，迹线“沿着”表面延伸的描述意味着迹线在接近于表面且大体平行于表面的方向上延伸。
包括作为导电元件18的迹线29可形成为表面14处的平薄且细长的导电材料条。在一些实施例中，迹线可与包括作为具有类似组成的导电元件18的端子27一体形成且从端子27延伸。另外，在表面14处的包括作为导电元件16的触点焊盘26可通过表面14处的迹线29互连。
用作导电元件18的端子、焊盘或迹线可通过很多已知的方法制作，例如，在衬底的表面14上电镀端子、焊盘或迹线。在一个实施例中，迹线可嵌入衬底的表面内，迹线的表面大体与衬底表面齐平。在一个实施例中，导电元件18可由固体金属材料形成，固体金属材料例如为铜、金、镍或其他该应用可接受的材料，包括各种合金，该合金包含铜、金、镍或其组合中的一种或多种。
至少一些导电元件18可与衬底12的第二表面16处的第二导电元件20互连，第二导电元件20可包括关于导电元件18所描述类似的导电焊盘、迹线或端子。使用形成在内衬有或填充有导电金属的衬底12中的通孔22以完成这种互连，衬底12可以衬有或填充与导电元件18和20相同的材料。优选地，衬底12中的通孔22被衬底12的表面14或16处的迹线或衬底12内的迹线19完全封闭。衬底12可包括多个介质材料层23，且相邻层23之间设有一层迹线19。包括作为导电元件18的触点焊盘25和端子31可通过用作导电元件18的表面16上的迹线33进一步互连。
参见图2，结构10可进一步包括在表面14的部分50处联接至至少一些导电元件18(如导电元件18的焊盘26)的多个线键合24。部分50可包括表面14的一个或多个区域，例如图7A所示的部分50A和50B。键合元件24在其基28处联接至焊盘26且可延伸至远离各个基28和远离衬底12的自由端部30。键合元件24的端部30是自由的特征在于，其没有电连接或以其他方式联接至微电子元件，该微电子元件电连接至表面14处的导电元件18或包括结构10的微电子组件内的任何其他导电特征，这些其他导电特征又连接至这个微电子元件。换句话说，自由端部30可以直接或间接地通过焊锡球或在此所述的其他特征直接或间接地电连接至包括结构10的微电子组件外部的导电特征。端部30通过封装材料(举例而言，形成在下文中结合图3和图4A至图4D所述的介质封装元件40的封装材料)保持在预定的位置或以其他方式联接或电连接至另一个导电特征，这并不意味着端部30不是如在此所述的“自由”，只要任何这种特征没有电连接至微电子元件即可，这种微电子元件在表面(例如表面14或16)处联接至导电元件，其基联接至该表面。相反地，如在此所述，基28不是自由的，因为它直接或间接地电连接至在表面14或16处连接的微电子元件22。
如图2所示，基28的形状可基本为圆形，且从键合元件24的边缘表面32向外延伸，该键合元件24可以是基28和端部30之间限定的线键合。基30的特定尺寸和形状可根据用于形成线键合24的材料类型，线键合24和导电元件18之间期望的连接强度，或用于形成线键合24的特定工艺而改变。制作线键合24的示例性方法在美国专利No.7,391,121,Otremba和美国专利申请公开No.2005/0095835中描述，两者的公开内容皆通过引用全部并入本文。在可选实施例中，一些线键合24可通过导电元件19和衬底12中通孔22的导电材料连接至衬底12的第二表面16处的导电元件20。
键合元件24可由导电材料(如铜、金、镍、焊锡、铝等)制成。此外，键合元件24可由各种材料的组合制成，例如由导电材料(如铜或铝)的芯和涂布在芯上的涂层制成。涂层可由第二导电材料(如铝，镍等)制成。可选地，涂层可由绝缘材料(如绝缘夹套)制成。在一个实施例中，用于形成键合元件24的线可具有约15μm-150μm的厚度(即横穿线的长度的尺寸)。
在包括其中使用楔形键合的其他实施例中，键合元件24可具有厚达约500μm的厚度。一般而言，线键合使用本领域已知的专用设备而形成在导电元件(例如可为焊盘等的导电元件26)上。线段的前端经加热且压着线段所键合的容纳表面，典型地，形成联接至焊盘26的表面的球状或类似于球状的基28。从键合工具拉伸出用于形成线键合的线段的期望长度，然后该键合工具可在期望长度处切割线键合。例如，可用于形成铝线键合的楔形键合是这样的过程，其中线的加热部分被牵引跨过容纳表面以形成与表面大体平行的楔子。然后经楔形键合形成的线键合可向上弯曲(如果需要)，且在切割之前延伸至期望长度或位置。在特定实施例中，用于形成线键合的线的横截面可为圆柱形。另外，从工具进给的用于形成线键合或楔形线键合的线可具有多边形(例如矩形或梯形)横截面。
线键合24的自由端部30具有端面34。端面34可形成由多个线键合24的各个端面34形成的阵列中的触点的至少一部分。
参见图3，结构10可进一步包括由介质材料形成的封装层元件40A和40B。在图3所示的实施例中，封装层元件40可形成在衬底12的第一表面14的部分50上，且限定远离且背离衬底12的顶表面42。元件40的材料填充键合元件24之间的空间，以使键合元件24通过封装元件40相互分离。键合元件24的未封装部分52由键合元件24的端部30的至少部分限定，优选地由其端面34限定，且未被封装元件40所覆盖，例如，在表面42处。
在特定实施例中，很多结构的衬底被提供为连续的或半连续的元件，例如条、带或片，尽管图1至图2中各个衬底之间没有可见的边界。在封装元件40形成在衬底上之后，结构10被沿着分割线62(图2没有显示各个衬底之间可见的边界)分割，以获得具有图3所述配置的单个结构10，且其中结构10的衬底12在相对边缘64之间延伸。图1至图2仅描述了适于制作多个结构的衬底片的部分，这些结构可容纳在其衬底的被限定部分上的微电子元件，这些将在下文具体描述。
参见图3，封装层元件40A和40B可分别限定第一边缘表面44A和44B，其分别从邻近顶表面42的顶部边线56向下延伸至邻近衬底12且设置在衬底12的边缘64内的底部边线58。进一步参见图7A，底部边线58设置在由衬底的边缘64界定的水平区域66内。在一个实施例中，第一边缘表面44A和44B分别从元件40A和40B的表面42正交地延伸，且表面14和表面42相互平行延伸，以使边线56、58在结构10的厚度方向上对齐。
在另一实施例中，第一边缘表面44A和44B中的一个或两个可以相对于顶表面42小于90°的倾斜角，在水平方向上从顶表面42向另一个元件40A或与其相对的元件40B倾斜，以使第一边缘表面44的底部边线58在向着相对元件40的水平方向上比顶部边线56离顶表面42更远，类似于2012年11月12日申请的美国专利申请No.13/674,280中描述的，其公开内容通过引用并入本文。
在一个实施例中，参见图7A，第一边缘表面44可通过塑形使得在离衬底12一段固定的垂直距离处沿着第一边缘表面44延伸的任何直线设置在第一水平方向H1的固定位置处。例如，在离衬底一段固定的垂直距离处延伸的虚线68(图7A)将位于一个固定的水平位置。在一些实施例中，第一边缘表面44大体为平坦的。
元件40A和40B可进一步包括第二边缘表面46A和46B，其分别从从顶表面42向衬底向下延伸。类似于表面44的表面46A和46B可从顶表面42和14向衬底正交地延伸，或可选地可分别在水平方向H2和H1上倾斜远离表面42。类似于边缘表面44，边缘表面46可通过塑形使得在离衬底12一段固定的垂直距离处沿着表面46延伸的任何直线分别设置在水平方向H2和H1上的固定位置处，类似于上文关于边缘表面44的描述。
封装元件40可具有在与水平方向H2和H1的正交的方向上延伸远离表面14至少大约150μm的厚度(h)。封装元件40也可覆盖区域50内的未以其他方式被键合元件24覆盖的一些导电元件18，包括其焊盘26。
封装元件40可至少部分地，且优选大体上封装联接至区域50内的导电元件26的线键合24，包括基28和键合元件的边缘表面32的至少部分。线键合24的部分可保持不被封装元件覆盖，该部分也可称为未封装的，由此使线键合24能够电连接至位于封装元件40外部的特征或元件。在一个实施例中，线键合24的端面34在封装元件40的表面42处保持不被封装元件40覆盖。除了或者可选的，使端面34保持不被封装层40覆盖，边缘表面32的部分未被封装元件40覆盖的其他实施例也是可行的。换句话说，封装元件40可覆盖覆盖在第一表面14的部分50上部件的所有部分(除线键合24的部分(例如至少端面34)之外)，以及边缘表面32的可选部分，或者两者的组合。在如图所示的实施例中，封装层40的表面42可以与衬底12的第一表面14间隔开，间隔距离足以覆盖除了端部30处的键合元件24的部分之外所有元件。参见图3，结构10的实施例可具有不与表面42齐平的线键合24的端面30，例如线键合24具有从表面42突出且终止于离表面42相同距离处的端面34的端部。
可选地，本发明的实施例可包括如图4A所示的结构10-1，该结构包括类似于上述结构10的那些部件。参见图4A，结构10-1可包括封装元件40A’和40B’，两者均具有大体上平坦且平行于衬底12的平坦表面14的顶表面42。元件40A’和40B’可封装具有分别离表面42不同距离处的端面34’和34”的线键合24’和24”,且分别限定包括端面34’和34”的部分52’和52”以及边缘表面32’和32”的部分。在一些实施例中，键合元件24的端面34可为平坦的，且其边缘表面32可为平坦的且垂直于端面34而延伸。
键合元件24的具有未封装部分52的配置(如图3和图4A所示)可提供至另一个导电元件的连接，例如通过图4B所示的焊锡球170等，通过允许焊锡吸附在边缘表面32且联接至边缘表面32和端面34。焊锡球170也可从边缘表面32延伸到表面42的未覆盖部分上。
由根据本发明的结构的封装元件40封装的线键合的24的其他配置也是可行的。例如，图4C显示了具有被封装元件140A封装的线键合24-1的结构10-2的实施例，封装元件140A的端部30-1没有直接定位在其基28-1之上。换言之，考虑到衬底12的第一表面14在两个横向上延伸，以大体上限定平面(参见图7A)，延伸穿过封装元件140A的线键合24-1的端部30-1可在这些横向中的至少一个上从基28-1的相应的横向位置位移。如图4C所示，线键合24-1可以沿着其纵向轴线基本是直的，如图3和图4A的实施例所示，纵向轴线相对于衬底12的第一表面14成角度116。虽然图4C的剖视图只示出在垂直于第一表面14的第一平面的角度116，线键合24-1也可在垂直于第一平面和第一表面14的另一个平面内相对于第一表面14成一个角度。这个角度可基本等于或不同于角度116。换言之，端部30-1可相对于基28-1在两个横向上位移，且可以在每个横向上位移相同或不同的距离。
在一个实施例中，由元件140A封装的各个线键合24-1和24-2可在不同方向上位移且可以沿着第一表面14在封装元件140A内位移不同量。这种布置允许结构10-2具有配置在元件140A的表面142的水平面上的阵列，其中元件140A的表面142的水平面不同于衬底12所在的水平面。例如，与在衬底12的第一表面14处相比较，阵列在表面142的水平面上可以覆盖较小或较大的总面积或具有较小或较大的节距。进一步，一些线键合24-1可具有定位在衬底12之上的端部30-1，以容纳不同大小的封装的微电子元件的堆叠布置。在另一示例中，线键合24-1可以配置为一个线键合24-1的端部30-1大体定位在另一个线键合24-1的基28-1之上，且另一个线键合24-1的端部30-1定位在其他地方。这种布置可称为相对于另一表面(例如表面14)上的相应的触点阵列的位置，在触点阵列内改变触点端面34的相对位置。在这种阵列中，触点端面的相对位置可如所期待的根据有结构10-2形成的微电子组件的应用或其他要求而改变或变化。
在如图4C所示的进一步示例中，由元件140A封装的线键合24-1可布置为基28-1布置成具有节距的第一图案。线键合24-1可配置为其未封装部分52(包括端面30-1)可设置成在封装元件140A的表面142的位置处的图案，未封装部分52具有大于附接至区域50内的导电焊盘26的的线键合24-1的各相邻基28-1之间的最小节距的最小节距。相应地，在表面142上相邻线键合之间的最小节距可大于线键合所附接的衬底的导电焊盘26之间的相应最小节距。为了实现这点，线键合可成角度，或可以例如如图4C所示弯曲，如上所述，以使端部30从基28在一个或多个横向上位移。在一个实施例中，导电元件26和端部30可布置成各行或各列，且在一行中的端面34的横向位移可大于另一行中的位移。为了实现这点，线键合24可例如相对于衬底12的表面14成不同角度116。
图4C示出进一步实施例，其中线键合24-2具有相对于其基24-2位于位移的横向位置处的端部30-2。在图4C的实施例中，线键合24-2通过包括其中的弯曲部分118而实现横向位移。弯曲部分118可在线键合形成过程的额外步骤中形成，且例如，当线部分被拉伸至期望长度时，可出现弯曲部分118。利用可用的线键合设备可进行这一步骤，其中可以包括使用单个机器。
根据需要，弯曲部分118可采用多种形状以达到线键合24-2的端部30-2的期望位置。例如，如图4C所示，弯曲部分118可形成为各种形状的S型曲线(例如包括在线键合24-2(A)内)或更平滑的形式(如在线键合24-2(B)内)。此外，弯曲部分118可布置在比接近端部30-2而更接近基28-2的位置，反之亦然。弯曲部分118可为螺旋形或环形，或为包括多个方向上的或不同形状或性质的曲线的组合。
在一个实施例中，结构10-2可包括封装元件140，每个封装元件140具有封装在其内的不同类型的键合元件24。参见图4C，元件140A可包括线键合或用作键合元件24的线，且封装元件140B可包括用作键合元件124的大体垂直的导电特征，例如微柱或接线柱。
应当理解的是，如图4C所示，结构可包括具有导致基和端部之间各种相对的横向位移的各种形状的键合元件的组合。键合元件24中的一些基本上是直的且端部30定位图3和图4A所示的各个基28之上，而其他键合元件24包括导致端部30和基28之间略微相对的横向位移的弯曲部分118。进一步地，一些键合元件24包括具有流线型形状的弯曲部分118，该弯曲部分118导致端部30从相关的基28横向位移一段大于端部28横向位移的距离的距离。
在键合元件24的这种实施例中，键合元件的线键合可配置成在端部30处未被封装元件覆盖且沿着其边缘表面的至少部分延伸远离端面34。如图3和图4A，4C所示，键合元件的自由端部未被覆盖，但是边缘表面32的部分可另外或可选地不被封装元件覆盖。这种配置可用于通过电连接至适当的特征而将包括结构的微电子组件接地，或用于机械或电连接至横向布置在微电子组件上的其他特征。
此外，参见图4C，封装元件140B可封装键合元件124，该键合元件124在其基128处以接线柱或微柱的形式连接至表面14处的导电元件26。元件140B可配置成包括经过刻蚀、模塑或其他方式形成的区域，以限定定位成比表面142更接近衬底12的凹入表面144。一个或多个微柱124-1可在沿着凹入表面144的区域内不被覆盖。在图4C所示的示例性实施例中，端面134-1和微柱124-1的边缘表面132-1的部分未被封装元件140B覆盖，以形成键合元件124-1的未封装部分152。
在一个实施例中，接线柱124-1的基128-1可通过凸点165联接至表面14上的导电元件26。凸点基本上包括由铜、镍、银、铂及金中的一种或多种组成的端部38，且当接线柱124-1由不可润湿的金属制成时,提供形成导电互连的方法。
类似于键合元件24，参见图4D，键合元件124的这种配置可提供至另一个导电元件的连接，例如通过焊锡球170等，通过允许焊锡吸附在边缘表面132-1且联接至边缘表面132-1和端面134-1，且其中焊锡可沿着表面144从边缘表面132-1延伸。键合元件124的部分可不被封装元件140B沿着凹入表面144覆盖的其他配置也是可行的，这些配置包括其中端面大体与凹入表面144平齐的配置。
参见图4C，结构10-2可包括微柱形式的具有通过凸点165联接至导电元件26的基128-2的键合元件124-2，端面134-2，以及从端面134-2延伸且限定在表面142处的线键合124-2的未封装部分152的边缘表面132-2。在另一个实施例中，结构10-2可包括微柱形式的键合元件124-3，该键合元件124-3与表面14处的导电元件26一体形成且从表面14延伸至端面134-3。键合元件124-3包括端面134-3和从端面134-3延伸的作为表面142处的未封装部分152的边缘表面132-3。
在进一步的实施例中，元件140B可配置成包括经过刻蚀、模塑或其他方式形成的区域，以限定从表面142延伸至衬底表面14的腔175。腔175可具有允许在形成在腔175内键合元件124-4的端面134-4处电连接的任何合适的形状，例如通过其中导电材料沉积，键合元件124-4具有作为未封装部分152的端面134-4。在一个实施例中，键合元件124-4可形成在具有锥形侧壁的梯形腔175内。键合元件124-4可具有端面134-4，端面134-4的横截面比基128-4和端面134-4之间的部分的横截面宽，其中基128-4和端面134-4相互平行，且边缘表面132-4从基128-4相向成锥形地延伸至端面134-4。
参见图4D，焊锡170可沉积在腔175内，以从端面134-4延伸至表面142之上，且沿着表面142的部分延伸远离腔175。
应当理解的是，根据本发明，结构可包括其他配置，通过该配置键合元件的部分未被封装元件(例如在端面处且可选地沿着其边缘表面)覆盖，这些配置类似于那些上述的远离且背离衬底的表面的封装元件的表面的多种配置。
参见图3，例如，封装元件40用于保护区域50内的导电元件18，包括在区域50内与焊盘26连接的键合元件24。这保障更加坚固的结构，以使在对其检测或运输或组装至其他微电子结构的过程中不太可能被损坏。封装元件40可由具有绝缘性能的介质材料形成，例如美国专利申请公开No.2010/0232129中描述的，其公开内容全部通过引用并入本文。
图3和图7A示出了由结构10的键合元件24的端面34形成的触点阵列的示例性图案。这种阵列可形成为面阵配置，使用在此所述的结构可实现阵列变型。这种阵列可用于将包括结构10的微电子组件10电连接和机械连接至另一个微电子结构，例如印刷电路板(“PCB”)，或其他封装的微电子元件。在这种堆叠布置中，线键合24和导电元件18和20可通过该布置承载多个电子信号，每个电子信号具有不同的信号电位以允许不同的信号由单个堆叠中不同的微电子元件处理。焊锡块可用于这种堆叠中微电子组件的互连，例如通过将端面34电附接和机械附接至外部部件的导电元件。
参见图3和图7A，结构10的衬底14的表面14和16在水平方向H1和H2上延伸，且结构90的边缘64在上表面和下表面之间延伸。封装元件40A和40B可限定具有预定尺寸和形状的微电子元件容纳区域210，以容纳微电子元件(例如单独的半导体芯片，或包括至少一个芯片的微电子组件或微电子封装)，被容纳的微电子元件从元件40A和40B横向设置且在由区域210的底部部分212覆盖的表面14的部分处连接至衬底12。例如，参见图7A，底部部分212可具有在水平方向H1上从元件40A的底部边线58延伸至元件40B的底部边线58的线性尺寸R1，以及在正交于方向H1的水平方向上在元件40的相对端部205之间延伸的线性尺寸R2，该元件40在平行于水平方向H1的方向上延伸。区域210包括在底部部分212处从表面14的暴露部分和表面14处的导电元件18向上延伸至离衬底的表面14一段预定垂直距离处的空间，当从表面14垂直测量时，该空间可以在元件40中的一个或两个的表面42的高度上方或下方或相同高度。由此区域210包括限定在封装元件40A和40B各自表面44A和44B之间的空间。区域210具有基于衬底的表面14上的封装元件40的尺寸、形状和定位的预定的尺寸和形状，且假设微电子元件的一部分可设置在不带接触表面42A和42B的元件、封装或组件的区域210内，该部分是其自身的，或封装或组件之内的待连接至由部分212覆盖的衬底的一部分的微电子元件的一部分。
根据本发明的进一步实施例的制作结构10的工艺可利用预形成的介电块，例如基本上包括介电材料的衬底，且利用模具元件(未示出)来形成封装键合元件24的封装元件40的介电块。在此工艺中，与衬底12的表面14处的焊盘26连接的键合元件可在存在于模塑阶段。在一个实施例中，形成元件40的介电块可模塑在键合元件24之上，键合元件24连接至衬底12的表面14上的迹线18。
另外，如上所述和如图3所示，用作封装元件的预形成介电块封装键合元件以限定未封装部分，且具有顶表面42和边缘表面44和46，该介电块可附接至衬底12的表面14的部分50，利用粘合剂(例如可固化粘合剂或环氧树脂)与另一个类似的封装元件横向隔开。
在封装元件形成在衬底12之前的制作结构10的进一步步骤中，用作导电元件18的迹线和焊盘可图案化至表面14。例如，整个表面14可被电镀、、掩模以及选择性地刻蚀以形成迹线。可选地，表面14可由掩膜材料覆盖，然后选择性地暴露在激光辐射下以通过掩膜开槽。种层可施加在掩膜上及槽内，掩膜被移除以剥离除了槽以外任何地方的晶种层。然后将表面暴露在电镀槽，以使金属仅在种存在的槽处沉积。可以利用其他任何技术，用于在介质体上形成金属特征。
在其他实施例中，用来形成封装元件40的可流动的介电材料可用作粘合剂，将封装元件键合至衬底12。
参见图7B、图7C和图7E，根据本发明实施例，在衬底上的封装元件的可选布置可以用于获得微电子元件容纳区域，其中封装元件封装与衬底连接的键合元件。例如，一个或多个封装元件300可形成在衬底312(例如类似于衬底12)的上表面304上，以使具有尺寸、形状和在上表面304(例如相对于另一个表面)上的布置，以限定具有可容纳微电子元件、封装或组件的尺寸及形状的微电子元件容纳区域(类似于上述区域210)。参见图7B，可以布置四个封装元件300以限定覆盖衬底312的上表面304且具有底部区域306的区域302，底部区域306具有水平延伸尺寸R3和R4，其中R4在结构的厚度方向上分别与在其相对边缘表面上的元件300A和300B的上边线和下边线对齐，R3在结构的厚度方向上分别与在其相对边缘表面上的元件300C和300D的上边线和下边线对齐。参见图7C，封装元件300可为单个元件，该单个元件限定具有矩形形状的底部部分306的区域302，其三边有这个单个元件限定。参见图7E，单个封装元件450可布置成覆盖衬底456的上表面454，以限定具有覆盖表面454的部分454A的底部部分456的微电子元件容纳区域452。元件450覆盖表面454的部分454B，且该部分454B完全包围部分454A。这种元件450在至少区域452的部分处完全包围容纳区域452，容纳区域452垂直延伸远离部分454A。
参见图5和图7D，在一个实施例中，具有类似于结构10的那些部件的结构400可包括单个封装元件440，或多个封装子元件440A、440B和440C，多个封装子元件440A、440B和440C封装键合元件424以在背离衬底的子元件440的表面442处提供由键合元件424的至少端面434限定的未封装部分452。例如，参见图7D，单个元件440可限定多个覆盖衬底上表面414且分别具有底部部分406A和406B的微电子容纳区域402A和402B。可选地，子元件440A、440B和440C(由图7D中无交叉影线的元件440的部分显示)可布置成相互平行且相互间隔，以限定区域402A和402B，类似于图3和图4A中的元件40A和40B。
参见图6，在一个实施例中，具有类似于结构10的构造的结构500可包括在衬底12的表面14上的封装元件40A和40B，以限定区域210。另外，封装元件540在提供由端面534和边缘表面532的部分限定的未封装部分550时，可覆盖表面16的部分560且封装联接至区域560内的焊盘522的键合元件524。在一个实施例中，封装元件540可至少部分地覆盖由部分212覆盖的表面14的部分。在一些实施例中，封装元件540可覆盖表面16以限定至少一个微电子元件容纳区域570，该至少一个微电子元件容纳区域570具有覆盖表面16的部分574的底部部分572且从部分560延伸至衬底12的相对边缘64。
参见图14和图15，在本发明的另一个实施例中，结构1010可包括以晶片级提供的有源晶元1012，例如现场可编程门阵列。晶元1012可具有包括电路系统1016和键合焊盘1018的有源表面1014。典型地，晶元1012是具有730μm厚度的硅，且电路系统1016可由任何合适的常规技术提供。可选地，晶元1012可为任何其他合适的材料(例如砷化镓)，且可具有任意合适的厚度。介电材料的再分布层1020可沿着表面1014延伸。迹线1022可电连接至层1020的表面1017处的触点焊盘1024，表面1017远离表面1014，而且迹线1022可穿过再分布层1020的衬底1026延伸至表面1014处的焊盘1018。类似于图2所示的结构10，键合元件24可在其基处与至少一些焊盘1024联接，焊盘1024穿过迹线1022在表面1014的部分1050处与焊盘1018联接。在结构中省略了再分布层1020的另一个实施例中，键合元件24的基28可通过焊锡元件(未示出)在部分1050处与焊盘1018联接。
参见图15，结构1010可进一步包括封装元件1040A和1040B，封装元件1040A和1040B具有类似于上述组件10中封装元件40的特征，由衬底12的表面1014的部分1050之上的介电材料形成，且限定远离且背离晶元1012的顶表面1042。元件1040的材料填充键合元件24之间的空间，且未封装部分52由键合元件24的端部30的至少部分限定。另外，封装元件1040A和1040B可以分别限定第一边缘表面1044A和1044B，第一边缘表面1044A和1044B从邻近顶表面1042处向下延伸至再分布层1020的表面1017，或当层1020被省略时，向下延伸至表面1014，其中表面1044设置在晶元1012的外围边缘1064内。元件1040A和1040B可分别进一步包括第二边缘表面1046A和1046B，第二边缘表面1046A和1046B从顶表面1042向下延伸至层1020的表面1017或晶元1012的表面1014，类似于上述延伸至衬底12的元件40的表面46。封装元件1040可配置成类似于图4A和图4B所示的封装元件40’和140，以封装键合元件24和不覆盖其未封装部分52。
在一些实施例中，很多结构的晶元被提供为连续的或半连续的元件，例如条、带或片。在封装元件1040形成在晶元上之后，结构1010被沿着分割线分割，以获得具有图15所示的配置的单个结构1010，且其中结构1010的晶元1012在相对边缘1064之间延伸。
可选地，本发明的实施例可包括如图16A所示的结构1010-1，该结构包括类似于上述结构1010的那些部件。参见图16A，结构1010-1可包括线键合24-1，一些线键合24-1可包括弯曲的或类似于图4C所示的大体笔直的部分，其被封装元件1040A封装，封装元件1040A的各个端部30-1没有直接定位在其基28-1之上，以使结构1010-1可具有不同地配置在元件1040A的水平面处的阵列，元件1040A的水平面相比于在晶元1012或再分布层1020处的水平面更加远离晶元1020。元件1040A可配置成包括经过刻蚀、模塑或其他方式形成的区域，以限定腔1070，该腔1070从远离晶元1012的元件1040A的表面1042延伸至定位成比表面1042更接近晶元1012的凹入表面1044。键合元件24-1可在沿着凹入表面1044的区域内的腔1070中不被覆盖。腔1070可具有任何适合的形状，以允许设置在腔1070中的键合元件24-1的端部30-1处的未封装部分52被电连接。在一个实施例中，键合元件24-1的未封装部分52可覆盖表面1044，且在封装元件1040A的锥形侧壁1045之间，封装元件1040A从表面1042延伸至限定腔1070的表面1044。
另外，封装元件1040B可封装键合元件1124，该键合元件1124配置成类似于图4C所示的键合元件124，且在其基1128处与再分布层1020的表面1017或晶元1012的表面1014处的焊盘连接。在图16A所示的示例性实施例中，键合元件1124可不被封装元件1040B覆盖，以形成由端面1134和封装元件1040B的腔1070内的键合元件的边缘表面1132的部分限定的未封装部分1152。在一个实施例中，接线柱1124的基1128可通过凸点1165与表面1017或1014处的焊盘联接。进一步，具有类似于图4C所示的腔175的配置的腔1075可形成在封装元件1040B中，且从表面1042延伸至表面1017，或当层1020被省略时延伸至表面1014。类似于键合元件124-2、124-3或124-4的键合元件1124A，可从设置在腔1175内的端面1130A延伸穿过腔1175至键合元件1124A的基，键合元件1124A的基与晶元1012的焊盘或层1020联接，其中键合元件1124A的未封装部分1152A由端面1130A和从端面1130A延伸的边缘表面1132A限定。
参见图16B，键合元件1124可提供至另一个导电元件的连接，例如通过焊锡元件1170等，通过允许填充腔1070或腔1175的未被线键合1124占据的部分，以分别封装键合元件24-1和1124的未封装部分52和1152。在一些实施例中，形成焊锡元件1170的材料可形成在从腔1070和1175延伸的表面1042的部分上。在另一个实施例中，焊锡元件1170的远离晶元1012的表面1172可在与封装元件1040的平坦表面1042相同的平面内。
在另一个实施例中，除了下列不同点，结构1010-2(参见图16C)可具有类似于结构1010-1的部件和配置。键合元件24-1可由封装元件1040A封装，以使仅仅是元件24-1的端面34-1限定其未封装部分52，且端面34-1与表面1044齐平。另外，具有未封装部分1152的键合元件1124可被封装元件1040B封装，以使仅仅是元件1124的端面1134限定未封装部分1152，且端面1134与表面1044齐平。进一步地，键合元件1124A可被封装元件1040B封装，以使仅仅是其端面1134A限定未封装部分1152A，且端面1134A与表面1044齐平。参见图16D，以及参见图16C所述类似的，焊锡元件1170可填充腔1070或腔1175未被键合元件1124占据的部分，以分别封装键合元件24-1和1124的未封装部分52和1152。
在一些实施例中，覆盖衬底112的封装元件，例如在上述结构10中(参见图3和图4A至图4D)，可用于封装键合元件和不覆盖未封装部分52，这类似于覆盖图16A至图16D所示的结构1010的实施例中的晶元1012的封装元件。
参见图15和图7E，类似于上述结构10，封装元件1040A和1040B可限定具有预定尺寸和形状的微电子元件容纳区域1210，以容纳微电子元件(例如单独的半导体芯片，或包括至少一个芯片的微电子组件或微电子封装)，被容纳的微电子元件从元件1040A和1040B横向设置且电连接至由区域1210的底部部分1212覆盖的表面1014的部分处的晶元1012。例如，参见图7E,封装元件1040A和1040B可以为具有类似于元件450的配置的单个集成封装元件1040的形式，覆盖晶元1012完全包围表面1014或1017的面积1014A或1017A的面积，以限定区域1210。区域1201可具有类似于区域452的配置，且包括类似于底部部分456的邻近晶元1012的部分1212。区域1210具有基于晶元1012的表面1014上的封装元件1040的尺寸、形状和定位的预定的尺寸和形状，且假设微电子元件的一部分可设置在不带接触表面1042A和1042B的元件、封装或组件的区域1210内，该部分是其自身的，或封装或组件之内的待连接至由部分1212覆盖的衬底的一部分的微电子元件的一部分。
参见图8，封装组件600可包括本发明的结构，该结构联接至结构的微电子区域处的微电子元件、封装或组件。例如，封装组件600可包括联接至微电子元件602的上述结构10。微电子元件或芯片602可包括相对的表面605、607，且相对于衬底12“面朝下”定向定位在区域212内，且表面605面对衬底12的表面14。表面605处的触点604可通过焊锡元件609键合至表面14处的导电元件618。区域210的底部部分212覆盖导电元件618。触点604可通过电路系统、衬底12内的这种迹线19或延伸穿过衬底12的导电通孔22与端子31及元件40A和40B内的键合元件24电连接，，其中迹线33从端子31在衬底12的表面16上延伸。通过将形成在端子31上的焊锡元件625(例如焊锡球)电连接至部件690的面对表面692上的触点(未示出)，组件600可联接至外部部件690(例如印刷电路板)，其中触点布置成对应于结构10的端子31的图案。
在一个实施例中，区域210可被适配，以使当微电子元件602键合至衬底12时，面对边缘表面44A和44B的微电子元件602的相对边缘表面613A和613B分别以离边缘表面44A和44B至少大约200μm的距离隔开。在一些实施例中，间隔的距离允许介电材料(例如填充层)可设置在相互面对的表面613A和44A之间，以及相互面对的表面613B和44B之间。在另一个实施例中，间隔的距离可允许微电子元件602的顶表面607之上的介电材料的模塑，微电子元件602在表面613A和613B之间延伸，以及在表面44A和44B之间延伸。
介电块或包胶模626形成在区域210的底部部分212之上，例如利用任何所述的技术形成上述衬底12之上的封装元件的介电块。介电块626具有远离表面14的顶表面628，该顶表面628在微电子元件602之上且背离表面14上的元件602在水平方向H1和H2上分别向封装元件40A和40B的边缘表面44A和44B延伸。在一个实施例中，顶表面628延伸至边缘表面44A和44B，且边缘表面628A和628B从顶表面628向下延伸至衬底12，且在一些实施例中分别沿着并接触边缘表面44A和44B的至少部分。同样地，介电块626可由第一介电材料制成，且封装元件40可由不同于第一介电材料的第二介电材料制成。在一些实施例中，可以提供介电块626，以使其顶表面628在封装元件40的表面42的部分之上延伸。介电块626进一步包括底表面630，该底表面630在背离封装元件40A和40B的水平方向H1和H2上从边缘表面628A和628B沿着表面14的暴露部分和表面14上的迹线618延伸。
在一个实施例中，在正交于H1和H2的组件600的厚度方向T上的封装元件40的厚度(h)背离表面14向上延伸，且等同于、大于或小于在方向T上的微电子元件602的厚度。在另一个实施例中，至少一个元件40的厚度(h)小于或等于其内封装有微电子元件602的介电块626在方向T上的厚度。
组件600可与覆盖衬底12的表面14的微电子封装2200联接。封装2200可包括具有远离第二表面2210的第一表面2208的衬底2206，其中第一表面2208面对封装元件40的表面42和介电块626的表面628。导电元件2212可沿着表面2208和2210延伸。另外，微电子元件2214以“面朝下”定向的方式定位成面对表面2210，且微电子元件2214的触点(未示出)通过焊锡元件(未示出)键合至表面2210上的导电元件2212。进一步，表面2208上的导电元件2212可布置成对应于键合元件24的未封装部分52的图案的图案，且焊锡元件2215可将这种元件2212与未封装部分52电连接。介电块2220可形成在微电子元件2214和表面2210的未覆盖部分上，以封装元件2202和衬底2206的表面2210，例如通过上述任意技术形成介电块。远离衬底2206的介电块2220的表面2222覆盖微电子元件2214和表面2210邻近元件2214的部分。同样地，键合元件24可将封装2200的导电元件与组件600的导电元件和外部部件690的导电元件电互连。
在另一个实施例中，参见图9，封装组件600’可具有如图8所示的组件600的类似构造，除了键合元件24的端面34与表面42齐平，芯片602通过引线622联接至衬底上的迹线618，且组件600’进一步包括再分布层654。例如，芯片602的表面607可通过粘合剂层611与由部分212覆盖的层14的部分附接，且引线622可在芯片602的表面607和边缘表面613上从触点604延伸至迹线618。进一步地，层654可由介电材料形成，且沿着至少一个封装元件40的表面42的一部分或介电块626的表面628的一部分延伸。在一个实施例中，再分布层654可仅覆盖结构10的部分50。在一个可选实施例中，部分212可覆盖再分布层654的部分。迹线658可电连接至内触点焊盘661，内触点焊盘661电连接至键合元件24的端面34，迹线658穿过再分布层654的衬底656延伸至衬底656的表面662处的触点焊盘660。然后，另一个微电子组件可通过焊锡块等联接至触点焊盘660。再分布层654事实上用作扇出层(fan-out layer)，扇出层可允许组件600’连接至不同配置的阵列而不是在区域50内的以其他方式允许的导电元件26阵列。
在进一步实施例中，组件600’可联接至微电子封装，例如上述的封装2200(参见图8)，该封装覆盖再分布层654。封装2200的表面2208可面对层654的表面662，且在表面2208处的封装2200的导电元件2212可布置成对应于层654的表面662处的触点焊盘660的图案的图案。焊锡元件2215可将这种元件2212与触点焊盘660电连接。同样地，封装2200的导电元件可通过再分布层的导电元件以及键合元件24与组件600’的导电元件和外部部件690的导电元件电连接。
应当理解的是，根据本发明，微电子元件或微电子封装可“面朝上”或“面朝下”安装，且通过线键合、球形键合或其他已知的连接技术联结至表面，例如，根据本发明的结构的衬底的表面(例如14，16)或与包括这种结构的封装组件联接的外部部件的表面(例如692)。
在另一个实施例中，参见图10A，封装组件700可包括根据本发明的与多个微电子元件联接的结构，其中一些微电子元件可为微电子封装的部分。参见图10A，组件700可包括上述的结构10，以及微电子元件702，该微电子元件702的触点703面对表面16且电连接至表面16处的导电元件20的焊盘25。介电块704形成在微电子元件702和表面16之上，且具有覆盖元件702和表面16的表面706。介电块704覆盖微电子元件702和表面16，类似于上述图8所示的介电块626形成在元件602和表面14之上。
另外，封装组件700可包括联接至表面14处的导电元件的微电子元件732。类似于微电子元件602，微电子元件732可相对于衬底12的表面14以“面朝下”定向定位在区域710内，表面735面对衬底12的表面14。表面735处的触点736可通过焊锡元件键合至表面14处的导电元件738。区域710的底部部分712覆盖导电元件738。触点736可电连接至通过衬底12内的电互连电连接至触点736的其他导电部件或元件，且键合元件24封装在元件40A和40B之内。
另外，介电材料748块可形成在区域710的部分712之上，类似于上述的包胶模628。介电块748具有远离表面14的表面750，表面750在微电子元件732之上背离表面14上的微电子元件732在水平方向H1和H2上分别向封装元件40A和40B的边缘表面44A和44B延伸。在一个实施例中，表面750可与边缘表面44A和44B间隔开，且介电块748包括从其向下延伸至衬底12的边缘表面752A和752B，边缘表面752A和752B分别面对边缘表面44A和44B且分别与边缘表面44A和44B间隔开。在另一个实施例中，边缘表面752中的一个(例如边缘表面752A)可至少部分地接触边缘表面44A的部分。介电块748可由第一介电材料制成，且封装元件40可由不同于第一介电材料的第二介电材料制成。介电块748进一步包括底部部分754，底部部分754在水平方向H1和H2上沿着表面14的暴露部分和表面14处的迹线738延伸，且与元件40A和40B隔开。
参考图11，图11为在表面14的方向上所看到的组件700的实施例的平面图，介电块748具有封装在其内的微电子元件732以形成封装微电子单元755，且在水平方向H1上延伸小于R1的预定长度L1以及在正交于水平方向H1和H2且平行于表面14的方向上延伸小于R2的预定长度W1。另外，参见图10A，介电块748具有在方向T上不超过预定厚度H2的厚度，该厚度是在厚度方向T上从表面14至外部部件790的面对表面792的距离，键合元件24在端面34处通过焊锡元件794电互连至该外部部件790，该距离小于焊锡元件794的预期厚度。例如，在表面754处介电块748在具有最大尺寸W1和L1的水平面积上延伸，具有在厚度方向T上预定形状且具有从表面14延伸至表面750的最多等于H3的厚度，以使元件40的表面42处的端面34可在组件700的厚度方向上与外部部件790的表面792上的焊盘(未示出)对齐，且介电块750在区域710内但不接触区域710内的元件40、部件790或其他部件。
在一些实施例中，包括图10A所示的微电子单元755的组件700也可连接至布置在区域710内的微电子封装800，且连接至部分712覆盖的导电元件18的端子27。封装800可包括具有远离第二表面810的第一表面808的衬底806，其中第一表面808面对表面14，且导电元件812沿着表面808和810延伸。另外，微电子元件814以“面朝下”定向方式面对表面810定位，微电子元件814的触点(未示出)通过焊锡元件(未示出)键合至表面810的导电元件812。进一步，表面808的导电元件812通过焊锡元件815电连接至表面14处的端子27。介电块820形成在微电子元件814和衬底806的表面810的部分之上，且相对边缘819在表面808和810之间延伸以封装元件802和衬底806的部分，例如利用所述的任何技术以形成介电块。远离衬底806的介电块820的表面822覆盖微电子元件814和表面810邻近元件814的部分。
进一步参见图11，封装800具有预定的尺寸和配置，且布置在与微电子单元755在方向H1上间隔开的表面14上的预定位置，且在方向H2上与元件40B间隔开，以不接触元件40和单元755。类似于单元755，封装800可定位在表面14之上，且表面808处的焊盘(未示出)在厚度方向T上与表面14处的相应的端子27对齐，以使部分712覆盖封装800。封装800在水平方向H1上延伸小于R1的预定长度L2以及在正交于水平方向H1和H2且平行于表面14的方向上延伸小于R2的预定长度W2。
进一步，在一些实施例中，微电子封装800’可布置在区域710之内且在区域710内与其他部件间隔开。例如，参见图10和图11，可具有与封装800相同或类似配置及部件的封装800’可布置在元件40B和封装800之间，且与元件40B和封装800间隔开，且在水平方向H1上延伸小于R1的预定长度L3以及在正交于水平方向H1和H2且平行于表面14的方向上延伸小于R2的预定长度W3。封装800’可具有面对外部部件790的表面792的表面808，以及连接至表面792上相应的焊盘(未示出)的表面808上的端子812。类似于封装800，封装800’具有在组件700的厚度方向上不大于H2的厚度。
同样地，区域710内的任何微电子元件，例如封装微电子单元的部分，连接至部分712覆盖的表面14处的导电元件的微电子封装，或连接至外部部件的焊盘的微电子封装，这些都具有组件700的厚度方向T上的高度，该高度允许键合元件24的端面的阵列与外部部件790的相应的导电元件连接。在一个实施例中，微电子元件702可为逻辑的，且布置在区域712内的微电子元件可为存储器。
在一些实施例中，微电子元件和区域710内的封装可在具有小于R1和R2的尺寸的水平面积上延伸，具有在厚度方向T上的预定形状，且具有从表面14延伸至表面792的最多等于H2的厚度，以使键合元件24的端面和封装800’的端子可在组件700的厚度方向上与外部部件790的表面792上的焊盘(未示出)对齐，且封装800和800’以及微电子元件752在区域712内但不相互接触且不接触封装元件40。焊锡元件794可将键合元件24与部件790的相应触点电互连，且将封装800’导电元件与部件790的相应触点电互连。
在另一个实施例中，封装800’具有在方向T上的厚度，以使表面822邻近表面14，且在一些实施例中，至少部分地接触表面14或通过粘合剂附接至表面14。
在进一步的实施例中，参见图10B，除了微电子封装(例如上述图8所示的封装2200)覆盖结构10的表面16而不是微电子元件702和介电块704，封装组件700’可具有类似于封装组件700(参见图10A)的构造。封装2200的表面2208可面对衬底12的表面16，且在表面2208处的封装2200的导电元件2212可布置成对应于表面16处的导电元件20的图案的图案。焊锡元件2215可将这种元件2212与导电元件20电连接。同样地，封装2200的导电元件可通过在衬底12之内或其表面处的导电元件电连接至封装800和800’的导电元件，单元755以及外部部件790。
在另一个实施例中，参见图12，封装组件850可包括类似于结构400(参见图5)的结构400’,该结构400’具有覆盖衬底412的表面414的部分450的封装子元件440A、440B和440C。元件40A、440B和440C限定分别具有顶部部分406A和406B的多个微电子容纳区域402A和402B。微电子元件702被衬底412的表面416上的介电块704封装，其中类似于在组件700内，表面416与限定微电子元件容纳区域的表面414相对。微电子封装800布置在区域402A中，类似于图10A的组件700的描述，该微电子封装800连接至部分406A覆盖的表面404处的导电元件，以不接触元件440A和440C。另外，封装微电子单元755布置在区域402B内，类似于图10A的组件700的描述，该封装微电子单元755连接至部分406B覆盖的表面404的导电元件，以不接触元件440A和440C。封装800和单元755具有预定形状，该预定形状具有在组件800的厚度方向上的高度，以类似于关于图10A所描述的，键合元424的端面可与面对元件440的表面442的外部部件的表面上的相应的焊盘电连接。
在另一个实施例中，参见图17和图18，封装组件1600可包括本发明的结构1010(参见图15)，该结构连接至其微电子元件区域1210处微电子元件、封装或组件。在一个实施例中，封装组件1600可包括连接至微电子元件1602的结构1010，例如DRAM，该结构具有相对的表面1605和1607，且相对于区域121内的晶元1012“面朝下”定向定位，表面1605面对晶元1012的表面1014。在表面1605处的触点1604可通过焊锡元件1609键合至再分布层1020的表面1017处的迹线1024’，或晶元1012的表面1014处的焊盘1018’，其中层1020从结构1010中省略。区域1210的底部部分1212覆盖迹线1024’和焊盘1018’。触点1604可通过晶元1012的迹线1024’、焊盘1018’和1018，以及晶元1012内的电路系统(未示出)与元件1040内的键合元件24电连接。
具有类似于模具626(参见图8)的配置的介电块或包胶模1626可形成在区域1210的底部部分1212之上。介电块1626具有远离表面1014的表面1628，该表面1628在微电子元件1602之上且背离表面1014上的元件1602在水平方向H1和H2上分别向封装元件1040A和1040B的边缘表面1044A和1044B延伸。在一个实施例中，表面1628延伸至边缘表面1044A和1044B，且边缘表面1628A和1628B从其向下延伸至层1020或晶元12，且在一些实施例中分别沿着并接触边缘表面1044A和1044B的至少部分。介电块1626可由第一介电材料制成，且封装元件1040可由不同于介电块1626的介电材料的第二介电材料制成。介电块1626进一步包括底表面1630，该底表面1630在背离封装元件1040A和1040B的水平方向H1和H2上从边缘表面1628A和1628B延伸，且分别沿着表面1017或1014的暴露部分和该表面上的迹线1024’或焊盘1018’延伸。
参见图18，组件1600可相对于外部部件(例如图10A所示的部件790)以“面朝下”或“倒装组件”定向的方式定位，键合元件24的未封装部分52面对表面790且通过焊锡元件794电连接至表面792上的触点(未示出)，这些触点布置成对应于组件1600内结构1010的未封装部分52的图案。介电块1726可形成在微电子元件1602之上，且从表面1728延伸至远离介电块1626的相对表面1730，表面1728沿着封装元件1040的表面1628和表面1042延伸。表面1730可在方向H1和H2上沿着表面1728延伸，以在方向H1和H2上分别与边缘1046A和1046B对齐，或分别延伸超过边缘1046A和1046B。介电块1726的相对的边缘表面1735A和1735B可在垂直方向上或者关于表面792和1042成角度分别从表面792延伸至表面1046A和1046B。介电块1726的介电材料可填充部件790和每个介电块1626之间的空间以及部件790和封装元件1040之间的空间，以封装键合元件24的未封装部分、焊锡元件794，以及与组件1600相对的表面792上的导电元件。同样地，类似于组件700与图10A所示的部件790的连接，组件1600可电连接至部件790的导电元件，其中组件1600在厚度方向T上的高度允许键合元件24的端面的阵列与外部部件790的相应的导电元件连接。另外，外部部件可包括相对且远离表面792的表面794上的迹线(未示出)，焊锡元件796可联接至表面794，用于通过键合元件24和在衬底790上及衬底790内的导电元件，提供晶元1012和微电子元件1602与另一个外部部件(未示出)的电连接。
在一些实施例中，例如在组件1600(参见图18)中，介电块1626、介电块1726和封装元件1040可分别由不同的介电材料形成。在如图19所示的进一步的实施例中，类似于图18所述，组件1600可联接至外部部件，除了由同样的介电材料制成的具有上述介电块1626和介电块1726的配置的介电块1800封装微电子元件1602、键合元件的未封装部分52、以及在表面792处的导电元件。但是，介电块1800由不同于封装元件1040的介电材料制成。
在另一个实施例中，参见图20，封装组件1800可包括具有单个封装元件1840的结构1900，该封装元件1840覆盖配置内的晶元1012，类似于图7D所示的封装元件450覆盖衬底，以限定多个微电子容纳区域402。类似于图7D所示，元件1840包括限定多个微电子容纳区域402A和402B的部分1840A、1840B和1840C，这些微电子容纳区域402A和402B分别具有部分406A和406B，且覆盖层1020的部分1017A和1017B，部分1017A和1017B进而覆盖晶元1012的表面1014的部分1014A和1014B。类似于图10A所示的组件700，微电子封装800可布置在区域402A内，且连接至部分406A覆盖的表面1017A处的导电元件，且不接触限定区域402A的封装元件1840的相邻部分1840A和1840C。另外，还是类似于图10A所示，微电子封装800’可布置在区域402B内，与部分1840C和1840B间隔开且连接至表面792处的部件790。封装800和800’可具有预定形状，该预定形状具有在结构1900的厚度方向上的高度，以类似于关于图10A所描述的，键合元24的端面可与外部部件的表面上的相应焊盘电连接，该外部部件面对远离晶元1012的元件1840的表面1842处的键合元件24的未封装部分52。
在另一个实施例中，参见图21，封装组件2000可包括结构1900(参见图20)，该结构1900联接至布置在区域402A和402B内的微电子元件2102A和2102B，且分别覆盖其部分406A和406B。类似于图18所示的微电子元件1602，微电子元件2101A和2101B的焊盘通过焊锡元件1609分别与部分1017A和1017B的迹线联接。形成介电块2026A和2026B以覆盖微电子元件2101A和2101B，且介电块2026A和2026B具有类似于图18所示的介电块1626的配置，其中其各个相对边缘表面2028A和2028B面对以及在一些实施例中接触元件1840的面对边缘表面1844的至少部分。例如，相对的边缘表面2028A的部分可分别接触面对边缘表面1844A和1844C的部分，且相对边缘表面2028B的部分可分别接触面对边缘表面1844C和1844B的部分。介电块2026A和2026B可由同样的或不同的介电材料制成，且介电块2026的材料不同于封装元件1840的介电材料。
以上讨论的组件可用于构造不同的电子系统。例如，根据本发明的进一步实施例的系统900(图13)包括第一封装组件902(如组件850)和第二封装组件904(如组件2000)，以及其他电子部件908和910。在所描述的示例中，部件908是半导体芯片而部件910是显示屏，但也可使用任何其他部件。当然，尽管为了说明的清楚性，图13只描述了两种额外的部件，但系统可包括任何数目的此类组件。封装组件902和904以及部件908和910安装至共用壳体901(以虚线示意性示出)，且视需要彼此电互连以形成所需的电路。在所示的示例性系统中，系统包括电路板907，例如柔性或刚性印刷电路板，且该电路板包括使部件互连的很多导体909(图13仅示出其中一个)。离板连接器将部件910连接至电路板。但是，这仅仅是示例性的，可使用适用于进行电连接的任何适当的结构。壳体901被描述为可用于例如移动电话或个人数字助理类型的便携式壳体，且屏幕910暴露在该壳体的表面处。同样，图13所示的简化系统仅仅是示例性的，可使用以上所述的封装制作其他系统，包括通常被视为固定结构的系统，如台式电脑、路由器等。
在不背离本发明的情况下，可以利用以上讨论的特征及特征的其他变型和组合，先前关于优选实施例的描述应当理解为对本发明的解释而不是对本发明的限定，本发明由权利要求限定。

Claims (74)

1.一种结构，包括：
衬底，所述衬底具有相对的第一表面和第二表面，以及在所述第一表面处的多个导电元件；
键合元件，所述键合元件具有联接至所述第一表面的第一部分处的各个所述导电元件的基，以及远离所述衬底和所述基的端面，每个所述键合元件从其所述基延伸至其所述端面；以及
介质封装元件，所述介质封装元件覆盖所述衬底的所述第一表面的所述第一部分且从所述衬底的所述第一表面的所述第一部分延伸，且填充所述键合元件之间的空间，以使所述键合元件通过所述封装元件相互分离，所述封装元件具有背离所述衬底的所述第一表面的第三表面且具有从所述第三表面向所述第一表面延伸的边缘表面，其中所述键合元件的未封装部分由在所述第三表面处未被所述封装元件覆盖的所述键合元件的所述端面的至少部分限定；
其中所述封装元件至少部分限定所述第一表面的第二部分，所述第二部分不同于所述第一表面的所述第一部分且具有容纳微电子元件的整个面积的面积，而且所述第一表面处的至少一些所述导电元件位于所述第二部分且用于与这种微电子元件相连接。
2.根据权利要求1所述的结构，其中所述键合元件包括线键合、微柱或导线中的至少一个。
3.根据权利要求1所述的结构，进一步包括在至少一个所述键合元件的所述基或所述端面中的至少一个处的焊锡。
4.根据权利要求3所述的结构，其中在所述至少一个键合元件的所述端面处的所述焊锡在所述第三表面处。
5.根据权利要求3所述的结构，其中所述焊锡从所述至少一个键合元件的所述端面穿过所述封装元件的部分向所述第三表面延伸。
6.根据权利要求1所述的结构，其中至少一个所述键合元件的邻近其端面的至少一部分垂直于所述第三表面。
7.根据权利要求1所述的结构，其中至少一个所述键合元件包括联接至其端面的凸点。
8.根据权利要求1所述的结构，其中至少一个所述键合元件在所述基和其所述未封装部分之间沿着大体为笔直的线延伸，且其中所述大体为笔直的线关于所述衬底的所述第一表面形成小于90°的角度。
9.根据权利要求1所述的结构，其中至少一个所述键合元件包括在所述基和其所述端面之间的大体为弯曲的部分。
10.根据权利要求1所述的结构，其中所述第三表面包括离所述衬底的所述第一表面第一距离处的第一表面部分，以及离所述衬底的所述第一表面第二距离处的第二表面部分，所述第二距离小于所述第一距离，且其中至少一个所述键合元件的所述未封装部分在所述第二表面部分处未被所述封装元件覆盖。
11.根据权利要求1所述的结构，其中所述封装元件包括形成在其内的腔，所述腔从所述第三表面向所述衬底延伸，且其中所述键合元件中的一个的未封装部分设置在所述腔内。
12.根据权利要求1所述的结构，其中至少一个所述键合元件包括铜、金、铝或焊锡中的至少一种。
13.根据权利要求1所述的结构，其中所述键合元件分别联接至的所述一些导电元件布置成第一预定配置的第一阵列，以及其中所述一些导电元件联接至的所述键合元件的所述未封装部分布置成第二预定配置的第二阵列，所述第二预定配置不同于所述第一预定配置。
14.根据权利要求13所述的结构，其中所述第一预定配置以第一节距为特征，且其中所述第二预定配置以小于所述第一节距的第二节距为特征。
15.根据权利要求1所述的结构，其中所述键合元件的所述端面用于连接至第一部件。
16.根据权利要求1所述的结构，其中所述衬底的所述第一表面的所述第二部分包括第一子部分和第二子部分，所述第一子部分和第二子部分具有分别容纳第一微电子元件和第二微电子元件的整个面积的尺寸，而且在所述第一表面处的至少一些所述导电元件位于所述第二部分的所述第一子部分和第二子部分，且用于允许分别与所述第一微电子元件和第二微电子元件连接。
17.根据权利要求16所述的结构，其中所述封装元件包括相互间隔布置的多个封装子元件，其中所述第一子部分或第二子部分中的至少一个的面积至少部分地由所述多个封装子元件的第一封装子元件和第二封装子元件限定。
18.根据权利要求1所述的结构，进一步包括：
多个第二导电元件，所述多个第二导电元件在所述衬底的所述第二表面处；
第二键合元件，所述第二键合元件具有联接至所述第二表面的第一部分处的各个所述第二导电元件的基，以及远离所述衬底和所述第二键合元件的所述基的端面，每个所述第二键合元件从其所述基延伸至其所述端面；以及
第二介质封装元件，所述第二介质封装元件覆盖所述第二表面的所述第一部分且从所述第二表面的所述第一部分延伸，且填充所述第二键合元件之间的空间，以使所述第二键合元件通过所述第二封装元件相互分离，所述第二封装元件具有背离所述第二表面的第四表面以及从所述第四表面向所述衬底的第二表面延伸的边缘表面，其中所述第二键合元件的未封装部分由在所述第四表面处未被所述第二封装元件覆盖的所述第二键合元件的所述端面的至少部分限定。
19.根据权利要求18所述的结构，其中所述第二封装元件至少部分地限定所述第二表面的第二部分，所述第二表面的所述第二部分不同于所述第二表面的所述第一部分且具有容纳另一个微电子元件的整个面积的面积，而且所述第二表面处的至少一些所述第二导电元件位于所述第二表面的所述第二部分且用于连接所述另一个微电子元件。
20.根据权利要求1所述的结构，进一步包括：
多个第一端子，所述多个第一端子在所述第二表面处且用于连接至第一部件，至少一些所述第一端子与所述导电元件电连接。
21.一种封装组件，包括权利要求1所述的结构且进一步包括：
第一微电子元件，所述第一微电子元件设置在所述第二部分之上且电连接至所述一些导电元件中的至少一个；以及
介电块，所述介电块覆盖所述第一微电子元件以及所述第二部分的至少部分，所述介电块限定远离且背离所述第一表面的第四表面，所述第四表面的至少部分在所述微电子元件和所述第二部分之上延伸，所述介电块限定面对所述边缘表面的至少部分的第二边缘表面，
其中所述介电块不同于所述封装元件。
22.根据权利要求21所述的封装组件，其中所述边缘表面的至少部分接触所述第二边缘表面的至少部分。
23.根据权利要求22所述的封装组件，其中所述边缘表面或所述第二边缘表面中的至少一个的至少部分是平坦的。
24.根据权利要求21所述的封装组件，其中所述介电块从所述衬底的所述第二表面的厚度小于所述封装元件从所述衬底的所述第二表面的厚度。
25.根据权利要求21所述的封装组件，其中所述第一微电子元件具有相对的第五表面和第六表面，所述第五表面面对所述第一表面，且其中所述第一微电子元件与所述第五表面和第六表面中的至少一个处的所述一些第一导电元件中的至少一个电连接。
26.根据权利要求25所述的封装组件，其中从所述第六表面延伸的键合线将所述第一微电子元件与所述一些导电元件中的至少一个电连接。
27.根据权利要求25所述的封装组件，其中所述第一微电子元件的所述第五表面处的触点与所述一些第一导电元件中的至少一个电连接。
28.根据权利要求21所述的封装组件，进一步包括：
再分布层，所述再分布层沿着所述第三表面或第四表面中的至少一个的至少一部分延伸，其中所述再分布层包括再分布衬底、第一导电焊盘以及第二导电焊盘，所述再分布衬底具有邻近所述第三表面或第四表面中的至少一个的第五表面以及远离第五表面的第六表面，所述第一导电焊盘在所述再分布衬底的第五表面处且与所述键合元件的各个未封装部分对齐且机械连接，所述第二导电焊盘在所述再分布衬底的第六表面处且电连接至所述第一导电焊盘。
29.一种封装组件，包括权利要求1所述的结构且进一步包括：
第一微电子元件，所述第一微电子元件设置在所述衬底的所述第二表面之上且通过在所述第二表面处的多个第二导电元件中的至少一个与所述导电元件中的至少一个电连接；以及
介电块，所述介电块覆盖所述第一微电子元件以及所述第二表面远离所述第一微电子元件延伸的至少部分，所述介电块限定远离且背离所述第二表面的第四表面。
30.根据权利要求29所述的封装组件，其中所述第一微电子元件具有相对的第五表面和第六表面，所述第五表面面对所述第二表面，且其中所述第一微电子元件在所述第五表面和第六表面中的至少一个处与所述第二导电元件中的至少一个电连接。
31.根据权利要求30所述的封装组件，其中从所述第六表面延伸的键合线将所述第一微电子元件与所述第二导电元件中的至少一个电连接。
32.根据权利要求30所述的封装组件，其中所述第一微电子元件的所述第五表面处的触点与所述第二导电元件中的至少一个电连接。
33.根据权利要求29所述的封装组件，进一步包括：
至少一个第二微电子元件，所述至少一个第二微电子元件布置在所述第二部分之上且与所述导电元件中的至少一个电连接。
34.根据权利要求33所述的封装组件，其中所述第二微电子元件具有相对的第七表面和第八表面，所述第七表面面对所述第一表面，且其中所述第二微电子元件在所述第七表面和第八表面中的至少一个处与所述至少一些导电元件电连接。
35.根据权利要求34所述的封装组件，其中从所述第八表面延伸的键合线将所述第二微电子元件与所述至少一些第一导电元件中的一个电连接。
36.根据权利要求34所述的封装组件，其中所述第二微电子元件的所述第七表面处的触点与所述至少一些导电元件中的一个电连接。
37.根据权利要求33所述的封装组件，其中所述第二微电子元件是微电子封装的部分，
其中所述微电子封装包括具有相对的第七表面和第八表面的第二衬底，所述第二微电子元件设置在所述第八表面之上，导电元件在所述第二衬底上且包括在第七表面处的端子，所述第二微电子元件与所述第二衬底上的所述导电元件中的至少一个电连接，
其中所述第七表面面对所述第一表面，且所述微电子封装的所述端子通过各个焊锡元件与所述结构的所述导电元件电连接。
38.根据权利要求33所述的封装组件，其中所述第二微电子元件是微电子封装的包括在其表面上的端子的一部分，
其中所述第二微电子元件通过外部部件的导电元件与所述一些导电元件中的至少一个电连接，所述微电子封装的所述端子和至少一个所述键合元件电连接至所述外部部件。
39.根据权利要求33所述的封装组件，其中所述至少一个第二微电子元件包括多个所述第二微电子元件，且至少一个所述第二微电子元件是微电子封装的与所述结构的所述导电元件的至少一些电连接的部分。
40.根据权利要求39所述的封装组件，其中所述第二微电子元件中的一个是具有在其表面处通过各个焊锡元件与所述结构的所述一些导电元件电连接的端子的微电子封装的部分，而且所述第二微电子元件中的另一个是具有在其表面处通过外部部件的导电元件与一些所述导电元件电连接的端子的微电子封装的部分，所述第二微电子元件中的所述另一个的端子和至少一个所述键合元件电连接至所述外部部件。
41.根据权利要求39所述的封装组件，其中所述衬底的所述第一表面的所述第二部分包括第一子部分和第二子部分，所述第一子部分和第二子部分分别具有容纳所述第二微电子元件中的第一个和包括所述第二微电子元件中的另一个的所述微电子封装的整个面积，而且在所述第一表面处的至少一些所述导电元件位于所述第二部分的所述第一子部分和第二子部分且用于允许分别与所述第二微电子元件中的所述第一个和所述微电子封装连接。
42.根据权利要求1所述的结构，其中所述封装元件从所述衬底的所述第一表面的所述第一部分向所述第三表面延伸至少150μm的长度。
43.根据权利要求1所述的结构，被封装元件覆盖的所述衬底的所述第一表面的所述第一部分完全包围所述衬底的所述第一表面的所述第二部分。
44.一种结构的制作方法，包括：
在衬底上形成介质封装元件，所述衬底具有相对的第一表面和第二表面，以及在所述第一表面处的多个导电元件，且其中键合元件在其基处联接至所述第一表面的第一部分处的各个所述导电元件，以及所述键合元件的端面远离所述衬底和所述基，每个所述键合元件从其所述基延伸至其所述端面，
其中形成所述介质封装元件，以覆盖所述衬底的所述第一表面的所述第一部分且从所述衬底的所述第一表面的所述第一部分延伸，且填充所述键合元件之间的空间，以使所述键合元件通过所述封装元件相互分离，所述封装元件具有背离所述衬底的所述第一表面的第三表面且具有从所述第三表面向所述第一表面延伸的边缘表面，其中所述键合元件的未封装部分由在所述第三表面处未被所述封装元件覆盖的所述键合元件的所述端面的至少部分限定；以及
其中所述封装元件至少部分限定所述第一表面的第二部分，所述第二部分不同于所述第一表面的所述第一部分且具有容纳微电子元件的整个面积的面积，而且所述第一表面处的至少一些所述导电元件位于所述第二部分且用于与这种微电子元件相连接。
45.根据权利要求44所述的方法，其中所述键合元件包括线键合、微柱或导线中的至少一个。
46.根据权利要求44所述的方法，其中所述键合元件包括，在所述衬底上形成所述封装元件之前，在其所述基处焊接至一个所述导电元件的至少一根导线。
47.根据权利要求44所述的方法，进一步包括：
在形成所述封装元件之后，形成覆盖第一微电子元件和所述第二部分的至少部分的介电块，所述第一微电子元件设置在所述第二部分之上且与至少一些所述导电元件电连接，所述介电块限定远离且背离所述第一表面的第四表面，所述第四表面的至少部分在所述微电子元件和所述第二部分之上延伸，所述介电块限定面对所述边缘表面的至少部分的第二边缘表面，
其中所述介电块不同于所述封装元件。
48.根据权利要求47所述的方法，其中所述边缘表面的至少部分接触所述第二边缘表面的至少部分。
49.根据权利要求44所述的方法，进一步包括：
形成介电块，以覆盖第一微电子元件及远离所述第一微电子元件而延伸的所述第二表面的至少部分，所述第一微电子元件设置在所述衬底的所述第二表面之上且通过所述第二表面处的多个第二导电元件中的至少一个与至少一个所述导电元件电连接。
50.根据权利要求49所述的方法，进一步包括：
将至少一个第二微电子元件与所述衬底的所述第一表面的所述第二部分处的一些所述导电元件电连接。
51.根据权利要求50所述的方法，其中所述至少一个第二微电子元件包括多个所述第二微电子元件，且至少一个所述第二微电子元件是与至少一些所述第一导电元件电连接的微电子封装的一部分。
52.根据权利要求50所述的方法，其中所述第二微电子元件中的一个是具有在其表面处通过各个焊锡元件电连接至所述结构的所述一些导电元件的端子的微电子封装的部分，而且所述第二微电子元件中的另一个是具有在其表面处通过外部部件的导电元件与在所述第一表面处的一些所述导电元件电连接的端子的微电子封装的一部分，所述第二微电子元件中的所述另一个的端子和至少一个所述键合元件电连接至所述外部部件。
53.一种结构，包括：
有源晶元，所述有源晶元具有相对的第一表面和第二表面，以及在所述第一表面处的多个导电元件，
键合元件，所述键合元件具有联接至所述第一表面的第一部分处的各个所述导电元件的基，以及远离所述晶元和所述基的端面，每个所述键合元件从其所述基延伸至其所述端面；以及
介质封装元件，所述介质封装元件覆盖所述晶元的所述第一表面的所述第一部分且从所述晶元的所述第一表面的所述第一部分延伸，且填充所述键合元件之间的空间，以使所述键合元件通过所述封装元件相互分离，所述封装元件具有背离所述晶元的所述第一表面的第三表面且具有从所述第三表面向所述第一表面延伸的边缘表面，其中所述键合元件的未封装部分由在所述第三表面处未被所述封装元件覆盖的所述键合元件的所述端面的至少部分限定；
其中所述封装元件至少部分限定所述第一表面的第二部分，所述第二部分不同于所述第一表面的所述第一部分且具有容纳微电子元件的整个面积的面积，而且所述第一表面处的至少一些所述导电元件位于所述第二部分且用于与这种微电子元件相连接。
54.根据权利要求53所述的结构，其中所述晶元是现场可编程门阵列。
55.根据权利要求53所述的结构，其中所述第三表面包括离所述晶元的所述第一表面第一距离处的第一表面部分，以及离所述晶元的所述第一表面第二距离处的第二表面部分，所述第二距离小于所述第一距离，且其中至少一个所述键合元件的所述未封装部分在所述第二表面部分处未被所述封装元件覆盖。
56.根据权利要求53所述的结构，其中所述封装元件包括形成在其内的腔，所述腔从所述第三表面向所述晶元延伸，且其中所述键合元件中的一个的未封装部分设置在所述腔内。
57.一种封装组件，包括权利要求53所述的结构且进一步包括：
第一微电子元件，所述第一微电子元件设置在所述第二部分之上且电连接至所述一些导电元件中的至少一个；以及
介电块，所述介电块覆盖所述第一微电子元件以及所述第二部分的至少部分，所述介电块限定远离且背离所述第一表面的第四表面，所述第四表面的至少部分在所述微电子元件和所述第二部分之上延伸，所述介电块限定面对所述边缘表面的至少部分的第二边缘表面，
其中所述介电块不同于所述封装元件。
58.根据权利要求57所述的封装组件，其中所述边缘表面的至少部分接触所述第二边缘表面的至少部分。
59.根据权利要求58所述的封装组件，其中所述边缘表面或所述第二边缘表面中的至少一个的至少部分是平坦的。
60.根据权利要求57所述的封装组件，其中所述介电块封装所述键合元件的所述未封装部分，且覆盖所述封装元件的所述第三表面。
61.根据权利要求57所述的封装组件，进一步包括：
第二介电块，所述第二介电块覆盖所述介电块的所述第四表面和所述封装元件的所述第三表面，且封装所述键合元件的所述未封装部分，
其中所述第二介电块不同于所述封装元件，也不同于所述介电块。
62.根据权利要求57所述的封装组件，其中所述晶元的所述第一表面的所述第二部分包括第一子部分和第二子部分，所述第一子部分和第二子部分具有分别容纳第一微电子元件和第二微电子元件的整个面积的面积，而且在所述第一表面处的至少一些所述导电元件位于所述第二部分的所述第一子部分和第二子部分且用于允许分别与所述第一微电子元件和第二微电子元件连接。
63.一种封装组件，包括权利要求62所述的结构且进一步包括：
所述第一微电子元件和所述第二微电子元件，其中所述第一微电子元件和所述第二微电子元件分别设置在所述第一子部分和所述第二子部分之上，且电连接至所述一些导电元件的中的至少一个；
第一介电块，所述第一介电块覆盖所述第一微电子元件和所述第一子部分的至少部分，所述第一介电块限定远离且背离所述第一表面的第四表面，所述第四表面的至少部分在所述第二微电子元件和所述第一子部分之上延伸，所述第一介电块限定面对所述边缘表面的至少部分的第二边缘表面；
第二介电块，所述第二介电块覆盖所述第二微电子元件和所述第二子部分的至少部分，所述第二介电块限定远离且背离所述第一表面的第五表面，所述第五表面的至少部分在所述第二微电子元件和所述第二子部分之上延伸，所述第二介电块限定面对所述边缘表面的至少部分的第二边缘表面；
其中所述第一介电块和所述第二介电块都不同于所述封装元件。
64.根据权利要求63所述的封装组件，其中所述边缘表面的至少部分接触所述第一介电块或所述第二介电块中至少一个的所述第二边缘表面的至少部分。
65.一种封装组件，包括权利要求62所述的结构且进一步包括：所述第一微电子元件和所述第二微电子元件，
其中所述第一微电子元件是设置在所述第一子部分之上且与所述第二表面处的至少一个所述导电元件电连接的第一微电子封装；以及
其中所述第二微电子元件是设置在所述第二子部分之上且通过外部部件的导电元件与所述第二表面处的至少一个所述导电元件电连接的第二微电子封装，所述第二封装的端子和至少一个所述键合元件电连接至所述外部部件。
66.一种结构的制作方法，包括：
在以晶片级提供的有源晶元上形成介质封装元件，所述晶元具有相对的第一表面和第二表面，以及在所述第一表面处的多个导电元件，且其中键合元件在其基处联接至所述第一表面的第一部分处的各个所述导电元件，以及所述键合元件的端面远离所述衬底和所述基，每个所述键合元件从其所述基延伸至其所述端面，
其中形成所述介质封装元件，以覆盖所述晶元的所述第一表面的所述第一部分且从所述晶元的所述第一表面的所述第一部分延伸，且填充所述键合元件之间的空间，以使所述键合元件通过所述封装元件相互分离，所述封装元件具有背离所述晶元的所述第一表面的第三表面且具有从所述第三表面向所述第一表面延伸的边缘表面，其中所述键合元件的未封装部分由在所述第三表面处未被所述封装元件覆盖的所述键合元件的所述端面的至少部分限定；以及
其中所述封装元件至少部分限定所述第一表面的第二部分，所述第二部分不同于所述第一表面的所述第一部分且具有容纳微电子元件的整个面积的面积，而且所述第一表面处的至少一些所述导电元件位于所述第二部分且用于与这种微电子元件相连接。
67.根据权利要求66所述的方法，进一步包括：
在形成所述封装元件之后，形成覆盖第一微电子元件和所述第二部分的至少部分的介电块，所述第一微电子元件设置在所述第二部分之上且与至少一些所述导电元件电连接，所述介电块限定远离且背离所述第一表面的第四表面，所述第四表面的至少一部分在所述微电子元件和所述第二部分上方延伸，所述介电块限定面对所述边缘表面的至少部分的第二边缘表面，
其中所述介电块不同于所述封装元件。
68.根据权利要求67所述的方法，其中所述边缘表面的至少部分接触所述第二边缘表面的至少部分。
69.根据权利要求67所述的方法，其中介电块封装所述键合元件的所述未封装部分且覆盖所述封装元件的所述第三表面。
70.根据权利要求67所述的方法，进一步包括：
形成第二介电块，以覆盖所述介电块的所述第四表面和所述封装元件的所述第三表面，且封装所述键合元件的所述未封装部分，
其中所述第二介电块不同于所述封装元件和所述介电块。
71.根据权利要求66所述的方法，进一步包括：
将至少一个微电子元件与所述晶元的所述第一表面的所述第二部分处的一些所述导电元件电连接。
72.根据权利要求66所述的方法，进一步包括：
将所述晶元的所述第一表面的所述第二部分的第一子部分处的至少一个第一微电子元件与所述晶元的所述第一表面的所述第二部分的第二子部分处的至少一个第二微电子元件电连接，其中所述第一子部分和所述第二子部分的面积均具有分别容纳所述第一微电子元件和所述第二微电子元件的整个面积的面积，且在所述第一表面处的至少一些所述导电元件位于所述第二部分的所述第一子部分和所述第二子部分，且用于允许分别与所述第一微电子元件和所述第二微电子元件连接。
73.根据权利要求72所述的方法，进一步包括：
形成第一介电块，以覆盖所述第一微电子元件和所述第一子部分的至少部分，所述第一介电块限定远离且背离所述第一表面的第四表面，所述第四表面的至少部分在所述第一微电子元件和所述第一子部分之上延伸，所述第一介电块限定面对所述边缘表面的至少部分的第二边缘表面，以及
形成第二介电块，以覆盖所述第二微电子元件和所述第二子部分的至少部分，所述第二介电块限定远离且背离所述第一表面的第五表面，所述第五表面的至少部分在所述第二微电子元件和所述第二子部分之上延伸，所述第二介电块限定面对所述边缘表面的至少部分的第二边缘表面，
其中所述第一介电块和所述第二介电块都不同于所述封装元件。
74.根据权利要求72所述的方法，其中所述第一微电子元件是设置在所述第一子部分之上且与所述第二表面处的至少一个所述导电元件电连接的第一微电子封装；以及
其中所述第二微电子元件是设置在所述第二子部分之上且通过外部部件的导电元件与所述第二表面处的至少一个所述导电元件电连接的第二微电子封装，所述第二封装的端子和至少一个所述键合元件电连接至所述外部部件。
CN201380073383.9A 2012-12-20 2013-12-17 用于具有封装键合元件的微电子封装的结构 Pending CN104995732A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/722,189 2012-12-20
US13/722,189 US8878353B2 (en) 2012-12-20 2012-12-20 Structure for microelectronic packaging with bond elements to encapsulation surface
PCT/US2013/075672 WO2014107301A1 (en) 2012-12-20 2013-12-17 Structure for microelectronic packaging with encapsulated bond elements

Publications (1)

Publication Number Publication Date
CN104995732A true CN104995732A (zh) 2015-10-21

Family

ID=49943528

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201380073383.9A Pending CN104995732A (zh) 2012-12-20 2013-12-17 用于具有封装键合元件的微电子封装的结构

Country Status (7)

Country Link
US (3) US8878353B2 (zh)
EP (1) EP2936557A1 (zh)
JP (1) JP6484179B2 (zh)
KR (1) KR20150097669A (zh)
CN (1) CN104995732A (zh)
TW (2) TWI555138B (zh)
WO (1) WO2014107301A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105575832A (zh) * 2015-12-22 2016-05-11 华进半导体封装先导技术研发中心有限公司 一种多层堆叠扇出型封装结构及制备方法
CN106898557A (zh) * 2017-03-03 2017-06-27 中芯长电半导体（江阴）有限公司 集成有供电传输系统的封装件的封装方法

Families Citing this family (88)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101313391B1 (ko) 2004-11-03 2013-10-01 테세라, 인코포레이티드 적층형 패키징
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
WO2011044289A1 (en) * 2009-10-07 2011-04-14 Rain Bird Corporation Volumetric budget based irrigation control
US9941195B2 (en) * 2009-11-10 2018-04-10 Taiwan Semiconductor Manufacturing Co., Ltd. Vertical metal insulator metal capacitor
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US20120146206A1 (en) 2010-12-13 2012-06-14 Tessera Research Llc Pin attachment
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US9105483B2 (en) 2011-10-17 2015-08-11 Invensas Corporation Package-on-package assembly with wire bond vias
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9349706B2 (en) * 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9379078B2 (en) * 2013-11-07 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. 3D die stacking structure with fine pitches
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9576926B2 (en) * 2014-01-16 2017-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Pad structure design in fan-out package
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9653442B2 (en) * 2014-01-17 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and methods of forming same
US9642261B2 (en) * 2014-01-24 2017-05-02 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Composite electronic structure with partially exposed and protruding copper termination posts
US9735134B2 (en) 2014-03-12 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with through-vias having tapered ends
US9214454B2 (en) * 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
KR101565690B1 (ko) * 2014-04-10 2015-11-03 삼성전기주식회사 회로기판, 회로기판 제조방법, 전자부품 패키지 및 전자부품 패키지 제조방법
US9209110B2 (en) * 2014-05-07 2015-12-08 Qualcomm Incorporated Integrated device comprising wires as vias in an encapsulation layer
US9064718B1 (en) * 2014-05-07 2015-06-23 Freescale Semiconductor, Inc. Pre-formed via array for integrated circuit package
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9824990B2 (en) 2014-06-12 2017-11-21 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for reliability enhancement in packages
US9881857B2 (en) * 2014-06-12 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for reliability enhancement in packages
US20160049383A1 (en) * 2014-08-12 2016-02-18 Invensas Corporation Device and method for an integrated ultra-high-density device
TWI623984B (zh) * 2014-08-12 2018-05-11 矽品精密工業股份有限公司 封裝結構及其製法
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
US10354974B2 (en) * 2014-12-11 2019-07-16 Mediatek Inc. Structure and formation method of chip package structure
US9899442B2 (en) 2014-12-11 2018-02-20 Invensas Corporation Image sensor device
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US10679866B2 (en) 2015-02-13 2020-06-09 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structure for semiconductor package and method of fabricating the interconnect structure
US9888579B2 (en) * 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US10276541B2 (en) * 2015-06-30 2019-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. 3D package structure and methods of forming same
US9543277B1 (en) * 2015-08-20 2017-01-10 Invensas Corporation Wafer level packages with mechanically decoupled fan-in and fan-out areas
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US10043779B2 (en) 2015-11-17 2018-08-07 Invensas Corporation Packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
KR101799668B1 (ko) * 2016-04-07 2017-11-20 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
US9659911B1 (en) * 2016-04-20 2017-05-23 Powertech Technology Inc. Package structure and manufacturing method thereof
KR102448098B1 (ko) * 2016-05-31 2022-09-27 에스케이하이닉스 주식회사 관통 몰드 볼 커넥터 및 엘리베이트 패드를 포함하는 반도체 패키지 및 제조 방법
US10050024B2 (en) * 2016-06-17 2018-08-14 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method of the same
US20170365567A1 (en) * 2016-06-20 2017-12-21 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
JP6712050B2 (ja) * 2016-06-21 2020-06-17 富士通株式会社 樹脂基板及びその製造方法、並びに回路基板及びその製造方法
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US20180168042A1 (en) 2016-12-13 2018-06-14 Northrop Grumman Systems Corporation Flexible connector
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
US11430740B2 (en) * 2017-03-29 2022-08-30 Intel Corporation Microelectronic device with embedded die substrate on interposer
US10269756B2 (en) 2017-04-21 2019-04-23 Invensas Bonding Technologies, Inc. Die processing
IT201700055983A1 (it) 2017-05-23 2018-11-23 St Microelectronics Srl Procedimento per produrre dispositivi a semiconduttore, dispositivo a semiconduttore e circuito corrispondenti
US10217720B2 (en) 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US10727219B2 (en) 2018-02-15 2020-07-28 Invensas Bonding Technologies, Inc. Techniques for processing devices
US10593647B2 (en) * 2018-06-27 2020-03-17 Powertech Technology Inc. Package structure and manufacturing method thereof
US20200006274A1 (en) * 2018-06-29 2020-01-02 Powertech Technology Inc. Semiconductor package and manufacturing method thereof
WO2020010265A1 (en) 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Microelectronic assemblies
EP3621104A1 (en) * 2018-09-05 2020-03-11 Infineon Technologies Austria AG Semiconductor package and method of manufacturing a semiconductor package
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11139268B2 (en) * 2019-08-06 2021-10-05 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method of manufacturing the same
US11032935B1 (en) 2019-12-10 2021-06-08 Northrop Grumman Systems Corporation Support structure for a flexible interconnect of a superconductor
US10985495B1 (en) 2020-02-24 2021-04-20 Northrop Grumman Systems Corporation High voltage connector with wet contacts
US11075486B1 (en) 2020-03-02 2021-07-27 Northrop Grumman Systems Corporation Signal connector system
US11742314B2 (en) 2020-03-31 2023-08-29 Adeia Semiconductor Bonding Technologies Inc. Reliable hybrid bonded apparatus
US11038594B1 (en) 2020-05-13 2021-06-15 Northrop Grumman Systems Corporation Self-insulating high bandwidth connector
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11569608B2 (en) 2021-03-30 2023-01-31 Northrop Grumman Systems Corporation Electrical connector system
US11881448B2 (en) * 2021-05-07 2024-01-23 Advanced Semiconductor Engineering, Inc. Semiconductor package structure having substrate with embedded electronic component and conductive pillars
JP2023045852A (ja) * 2021-09-22 2023-04-03 キオクシア株式会社 半導体装置及び半導体装置の製造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101101898A (zh) * 2006-07-06 2008-01-09 三星电机株式会社 层叠封装的底部衬底及其制造方法
CN101286484A (zh) * 2007-04-13 2008-10-15 日本电气株式会社 半导体器件和制造方法
US20120015481A1 (en) * 2010-07-15 2012-01-19 Woo-Jae Kim Method of manufacturing stack type semiconductor package
US20120280386A1 (en) * 2011-05-03 2012-11-08 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface

Family Cites Families (534)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1439262B2 (de) 1963-07-23 1972-03-30 Siemens AG, 1000 Berlin u. 8000 München Verfahren zum kontaktieren von halbleiterbauelementen durch thermokompression
US3358897A (en) 1964-03-31 1967-12-19 Tempress Res Co Electric lead wire bonding tools
US3430835A (en) 1966-06-07 1969-03-04 Westinghouse Electric Corp Wire bonding apparatus for microelectronic components
US3623649A (en) 1969-06-09 1971-11-30 Gen Motors Corp Wedge bonding tool for the attachment of semiconductor leads
DE2119567C2 (de) 1970-05-05 1983-07-14 International Computers Ltd., London Elektrische Verbindungsvorrichtung und Verfahren zu ihrer Herstellung
DE2228703A1 (de) 1972-06-13 1974-01-10 Licentia Gmbh Verfahren zum herstellen einer vorgegebenen lotschichtstaerke bei der fertigung von halbleiterbauelementen
JPS5150661A (zh) 1974-10-30 1976-05-04 Hitachi Ltd
US4067104A (en) 1977-02-24 1978-01-10 Rockwell International Corporation Method of fabricating an array of flexible metallic interconnects for coupling microelectronics components
US4213556A (en) 1978-10-02 1980-07-22 General Motors Corporation Method and apparatus to detect automatic wire bonder failure
US4327860A (en) 1980-01-03 1982-05-04 Kulicke And Soffa Ind. Inc. Method of making slack free wire interconnections
US4422568A (en) 1981-01-12 1983-12-27 Kulicke And Soffa Industries, Inc. Method of making constant bonding wire tail lengths
US4437604A (en) 1982-03-15 1984-03-20 Kulicke & Soffa Industries, Inc. Method of making fine wire interconnections
JPS59189069A (ja) 1983-04-12 1984-10-26 Alps Electric Co Ltd 電気部品の端子のハンダ塗布装置
JPS61125062A (ja) 1984-11-22 1986-06-12 Hitachi Ltd ピン取付け方法およびピン取付け装置
US4604644A (en) 1985-01-28 1986-08-05 International Business Machines Corporation Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and process for making
US4642889A (en) 1985-04-29 1987-02-17 Amp Incorporated Compliant interconnection and method therefor
JP2608701B2 (ja) 1985-09-19 1997-05-14 三菱電機株式会社 保護装置の点検回路
US5917707A (en) 1993-11-16 1999-06-29 Formfactor, Inc. Flexible contact structure with an electrically conductive shell
US5476211A (en) 1993-11-16 1995-12-19 Form Factor, Inc. Method of manufacturing electrical contacts, using a sacrificial member
US4716049A (en) 1985-12-20 1987-12-29 Hughes Aircraft Company Compressive pedestal for microminiature connections
US4924353A (en) 1985-12-20 1990-05-08 Hughes Aircraft Company Connector system for coupling to an integrated circuit chip
JPS62158338A (ja) 1985-12-28 1987-07-14 Tanaka Denshi Kogyo Kk 半導体装置
US4793814A (en) 1986-07-21 1988-12-27 Rogers Corporation Electrical circuit board interconnect
US4695870A (en) 1986-03-27 1987-09-22 Hughes Aircraft Company Inverted chip carrier
JPS62226307A (ja) 1986-03-28 1987-10-05 Toshiba Corp ロボツト装置
US4771930A (en) 1986-06-30 1988-09-20 Kulicke And Soffa Industries Inc. Apparatus for supplying uniform tail lengths
JPS6397941A (ja) 1986-10-14 1988-04-28 Fuji Photo Film Co Ltd 感光材料
US4955523A (en) 1986-12-17 1990-09-11 Raychem Corporation Interconnection of electronic components
DE3703694A1 (de) 1987-02-06 1988-08-18 Dynapert Delvotec Gmbh Ball-bondverfahren und vorrichtung zur durchfuehrung derselben
KR970003915B1 (ko) 1987-06-24 1997-03-22 미다 가쓰시게 반도체 기억장치 및 그것을 사용한 반도체 메모리 모듈
JP2642359B2 (ja) 1987-09-11 1997-08-20 株式会社日立製作所 半導体装置
US5138438A (en) 1987-06-24 1992-08-11 Akita Electronics Co. Ltd. Lead connections means for stacked tab packaged IC chips
US4804132A (en) 1987-08-28 1989-02-14 Difrancesco Louis Method for cold bonding
US4845354A (en) 1988-03-08 1989-07-04 International Business Machines Corporation Process control for laser wire bonding
JPH01313969A (ja) 1988-06-13 1989-12-19 Hitachi Ltd 半導体装置
US4998885A (en) 1989-10-27 1991-03-12 International Business Machines Corporation Elastomeric area array interposer
US5077598A (en) 1989-11-08 1991-12-31 Hewlett-Packard Company Strain relief flip-chip integrated circuit assembly with test fixturing
US5095187A (en) 1989-12-20 1992-03-10 Raychem Corporation Weakening wire supplied through a wire bonder
CA2034700A1 (en) 1990-01-23 1991-07-24 Masanori Nishiguchi Substrate for packaging a semiconductor device
AU645283B2 (en) 1990-01-23 1994-01-13 Sumitomo Electric Industries, Ltd. Substrate for packaging a semiconductor device
US5376403A (en) 1990-02-09 1994-12-27 Capote; Miguel A. Electrically conductive compositions and methods for the preparation and use thereof
US5948533A (en) 1990-02-09 1999-09-07 Ormet Corporation Vertically interconnected electronic assemblies and compositions useful therefor
US5083697A (en) 1990-02-14 1992-01-28 Difrancesco Louis Particle-enhanced joining of metal surfaces
US4975079A (en) 1990-02-23 1990-12-04 International Business Machines Corp. Connector assembly for chip testing
US4999472A (en) 1990-03-12 1991-03-12 Neinast James E Electric arc system for ablating a surface coating
US5241456A (en) 1990-07-02 1993-08-31 General Electric Company Compact high density interconnect structure
US5148266A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies having interposer and flexible lead
US5679977A (en) 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5148265A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
US5067382A (en) 1990-11-02 1991-11-26 Cray Computer Corporation Method and apparatus for notching a lead wire attached to an IC chip to facilitate severing the wire
KR940001149B1 (ko) 1991-04-16 1994-02-14 삼성전자 주식회사 반도체 장치의 칩 본딩 방법
JPH04346436A (ja) 1991-05-24 1992-12-02 Fujitsu Ltd バンプ製造方法とバンプ製造装置
US5316788A (en) 1991-07-26 1994-05-31 International Business Machines Corporation Applying solder to high density substrates
US5203075A (en) 1991-08-12 1993-04-20 Inernational Business Machines Method of bonding flexible circuit to cicuitized substrate to provide electrical connection therebetween using different solders
US5133495A (en) 1991-08-12 1992-07-28 International Business Machines Corporation Method of bonding flexible circuit to circuitized substrate to provide electrical connection therebetween
JPH06510122A (ja) 1991-08-23 1994-11-10 エヌチップ　インコーポレイテッド パッケージされていない集積回路のバーン・イン技術
US5220489A (en) 1991-10-11 1993-06-15 Motorola, Inc. Multicomponent integrated circuit package
US5238173A (en) 1991-12-04 1993-08-24 Kaijo Corporation Wire bonding misattachment detection apparatus and that detection method in a wire bonder
JP2931936B2 (ja) 1992-01-17 1999-08-09 株式会社日立製作所 半導体装置用リードフレームの製造方法及び半導体装置用リードフレーム並びに樹脂封止型半導体装置
US5831836A (en) 1992-01-30 1998-11-03 Lsi Logic Power plane for semiconductor device
US5222014A (en) 1992-03-02 1993-06-22 Motorola, Inc. Three-dimensional multi-chip pad array carrier
US5438224A (en) 1992-04-23 1995-08-01 Motorola, Inc. Integrated circuit package having a face-to-face IC chip arrangement
US5494667A (en) 1992-06-04 1996-02-27 Kabushiki Kaisha Hayahibara Topically applied hair restorer containing pine extract
US6054756A (en) 1992-07-24 2000-04-25 Tessera, Inc. Connection components with frangible leads and bus
US5977618A (en) 1992-07-24 1999-11-02 Tessera, Inc. Semiconductor connection components and methods with releasable lead support
JP3151219B2 (ja) 1992-07-24 2001-04-03 テツセラ，インコーポレイテッド 取り外し自在のリード支持体を備えた半導体接続構成体およびその製造方法
US5371654A (en) 1992-10-19 1994-12-06 International Business Machines Corporation Three dimensional high performance interconnection package
US6295729B1 (en) 1992-10-19 2001-10-02 International Business Machines Corporation Angled flying lead wire bonding process
US20050062492A1 (en) 2001-08-03 2005-03-24 Beaman Brian Samuel High density integrated circuit apparatus, test probe and methods of use thereof
JP2716336B2 (ja) 1993-03-10 1998-02-18 日本電気株式会社 集積回路装置
JPH06268101A (ja) 1993-03-17 1994-09-22 Hitachi Ltd 半導体装置及びその製造方法、電子装置、リ−ドフレ−ム並びに実装基板
US5340771A (en) 1993-03-18 1994-08-23 Lsi Logic Corporation Techniques for providing high I/O count connections to semiconductor dies
US20030048108A1 (en) 1993-04-30 2003-03-13 Beaman Brian Samuel Structural design and processes to control probe position accuracy in a wafer test probe assembly
US7368924B2 (en) 1993-04-30 2008-05-06 International Business Machines Corporation Probe structure having a plurality of discrete insulated probe tips projecting from a support surface, apparatus for use thereof and methods of fabrication thereof
US5811982A (en) 1995-11-27 1998-09-22 International Business Machines Corporation High density cantilevered probe for electronic devices
JP2981385B2 (ja) 1993-09-06 1999-11-22 シャープ株式会社 チップ部品型ｌｅｄの構造及びその製造方法
US5346118A (en) 1993-09-28 1994-09-13 At&T Bell Laboratories Surface mount solder assembly of leadless integrated circuit packages to substrates
US6835898B2 (en) 1993-11-16 2004-12-28 Formfactor, Inc. Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures
US5455390A (en) 1994-02-01 1995-10-03 Tessera, Inc. Microelectronics unit mounting with multiple lead bonding
CN1117395C (zh) 1994-03-18 2003-08-06 日立化成工业株式会社 半导体组件的制造方法及半导体组件
US5615824A (en) 1994-06-07 1997-04-01 Tessera, Inc. Soldering with resilient contacts
US5802699A (en) 1994-06-07 1998-09-08 Tessera, Inc. Methods of assembling microelectronic assembly with socket for engaging bump leads
JPH07335783A (ja) 1994-06-13 1995-12-22 Fujitsu Ltd 半導体装置及び半導体装置ユニット
US5468995A (en) 1994-07-05 1995-11-21 Motorola, Inc. Semiconductor device having compliant columnar electrical connections
US6828668B2 (en) 1994-07-07 2004-12-07 Tessera, Inc. Flexible lead structures and methods of making same
US5688716A (en) 1994-07-07 1997-11-18 Tessera, Inc. Fan-out semiconductor chip assembly
US5518964A (en) 1994-07-07 1996-05-21 Tessera, Inc. Microelectronic mounting with multiple lead deformation and bonding
US6117694A (en) 1994-07-07 2000-09-12 Tessera, Inc. Flexible lead structures and methods of making same
US5989936A (en) 1994-07-07 1999-11-23 Tessera, Inc. Microelectronic assembly fabrication with terminal formation from a conductive layer
US6177636B1 (en) 1994-12-29 2001-01-23 Tessera, Inc. Connection components with posts
US5656550A (en) 1994-08-24 1997-08-12 Fujitsu Limited Method of producing a semicondutor device having a lead portion with outer connecting terminal
US5659952A (en) 1994-09-20 1997-08-26 Tessera, Inc. Method of fabricating compliant interface for semiconductor chip
US5541567A (en) 1994-10-17 1996-07-30 International Business Machines Corporation Coaxial vias in an electronic substrate
US5495667A (en) 1994-11-07 1996-03-05 Micron Technology, Inc. Method for forming contact pins for semiconductor dice and interconnects
US5736074A (en) 1995-06-30 1998-04-07 Micro Fab Technologies, Inc. Manufacture of coated spheres
US5971253A (en) 1995-07-31 1999-10-26 Tessera, Inc. Microelectronic component mounting with deformable shell terminals
US5872051A (en) 1995-08-02 1999-02-16 International Business Machines Corporation Process for transferring material to semiconductor chip conductive pads using a transfer substrate
US5810609A (en) 1995-08-28 1998-09-22 Tessera, Inc. Socket for engaging bump leads on a microelectronic device and methods therefor
US5766987A (en) 1995-09-22 1998-06-16 Tessera, Inc. Microelectronic encapsulation methods and equipment
US6211572B1 (en) 1995-10-31 2001-04-03 Tessera, Inc. Semiconductor chip package with fan-in leads
JPH09134934A (ja) 1995-11-07 1997-05-20 Sumitomo Metal Ind Ltd 半導体パッケージ及び半導体装置
JP3332308B2 (ja) 1995-11-07 2002-10-07 新光電気工業株式会社 半導体装置及びその製造方法
US5718361A (en) 1995-11-21 1998-02-17 International Business Machines Corporation Apparatus and method for forming mold for metallic material
US5731709A (en) 1996-01-26 1998-03-24 Motorola, Inc. Method for testing a ball grid array semiconductor device and a device for such testing
US5994152A (en) 1996-02-21 1999-11-30 Formfactor, Inc. Fabricating interconnects and tips using sacrificial substrates
JP3146345B2 (ja) 1996-03-11 2001-03-12 アムコー テクノロジー コリア インコーポレーティド バンプチップスケール半導体パッケージのバンプ形成方法
US6000126A (en) 1996-03-29 1999-12-14 General Dynamics Information Systems, Inc. Method and apparatus for connecting area grid arrays to printed wire board
US6821821B2 (en) 1996-04-18 2004-11-23 Tessera, Inc. Methods for manufacturing resistors using a sacrificial layer
DE19618227A1 (de) 1996-05-07 1997-11-13 Herbert Streckfus Gmbh Verfahren und Vorrichtung zum Verlöten von elektronischen Bauelementen auf einer Leiterplatte
KR100186333B1 (ko) 1996-06-20 1999-03-20 문정환 칩 사이즈 반도체 패키지 및 그 제조방법
JPH1012769A (ja) 1996-06-24 1998-01-16 Ricoh Co Ltd 半導体装置およびその製造方法
JPH10135221A (ja) 1996-10-29 1998-05-22 Taiyo Yuden Co Ltd バンプ形成方法
JPH10135220A (ja) 1996-10-29 1998-05-22 Taiyo Yuden Co Ltd バンプ形成方法
US6492719B2 (en) 1999-07-30 2002-12-10 Hitachi, Ltd. Semiconductor device
US5976913A (en) 1996-12-12 1999-11-02 Tessera, Inc. Microelectronic mounting with multiple lead deformation using restraining straps
US6133072A (en) 1996-12-13 2000-10-17 Tessera, Inc. Microelectronic connector with planar elastomer sockets
US6225688B1 (en) 1997-12-11 2001-05-01 Tessera, Inc. Stacked microelectronic assembly and method therefor
US6121676A (en) 1996-12-13 2000-09-19 Tessera, Inc. Stacked microelectronic assembly and method therefor
US6054337A (en) 1996-12-13 2000-04-25 Tessera, Inc. Method of making a compliant multichip package
JP3400279B2 (ja) 1997-01-13 2003-04-28 株式会社新川 バンプ形成方法
US5898991A (en) 1997-01-16 1999-05-04 International Business Machines Corporation Methods of fabrication of coaxial vias and magnetic devices
US5839191A (en) 1997-01-24 1998-11-24 Unisys Corporation Vibrating template method of placing solder balls on the I/O pads of an integrated circuit package
JPH1118364A (ja) 1997-06-27 1999-01-22 Matsushita Electric Ind Co Ltd キャプスタンモータ
KR100543836B1 (ko) 1997-08-19 2006-01-23 가부시키가이샤 히타치세이사쿠쇼 멀티칩 모듈 구조체 및 그 제작 방법
CA2213590C (en) 1997-08-21 2006-11-07 Keith C. Carroll Flexible circuit connector and method of making same
JP3859318B2 (ja) 1997-08-29 2006-12-20 シチズン電子株式会社 電子回路のパッケージ方法
US6525414B2 (en) 1997-09-16 2003-02-25 Matsushita Electric Industrial Co., Ltd. Semiconductor device including a wiring board and semiconductor elements mounted thereon
JP3937265B2 (ja) 1997-09-29 2007-06-27 エルピーダメモリ株式会社 半導体装置
JP2978861B2 (ja) 1997-10-28 1999-11-15 九州日本電気株式会社 モールドｂｇａ型半導体装置及びその製造方法
US6038136A (en) 1997-10-29 2000-03-14 Hestia Technologies, Inc. Chip package with molded underfill
JP3393800B2 (ja) 1997-11-05 2003-04-07 新光電気工業株式会社 半導体装置の製造方法
JPH11219984A (ja) 1997-11-06 1999-08-10 Sharp Corp 半導体装置パッケージおよびその製造方法ならびにそのための回路基板
US6222136B1 (en) 1997-11-12 2001-04-24 International Business Machines Corporation Printed circuit board with continuous connective bumps
US6038133A (en) 1997-11-25 2000-03-14 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module and method for producing the same
US6002168A (en) 1997-11-25 1999-12-14 Tessera, Inc. Microelectronic component with rigid interposer
JPH11163022A (ja) 1997-11-28 1999-06-18 Sony Corp 半導体装置、その製造方法及び電子機器
US6124546A (en) 1997-12-03 2000-09-26 Advanced Micro Devices, Inc. Integrated circuit chip package and method of making the same
US6260264B1 (en) 1997-12-08 2001-07-17 3M Innovative Properties Company Methods for making z-axis electrical connections
US6052287A (en) 1997-12-09 2000-04-18 Sandia Corporation Silicon ball grid array chip carrier
US5973391A (en) 1997-12-11 1999-10-26 Read-Rite Corporation Interposer with embedded circuitry and method for using the same to package microelectronic units
JPH11220082A (ja) 1998-02-03 1999-08-10 Oki Electric Ind Co Ltd 半導体装置
JP3536650B2 (ja) 1998-02-27 2004-06-14 富士ゼロックス株式会社 バンプ形成方法および装置
JPH11260856A (ja) 1998-03-11 1999-09-24 Matsushita Electron Corp 半導体装置及びその製造方法並びに半導体装置の実装構造
KR100260997B1 (ko) 1998-04-08 2000-07-01 마이클 디. 오브라이언 반도체패키지
US6329224B1 (en) 1998-04-28 2001-12-11 Tessera, Inc. Encapsulation of microelectronic assemblies
US6180881B1 (en) 1998-05-05 2001-01-30 Harlan Ruben Isaak Chip stack and method of making same
JPH11330134A (ja) 1998-05-12 1999-11-30 Hitachi Ltd ワイヤボンディング方法およびその装置並びに半導体装置
KR100266693B1 (ko) 1998-05-30 2000-09-15 김영환 적층가능한 비지에이 반도체 칩 패키지 및 그 제조방법
US5977640A (en) * 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
KR100265563B1 (ko) 1998-06-29 2000-09-15 김영환 볼 그리드 어레이 패키지 및 그의 제조 방법
US6414391B1 (en) 1998-06-30 2002-07-02 Micron Technology, Inc. Module assembly for stacked BGA packages with a common bus bar in the assembly
US6164523A (en) 1998-07-01 2000-12-26 Semiconductor Components Industries, Llc Electronic component and method of manufacture
US6399426B1 (en) 1998-07-21 2002-06-04 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
US5854507A (en) 1998-07-21 1998-12-29 Hewlett-Packard Company Multiple chip assembly
US6515355B1 (en) 1998-09-02 2003-02-04 Micron Technology, Inc. Passivation layer for packaged integrated circuits
JP2000091383A (ja) 1998-09-07 2000-03-31 Ngk Spark Plug Co Ltd 配線基板
US6194250B1 (en) 1998-09-14 2001-02-27 Motorola, Inc. Low-profile microelectronic package
US6158647A (en) 1998-09-29 2000-12-12 Micron Technology, Inc. Concave face wire bond capillary
US6684007B2 (en) 1998-10-09 2004-01-27 Fujitsu Limited Optical coupling structures and the fabrication processes
US6268662B1 (en) 1998-10-14 2001-07-31 Texas Instruments Incorporated Wire bonded flip-chip assembly of semiconductor devices
JP3407275B2 (ja) 1998-10-28 2003-05-19 インターナショナル・ビジネス・マシーンズ・コーポレーション バンプ及びその形成方法
US6332270B2 (en) 1998-11-23 2001-12-25 International Business Machines Corporation Method of making high density integral test probe
WO2000045430A1 (en) 1999-01-29 2000-08-03 Matsushita Electric Industrial Co., Ltd. Electronic parts mounting method and device therefor
US6206273B1 (en) 1999-02-17 2001-03-27 International Business Machines Corporation Structures and processes to create a desired probetip contact geometry on a wafer test probe
JP2000243876A (ja) * 1999-02-23 2000-09-08 Fujitsu Ltd 半導体装置とその製造方法
KR100319609B1 (ko) 1999-03-09 2002-01-05 김영환 와이어 어래이드 칩 사이즈 패키지 및 그 제조방법
US6177729B1 (en) 1999-04-03 2001-01-23 International Business Machines Corporation Rolling ball connector
US6211574B1 (en) 1999-04-16 2001-04-03 Advanced Semiconductor Engineering Inc. Semiconductor package with wire protection and method therefor
US6258625B1 (en) 1999-05-18 2001-07-10 International Business Machines Corporation Method of interconnecting electronic components using a plurality of conductive studs
US6376769B1 (en) 1999-05-18 2002-04-23 Amerasia International Technology, Inc. High-density electronic package, and method for making same
JP3398721B2 (ja) 1999-05-20 2003-04-21 アムコー テクノロジー コリア インコーポレーティド 半導体パッケージ及びその製造方法
US6228687B1 (en) 1999-06-28 2001-05-08 Micron Technology, Inc. Wafer-level package and methods of fabricating
TW417839U (en) 1999-07-30 2001-01-01 Shen Ming Tung Stacked memory module structure and multi-layered stacked memory module structure using the same
JP4526651B2 (ja) 1999-08-12 2010-08-18 富士通セミコンダクター株式会社 半導体装置
JP5333337B2 (ja) 1999-08-12 2013-11-06 富士通セミコンダクター株式会社 半導体装置の製造方法
US6168965B1 (en) 1999-08-12 2001-01-02 Tower Semiconductor Ltd. Method for making backside illuminated image sensor
KR100842389B1 (ko) 1999-09-02 2008-07-01 이비덴 가부시키가이샤 프린트배선판 및 그 제조방법
US6867499B1 (en) 1999-09-30 2005-03-15 Skyworks Solutions, Inc. Semiconductor packaging
JP3513444B2 (ja) 1999-10-20 2004-03-31 株式会社新川 ピン状ワイヤ等の形成方法
JP2001127246A (ja) 1999-10-29 2001-05-11 Fujitsu Ltd 半導体装置
US6362525B1 (en) 1999-11-09 2002-03-26 Cypress Semiconductor Corp. Circuit structure including a passive element formed within a grid array substrate and method for making the same
JP3619410B2 (ja) 1999-11-18 2005-02-09 株式会社ルネサステクノロジ バンプ形成方法およびそのシステム
JP3798597B2 (ja) 1999-11-30 2006-07-19 富士通株式会社 半導体装置
JP3566156B2 (ja) 1999-12-02 2004-09-15 株式会社新川 ピン状ワイヤ等の形成方法
KR100426494B1 (ko) 1999-12-20 2004-04-13 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 이것의 제조방법
US6790757B1 (en) 1999-12-20 2004-09-14 Agere Systems Inc. Wire bonding method for copper interconnects in semiconductor devices
KR20010061849A (ko) 1999-12-29 2001-07-07 박종섭 웨이퍼 레벨 패키지
JP2001196407A (ja) 2000-01-14 2001-07-19 Seiko Instruments Inc 半導体装置および半導体装置の形成方法
US6710454B1 (en) 2000-02-16 2004-03-23 Micron Technology, Inc. Adhesive layer for an electronic apparatus having multiple semiconductor devices
JP2001339011A (ja) 2000-03-24 2001-12-07 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
JP3980807B2 (ja) 2000-03-27 2007-09-26 株式会社東芝 半導体装置及び半導体モジュール
JP2001274196A (ja) 2000-03-28 2001-10-05 Rohm Co Ltd 半導体装置
KR100583491B1 (ko) 2000-04-07 2006-05-24 앰코 테크놀로지 코리아 주식회사 반도체패키지 및 그 제조방법
US6578754B1 (en) 2000-04-27 2003-06-17 Advanpack Solutions Pte. Ltd. Pillar connections for semiconductor chips and method of manufacture
US6531335B1 (en) 2000-04-28 2003-03-11 Micron Technology, Inc. Interposers including upwardly protruding dams, semiconductor device assemblies including the interposers, and methods
JP2001326236A (ja) 2000-05-12 2001-11-22 Nec Kyushu Ltd 半導体装置の製造方法
JP2001326304A (ja) 2000-05-15 2001-11-22 Toshiba Corp 半導体装置及びその製造方法
US6522018B1 (en) 2000-05-16 2003-02-18 Micron Technology, Inc. Ball grid array chip packages having improved testing and stacking characteristics
US6647310B1 (en) 2000-05-30 2003-11-11 Advanced Micro Devices, Inc. Temperature control of an integrated circuit
US6531784B1 (en) 2000-06-02 2003-03-11 Amkor Technology, Inc. Semiconductor package with spacer strips
US6560117B2 (en) 2000-06-28 2003-05-06 Micron Technology, Inc. Packaged microelectronic die assemblies and methods of manufacture
US6476583B2 (en) 2000-07-21 2002-11-05 Jomahip, Llc Automatic battery charging system for a battery back-up DC power supply
SE517086C2 (sv) 2000-08-08 2002-04-09 Ericsson Telefon Ab L M Förfarande för säkring av lodkulor och eventuella komponenter, vilka är fästa på en och samma sida av ett substrat
US20020020898A1 (en) 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US6462575B1 (en) 2000-08-28 2002-10-08 Micron Technology, Inc. Method and system for wafer level testing and burning-in semiconductor components
JP3874062B2 (ja) 2000-09-05 2007-01-31 セイコーエプソン株式会社 半導体装置
US6507104B2 (en) 2000-09-07 2003-01-14 Siliconware Precision Industries Co., Ltd. Semiconductor package with embedded heat-dissipating device
US7009297B1 (en) 2000-10-13 2006-03-07 Bridge Semiconductor Corporation Semiconductor chip assembly with embedded metal particle
US6423570B1 (en) 2000-10-18 2002-07-23 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
JP4505983B2 (ja) 2000-12-01 2010-07-21 日本電気株式会社 半導体装置
JP3798620B2 (ja) 2000-12-04 2006-07-19 富士通株式会社 半導体装置の製造方法
TW511405B (en) 2000-12-27 2002-11-21 Matsushita Electric Ind Co Ltd Device built-in module and manufacturing method thereof
KR100393102B1 (ko) 2000-12-29 2003-07-31 앰코 테크놀로지 코리아 주식회사 스택형 반도체패키지
AUPR244801A0 (en) 2001-01-10 2001-02-01 Silverbrook Research Pty Ltd A method and apparatus (WSM01)
US6388322B1 (en) 2001-01-17 2002-05-14 Aralight, Inc. Article comprising a mechanically compliant bump
US6653170B1 (en) 2001-02-06 2003-11-25 Charles W. C. Lin Semiconductor chip assembly with elongated wire ball bonded to chip and electrolessly plated to support circuit
JP2002280414A (ja) 2001-03-22 2002-09-27 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2002289769A (ja) 2001-03-26 2002-10-04 Matsushita Electric Ind Co Ltd 積層型半導体装置およびその製造方法
SG108245A1 (en) 2001-03-30 2005-01-28 Micron Technology Inc Ball grid array interposer, packages and methods
US7115986B2 (en) 2001-05-02 2006-10-03 Micron Technology, Inc. Flexible ball grid array chip scale packages
US6825552B2 (en) 2001-05-09 2004-11-30 Tessera, Inc. Connection components with anisotropic conductive material interconnection
TW544826B (en) 2001-05-18 2003-08-01 Nec Electronics Corp Flip-chip-type semiconductor device and manufacturing method thereof
US6930256B1 (en) 2002-05-01 2005-08-16 Amkor Technology, Inc. Integrated circuit substrate having laser-embedded conductive patterns and method therefor
US6754407B2 (en) 2001-06-26 2004-06-22 Intel Corporation Flip-chip package integrating optical and electrical devices and coupling to a waveguide on a board
US20030006494A1 (en) 2001-07-03 2003-01-09 Lee Sang Ho Thin profile stackable semiconductor package and method for manufacturing
US6765287B1 (en) 2001-07-27 2004-07-20 Charles W. C. Lin Three-dimensional stacked semiconductor package
US6451626B1 (en) 2001-07-27 2002-09-17 Charles W.C. Lin Three-dimensional stacked semiconductor package
JP4023159B2 (ja) 2001-07-31 2007-12-19 ソニー株式会社 半導体装置の製造方法及び積層半導体装置の製造方法
US6550666B2 (en) 2001-08-21 2003-04-22 Advanpack Solutions Pte Ltd Method for forming a flip chip on leadframe semiconductor package
WO2003019654A1 (en) 2001-08-22 2003-03-06 Tessera, Inc. Stacked chip assembly with stiffening layer
US7176506B2 (en) 2001-08-28 2007-02-13 Tessera, Inc. High frequency chip packages with connecting elements
US20030057544A1 (en) 2001-09-13 2003-03-27 Nathan Richard J. Integrated assembly protocol
US6977440B2 (en) 2001-10-09 2005-12-20 Tessera, Inc. Stacked packages
US6897565B2 (en) 2001-10-09 2005-05-24 Tessera, Inc. Stacked packages
JP2003122611A (ja) 2001-10-11 2003-04-25 Oki Electric Ind Co Ltd データ提供方法及びサーバ装置
JP4257771B2 (ja) 2001-10-16 2009-04-22 シンジーテック株式会社 導電性ブレード
JP3875077B2 (ja) 2001-11-16 2007-01-31 富士通株式会社 電子デバイス及びデバイス接続方法
US20030094666A1 (en) 2001-11-16 2003-05-22 R-Tec Corporation Interposer
JP2003174124A (ja) 2001-12-04 2003-06-20 Sainekkusu:Kk 半導体装置の外部電極形成方法
JP3507059B2 (ja) 2002-06-27 2004-03-15 沖電気工業株式会社 積層マルチチップパッケージ
JP2003197669A (ja) 2001-12-28 2003-07-11 Seiko Epson Corp ボンディング方法及びボンディング装置
TW584950B (en) 2001-12-31 2004-04-21 Megic Corp Chip packaging structure and process thereof
JP3935370B2 (ja) 2002-02-19 2007-06-20 セイコーエプソン株式会社 バンプ付き半導体素子の製造方法、半導体装置及びその製造方法、回路基板並びに電子機器
SG115456A1 (en) 2002-03-04 2005-10-28 Micron Technology Inc Semiconductor die packages with recessed interconnecting structures and methods for assembling the same
US6653723B2 (en) 2002-03-09 2003-11-25 Fujitsu Limited System for providing an open-cavity low profile encapsulated semiconductor package
KR100452819B1 (ko) 2002-03-18 2004-10-15 삼성전기주식회사 칩 패키지 및 그 제조방법
US6979230B2 (en) 2002-03-20 2005-12-27 Gabe Cherian Light socket
JP2003318327A (ja) * 2002-04-22 2003-11-07 Mitsui Chemicals Inc プリント配線板および積層パッケージ
US7323767B2 (en) 2002-04-25 2008-01-29 Micron Technology, Inc. Standoffs for centralizing internals in packaging process
US7633765B1 (en) 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
US7078822B2 (en) 2002-06-25 2006-07-18 Intel Corporation Microelectronic device interconnects
JP2004047702A (ja) 2002-07-11 2004-02-12 Toshiba Corp 半導体装置積層モジュール
US6756252B2 (en) 2002-07-17 2004-06-29 Texas Instrument Incorporated Multilayer laser trim interconnect method
US6987032B1 (en) 2002-07-19 2006-01-17 Asat Ltd. Ball grid array package and process for manufacturing same
US7053485B2 (en) 2002-08-16 2006-05-30 Tessera, Inc. Microelectronic packages with self-aligning features
TW549592U (en) 2002-08-16 2003-08-21 Via Tech Inc Integrated circuit package with a balanced-part structure
US6740546B2 (en) 2002-08-21 2004-05-25 Micron Technology, Inc. Packaged microelectronic devices and methods for assembling microelectronic devices
US6964881B2 (en) 2002-08-27 2005-11-15 Micron Technology, Inc. Multi-chip wafer level system packages and methods of forming same
JP3765778B2 (ja) 2002-08-29 2006-04-12 ローム株式会社 ワイヤボンディング用キャピラリ及びこれを用いたワイヤボンディング方法
JP2004095799A (ja) 2002-08-30 2004-03-25 Toshiba Corp 半導体装置およびその製造方法
US7294928B2 (en) 2002-09-06 2007-11-13 Tessera, Inc. Components, methods and assemblies for stacked packages
US7246431B2 (en) 2002-09-06 2007-07-24 Tessera, Inc. Methods of making microelectronic packages including folded substrates
US7071547B2 (en) 2002-09-11 2006-07-04 Tessera, Inc. Assemblies having stacked semiconductor chips and methods of making same
US7229906B2 (en) 2002-09-19 2007-06-12 Kulicke And Soffa Industries, Inc. Method and apparatus for forming bumps for semiconductor interconnections using a wire bonding machine
US7259445B2 (en) 2002-09-30 2007-08-21 Advanced Interconnect Technologies Limited Thermal enhanced package for block mold assembly
US7045884B2 (en) 2002-10-04 2006-05-16 International Rectifier Corporation Semiconductor device package
US7049691B2 (en) 2002-10-08 2006-05-23 Chippac, Inc. Semiconductor multi-package module having inverted second package and including additional die or stacked package on second package
US6989122B1 (en) 2002-10-17 2006-01-24 National Semiconductor Corporation Techniques for manufacturing flash-free contacts on a semiconductor package
TW567601B (en) 2002-10-18 2003-12-21 Siliconware Precision Industries Co Ltd Module device of stacked semiconductor package and method for fabricating the same
TWI221664B (en) 2002-11-07 2004-10-01 Via Tech Inc Structure of chip package and process thereof
JP2004172157A (ja) 2002-11-15 2004-06-17 Shinko Electric Ind Co Ltd 半導体パッケージおよびパッケージスタック半導体装置
JP2004172477A (ja) 2002-11-21 2004-06-17 Kaijo Corp ワイヤループ形状、そのワイヤループ形状を備えた半導体装置、ワイヤボンディング方法及び半導体製造装置
JP4464041B2 (ja) 2002-12-13 2010-05-19 キヤノン株式会社 柱状構造体、柱状構造体を有する電極、及びこれらの作製方法
KR100621991B1 (ko) 2003-01-03 2006-09-13 삼성전자주식회사 칩 스케일 적층 패키지
JP2004221257A (ja) 2003-01-14 2004-08-05 Seiko Epson Corp ワイヤボンディング方法及びワイヤボンディング装置
US20040222518A1 (en) 2003-02-25 2004-11-11 Tessera, Inc. Ball grid array with bumps
TW583757B (en) 2003-02-26 2004-04-11 Advanced Semiconductor Eng A structure of a flip-chip package and a process thereof
US20040217471A1 (en) 2003-02-27 2004-11-04 Tessera, Inc. Component and assemblies with ends offset downwardly
JP3885747B2 (ja) 2003-03-13 2007-02-28 株式会社デンソー ワイヤボンディング方法
JP2004343030A (ja) 2003-03-31 2004-12-02 North:Kk 配線回路基板とその製造方法とその配線回路基板を備えた回路モジュール
JP2004319892A (ja) 2003-04-18 2004-11-11 Renesas Technology Corp 半導体装置の製造方法
JP4199588B2 (ja) 2003-04-25 2008-12-17 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド 配線回路基板の製造方法、及び、この配線回路基板を用いた半導体集積回路装置の製造方法
DE10320646A1 (de) 2003-05-07 2004-09-16 Infineon Technologies Ag Elektronisches Bauteil, sowie Systemträger und Nutzen zur Herstellung desselben
JP4145730B2 (ja) 2003-06-17 2008-09-03 松下電器産業株式会社 半導体内蔵モジュール
US20040262728A1 (en) 2003-06-30 2004-12-30 Sterrett Terry L. Modular device assemblies
KR100604821B1 (ko) 2003-06-30 2006-07-26 삼성전자주식회사 적층형 볼 그리드 어레이 패키지 및 그 제조방법
JP2005033141A (ja) 2003-07-11 2005-02-03 Sony Corp 半導体装置及びその製造方法、疑似ウェーハ及びその製造方法、並びに半導体装置の実装構造
US7227095B2 (en) 2003-08-06 2007-06-05 Micron Technology, Inc. Wire bonders and methods of wire-bonding
KR100546374B1 (ko) 2003-08-28 2006-01-26 삼성전자주식회사 센터 패드를 갖는 적층형 반도체 패키지 및 그 제조방법
US7372151B1 (en) 2003-09-12 2008-05-13 Asat Ltd. Ball grid array package and process for manufacturing same
JP3999720B2 (ja) * 2003-09-16 2007-10-31 沖電気工業株式会社 半導体装置およびその製造方法
US7061096B2 (en) 2003-09-24 2006-06-13 Silicon Pipe, Inc. Multi-surface IC packaging structures and methods for their manufacture
US20050085016A1 (en) 2003-09-26 2005-04-21 Tessera, Inc. Structure and method of making capped chips using sacrificial layer
US7462936B2 (en) 2003-10-06 2008-12-09 Tessera, Inc. Formation of circuitry with modification of feature height
JP4272968B2 (ja) 2003-10-16 2009-06-03 エルピーダメモリ株式会社 半導体装置および半導体チップ制御方法
JP4167965B2 (ja) 2003-11-07 2008-10-22 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド 配線回路用部材の製造方法
KR100564585B1 (ko) 2003-11-13 2006-03-28 삼성전자주식회사 이중 스택된 ｂｇａ 패키지 및 다중 스택된 ｂｇａ 패키지
TWI227555B (en) 2003-11-17 2005-02-01 Advanced Semiconductor Eng Structure of chip package and the process thereof
KR100621992B1 (ko) 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
JP2005183923A (ja) 2003-11-28 2005-07-07 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US7345361B2 (en) 2003-12-04 2008-03-18 Intel Corporation Stackable integrated circuit packaging
JP2005175019A (ja) 2003-12-08 2005-06-30 Sharp Corp 半導体装置及び積層型半導体装置
JP5197961B2 (ja) 2003-12-17 2013-05-15 スタッツ・チップパック・インコーポレイテッド マルチチップパッケージモジュールおよびその製造方法
DE10360708B4 (de) 2003-12-19 2008-04-10 Infineon Technologies Ag Halbleitermodul mit einem Halbleiterstapel, Umverdrahtungsplatte, und Verfahren zur Herstellung derselben
JP4334996B2 (ja) 2003-12-24 2009-09-30 株式会社フジクラ 多層配線板用基材、両面配線板およびそれらの製造方法
US7495644B2 (en) 2003-12-26 2009-02-24 Semiconductor Energy Laboratory Co., Ltd. Display device and method for manufacturing display device
US6900530B1 (en) 2003-12-29 2005-05-31 Ramtek Technology, Inc. Stacked IC
US6917098B1 (en) 2003-12-29 2005-07-12 Texas Instruments Incorporated Three-level leadframe for no-lead packages
WO2005065207A2 (en) 2003-12-30 2005-07-21 Tessera, Inc. Microelectronic packages and methods therefor
US7709968B2 (en) 2003-12-30 2010-05-04 Tessera, Inc. Micro pin grid array with pin motion isolation
US8207604B2 (en) 2003-12-30 2012-06-26 Tessera, Inc. Microelectronic package comprising offset conductive posts on compliant layer
JP2005203497A (ja) 2004-01-14 2005-07-28 Toshiba Corp 半導体装置およびその製造方法
US20050173807A1 (en) 2004-02-05 2005-08-11 Jianbai Zhu High density vertically stacked semiconductor device
US8399972B2 (en) 2004-03-04 2013-03-19 Skyworks Solutions, Inc. Overmolded semiconductor package with a wirebond cage for EMI shielding
US7095105B2 (en) 2004-03-23 2006-08-22 Texas Instruments Incorporated Vertically stacked semiconductor device
JP4484035B2 (ja) 2004-04-06 2010-06-16 セイコーエプソン株式会社 半導体装置の製造方法
US8092734B2 (en) 2004-05-13 2012-01-10 Aptina Imaging Corporation Covers for microelectronic imagers and methods for wafer-level packaging of microelectronics imagers
US7629695B2 (en) 2004-05-20 2009-12-08 Kabushiki Kaisha Toshiba Stacked electronic component and manufacturing method thereof
US6962864B1 (en) 2004-05-26 2005-11-08 National Chung Cheng University Wire-bonding method for chips with copper interconnects by introducing a thin layer
US7233057B2 (en) 2004-05-28 2007-06-19 Nokia Corporation Integrated circuit package with optimized mold shape
TWI255022B (en) 2004-05-31 2006-05-11 Via Tech Inc Circuit carrier and manufacturing process thereof
US7453157B2 (en) 2004-06-25 2008-11-18 Tessera, Inc. Microelectronic packages and methods therefor
JP4385329B2 (ja) 2004-10-08 2009-12-16 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
EP1807239A2 (de) 2004-11-02 2007-07-18 Imasys AG Verlegevorrichtung, kontaktiervorrichtung, zustellsystem, verlege- und kontaktiereinheit herstellungsanlage, verfahren zur herstellung und eine transpondereinheit
KR101313391B1 (ko) 2004-11-03 2013-10-01 테세라, 인코포레이티드 적층형 패키징
US7268421B1 (en) 2004-11-10 2007-09-11 Bridge Semiconductor Corporation Semiconductor chip assembly with welded metal pillar that includes enlarged ball bond
US7750483B1 (en) 2004-11-10 2010-07-06 Bridge Semiconductor Corporation Semiconductor chip assembly with welded metal pillar and enlarged plated contact terminal
KR100674926B1 (ko) 2004-12-08 2007-01-26 삼성전자주식회사 메모리 카드 및 그 제조 방법
JP4504798B2 (ja) 2004-12-16 2010-07-14 パナソニック株式会社 多段構成半導体モジュール
JP2006186086A (ja) 2004-12-27 2006-07-13 Itoo:Kk プリント基板のはんだ付け方法およびブリッジ防止用ガイド板
DE102005006333B4 (de) 2005-02-10 2007-10-18 Infineon Technologies Ag Halbleiterbauteil mit mehreren Bondanschlüssen und gebondeten Kontaktelementen unterschiedlicher Metallzusammensetzung und Verfahren zur Herstellung desselben
DE102005006995B4 (de) 2005-02-15 2008-01-24 Infineon Technologies Ag Halbleiterbauteil mit Kunstoffgehäuse und Außenanschlüssen sowie Verfahren zur Herstellung desselben
KR100630741B1 (ko) 2005-03-04 2006-10-02 삼성전자주식회사 다중 몰딩에 의한 적층형 반도체 패키지 및 그 제조방법
US7939934B2 (en) 2005-03-16 2011-05-10 Tessera, Inc. Microelectronic packages and methods therefor
US7371676B2 (en) 2005-04-08 2008-05-13 Micron Technology, Inc. Method for fabricating semiconductor components with through wire interconnects
TWI284394B (en) 2005-05-12 2007-07-21 Advanced Semiconductor Eng Lid used in package structure and the package structure of having the same
JP2006324553A (ja) 2005-05-20 2006-11-30 Renesas Technology Corp 半導体装置及びその製造方法
US7216794B2 (en) 2005-06-09 2007-05-15 Texas Instruments Incorporated Bond capillary design for ribbon wire bonding
JP4322844B2 (ja) 2005-06-10 2009-09-02 シャープ株式会社 半導体装置および積層型半導体装置
WO2007004137A2 (en) 2005-07-01 2007-01-11 Koninklijke Philips Electronics N.V. Electronic device
US7476608B2 (en) 2005-07-14 2009-01-13 Hewlett-Packard Development Company, L.P. Electrically connecting substrate with electrical device
TWI263313B (en) 2005-08-15 2006-10-01 Phoenix Prec Technology Corp Stack structure of semiconductor component embedded in supporting board
SG130055A1 (en) 2005-08-19 2007-03-20 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
SG130066A1 (en) 2005-08-26 2007-03-20 Micron Technology Inc Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices
JP5522561B2 (ja) 2005-08-31 2014-06-18 マイクロン テクノロジー， インク． マイクロ電子デバイスパッケージ、積重ね型マイクロ電子デバイスパッケージ、およびマイクロ電子デバイスを製造する方法
US7675152B2 (en) 2005-09-01 2010-03-09 Texas Instruments Incorporated Package-on-package semiconductor assembly
JP4662356B2 (ja) * 2005-10-21 2011-03-30 キヤノン株式会社 撮像装置及びその制御方法、及びその制御プログラム、制御プログラムを格納した記憶媒体
US7504716B2 (en) 2005-10-26 2009-03-17 Texas Instruments Incorporated Structure and method of molded QFN device suitable for miniaturization, multiple rows and stacking
JP2007123524A (ja) * 2005-10-27 2007-05-17 Shinko Electric Ind Co Ltd 電子部品内蔵基板
JP2007123595A (ja) 2005-10-28 2007-05-17 Nec Corp 半導体装置及びその実装構造
US8183682B2 (en) 2005-11-01 2012-05-22 Nxp B.V. Methods of packaging a semiconductor die and package formed by the methods
JP4530975B2 (ja) 2005-11-14 2010-08-25 株式会社新川 ワイヤボンディング方法
JP2007142042A (ja) 2005-11-16 2007-06-07 Sharp Corp 半導体パッケージとその製造方法，半導体モジュール，および電子機器
US7344917B2 (en) 2005-11-30 2008-03-18 Freescale Semiconductor, Inc. Method for packaging a semiconductor device
US7307348B2 (en) 2005-12-07 2007-12-11 Micron Technology, Inc. Semiconductor components having through wire interconnects (TWI)
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
JP4530984B2 (ja) 2005-12-28 2010-08-25 株式会社新川 ワイヤボンディング装置、ボンディング制御プログラム及びボンディング方法
US20070190747A1 (en) 2006-01-23 2007-08-16 Tessera Technologies Hungary Kft. Wafer level packaging to lidded chips
JP2007208159A (ja) 2006-02-06 2007-08-16 Hitachi Ltd 半導体装置
SG135074A1 (en) 2006-02-28 2007-09-28 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
JP2007234845A (ja) 2006-03-01 2007-09-13 Nec Corp 半導体装置
US7390700B2 (en) 2006-04-07 2008-06-24 Texas Instruments Incorporated Packaged system of semiconductor chips having a semiconductor interposer
US7759782B2 (en) 2006-04-07 2010-07-20 Tessera, Inc. Substrate for a microelectronic package and method of fabricating thereof
JP5598787B2 (ja) 2006-04-17 2014-10-01 マイクロンメモリジャパン株式会社 積層型半導体装置の製造方法
US7659612B2 (en) 2006-04-24 2010-02-09 Micron Technology, Inc. Semiconductor components having encapsulated through wire interconnects (TWI)
US7242081B1 (en) 2006-04-24 2007-07-10 Advanced Semiconductor Engineering Inc. Stacked package structure
US7780064B2 (en) 2006-06-02 2010-08-24 Asm Technology Singapore Pte Ltd Wire bonding method for forming low-loop profiles
JP4961848B2 (ja) 2006-06-12 2012-06-27 日本電気株式会社 金属ポストを有する配線基板、半導体装置及び半導体装置モジュールの製造方法
US7967062B2 (en) 2006-06-16 2011-06-28 International Business Machines Corporation Thermally conductive composite interface, cooled electronic assemblies employing the same, and methods of fabrication thereof
US20070290325A1 (en) 2006-06-16 2007-12-20 Lite-On Semiconductor Corporation Surface mounting structure and packaging method thereof
CN101449375B (zh) 2006-06-29 2012-01-18 英特尔公司 用于集成电路封装中的无导线连接的设备、系统和方法
KR100800478B1 (ko) 2006-07-18 2008-02-04 삼성전자주식회사 적층형 반도체 패키지 및 그의 제조방법
US20080023805A1 (en) 2006-07-26 2008-01-31 Texas Instruments Incorporated Array-Processed Stacked Semiconductor Packages
US8048479B2 (en) 2006-08-01 2011-11-01 Qimonda Ag Method for placing material onto a target board by means of a transfer board
JP2008039502A (ja) 2006-08-03 2008-02-21 Alps Electric Co Ltd 接触子およびその製造方法
US7486525B2 (en) 2006-08-04 2009-02-03 International Business Machines Corporation Temporary chip attach carrier
US7425758B2 (en) 2006-08-28 2008-09-16 Micron Technology, Inc. Metal core foldover package structures
KR20080020069A (ko) 2006-08-30 2008-03-05 삼성전자주식회사 반도체 패키지 및 그 제조방법
KR100891516B1 (ko) 2006-08-31 2009-04-06 주식회사 하이닉스반도체 적층 가능한 에프비지에이 타입 반도체 패키지와 이를이용한 적층 패키지
KR100770934B1 (ko) 2006-09-26 2007-10-26 삼성전자주식회사 반도체 패키지와 그를 이용한 반도체 시스템 패키지
TWI336502B (en) 2006-09-27 2011-01-21 Advanced Semiconductor Eng Semiconductor package and semiconductor device and the method of making the same
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
TWI312561B (en) 2006-10-27 2009-07-21 Advanced Semiconductor Eng Structure of package on package and method for fabricating the same
KR100817073B1 (ko) 2006-11-03 2008-03-26 삼성전자주식회사 휨방지용 보강부재가 기판에 연결된 반도체 칩 스택 패키지
US8193034B2 (en) 2006-11-10 2012-06-05 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure using stud bumps
WO2008065896A1 (fr) 2006-11-28 2008-06-05 Kyushu Institute Of Technology Procédé de fabrication d'un dispositif semi-conducteur ayant une structure d'électrode à double face et dispositif semi-conducteur fabriqué par le procédé
JP2008166439A (ja) 2006-12-27 2008-07-17 Spansion Llc 半導体装置およびその製造方法
US8598717B2 (en) 2006-12-27 2013-12-03 Spansion Llc Semiconductor device and method for manufacturing the same
KR100757345B1 (ko) 2006-12-29 2007-09-10 삼성전자주식회사 플립 칩 패키지 및 그의 제조 방법
US20080156518A1 (en) 2007-01-03 2008-07-03 Tessera, Inc. Alignment and cutting of microelectronic substrates
TWI332702B (en) 2007-01-09 2010-11-01 Advanced Semiconductor Eng Stackable semiconductor package and the method for making the same
JP5347222B2 (ja) 2007-01-10 2013-11-20 富士通株式会社 半導体装置の製造方法
US7719122B2 (en) 2007-01-11 2010-05-18 Taiwan Semiconductor Manufacturing Co., Ltd. System-in-package packaging for minimizing bond wire contamination and yield loss
CN101617400A (zh) 2007-01-31 2009-12-30 富士通微电子株式会社 半导体器件及其制造方法
JP4823089B2 (ja) 2007-01-31 2011-11-24 株式会社東芝 積層型半導体装置の製造方法
US8685792B2 (en) 2007-03-03 2014-04-01 Stats Chippac Ltd. Integrated circuit package system with interposer
EP2575166A3 (en) 2007-03-05 2014-04-09 Invensas Corporation Chips having rear contacts connected by through vias to front contacts
US7517733B2 (en) 2007-03-22 2009-04-14 Stats Chippac, Ltd. Leadframe design for QFN package with top terminal leads
JPWO2008117488A1 (ja) 2007-03-23 2010-07-08 三洋電機株式会社 半導体装置およびその製造方法
WO2008120755A1 (ja) 2007-03-30 2008-10-09 Nec Corporation 機能素子内蔵回路基板及びその製造方法、並びに電子機器
JP4926787B2 (ja) 2007-03-30 2012-05-09 アオイ電子株式会社 半導体装置の製造方法
US7589394B2 (en) 2007-04-10 2009-09-15 Ibiden Co., Ltd. Interposer
US7994622B2 (en) 2007-04-16 2011-08-09 Tessera, Inc. Microelectronic packages having cavities for receiving microelectric elements
KR20080094251A (ko) 2007-04-19 2008-10-23 삼성전자주식회사 웨이퍼 레벨 패키지 및 그 제조방법
JP5601751B2 (ja) 2007-04-26 2014-10-08 スパンション エルエルシー 半導体装置
US20080284045A1 (en) 2007-05-18 2008-11-20 Texas Instruments Incorporated Method for Fabricating Array-Molded Package-On-Package
JP2008306128A (ja) 2007-06-11 2008-12-18 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
KR100865125B1 (ko) 2007-06-12 2008-10-24 삼성전기주식회사 반도체 패키지 및 그 제조방법
US20080308305A1 (en) 2007-06-15 2008-12-18 Ngk Spark Plug Co., Ltd. Wiring substrate with reinforcing member
JP5179787B2 (ja) 2007-06-22 2013-04-10 ラピスセミコンダクタ株式会社 半導体装置及びその製造方法
US7944034B2 (en) 2007-06-22 2011-05-17 Texas Instruments Incorporated Array molded package-on-package having redistribution lines
US7911805B2 (en) 2007-06-29 2011-03-22 Tessera, Inc. Multilayer wiring element having pin interface
SG148901A1 (en) 2007-07-09 2009-01-29 Micron Technology Inc Packaged semiconductor assemblies and methods for manufacturing such assemblies
KR20090007120A (ko) 2007-07-13 2009-01-16 삼성전자주식회사 봉지부를 통하여 재배선을 달성하는 웨이퍼 레벨 적층형패키지 및 그 제조방법
US7781877B2 (en) 2007-08-07 2010-08-24 Micron Technology, Inc. Packaged integrated circuit devices with through-body conductive vias, and methods of making same
JP2009044110A (ja) 2007-08-13 2009-02-26 Elpida Memory Inc 半導体装置及びその製造方法
SG150396A1 (en) 2007-08-16 2009-03-30 Micron Technology Inc Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods
US8039960B2 (en) 2007-09-21 2011-10-18 Stats Chippac, Ltd. Solder bump with inner core pillar in semiconductor package
US8558379B2 (en) 2007-09-28 2013-10-15 Tessera, Inc. Flip chip interconnection with double post
JP2009088254A (ja) 2007-09-28 2009-04-23 Toshiba Corp 電子部品パッケージ及び電子部品パッケージの製造方法
KR20090033605A (ko) 2007-10-01 2009-04-06 삼성전자주식회사 적층형 반도체 패키지, 그 형성방법 및 이를 구비하는전자장치
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
US20090091009A1 (en) 2007-10-03 2009-04-09 Corisis David J Stackable integrated circuit package
US8008183B2 (en) 2007-10-04 2011-08-30 Texas Instruments Incorporated Dual capillary IC wirebonding
US7834464B2 (en) 2007-10-09 2010-11-16 Infineon Technologies Ag Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device
TWI360207B (en) 2007-10-22 2012-03-11 Advanced Semiconductor Eng Chip package structure and method of manufacturing
TWI389220B (zh) 2007-10-22 2013-03-11 矽品精密工業股份有限公司 半導體封裝件及其製法
JP2009123863A (ja) 2007-11-14 2009-06-04 Tessera Interconnect Materials Inc バンプ構造形成方法及びバンプ構造
US20090127686A1 (en) 2007-11-21 2009-05-21 Advanced Chip Engineering Technology Inc. Stacking die package structure for semiconductor devices and method of the same
KR100886100B1 (ko) 2007-11-29 2009-02-27 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
JP2009135398A (ja) 2007-11-29 2009-06-18 Ibiden Co Ltd 組合せ基板
US7902644B2 (en) 2007-12-07 2011-03-08 Stats Chippac Ltd. Integrated circuit package system for electromagnetic isolation
US7964956B1 (en) 2007-12-10 2011-06-21 Oracle America, Inc. Circuit packaging and connectivity
US8390117B2 (en) 2007-12-11 2013-03-05 Panasonic Corporation Semiconductor device and method of manufacturing the same
JP2009158593A (ja) 2007-12-25 2009-07-16 Tessera Interconnect Materials Inc バンプ構造およびその製造方法
US20090170241A1 (en) 2007-12-26 2009-07-02 Stats Chippac, Ltd. Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
WO2009096950A1 (en) 2008-01-30 2009-08-06 Kulicke And Soffa Industries, Inc. Wire loop and method of forming the wire loop
US8120186B2 (en) 2008-02-15 2012-02-21 Qimonda Ag Integrated circuit and method
US8258015B2 (en) 2008-02-22 2012-09-04 Stats Chippac Ltd. Integrated circuit package system with penetrable film adhesive
US7956456B2 (en) 2008-02-27 2011-06-07 Texas Instruments Incorporated Thermal interface material design for enhanced thermal performance and improved package structural integrity
US7919871B2 (en) 2008-03-21 2011-04-05 Stats Chippac Ltd. Integrated circuit package system for stackable devices
KR101501739B1 (ko) 2008-03-21 2015-03-11 삼성전자주식회사 반도체 패키지 제조 방법
JP5043743B2 (ja) 2008-04-18 2012-10-10 ラピスセミコンダクタ株式会社 半導体装置の製造方法
KR20090123680A (ko) 2008-05-28 2009-12-02 주식회사 하이닉스반도체 적층 반도체 패키지
US8021907B2 (en) 2008-06-09 2011-09-20 Stats Chippac, Ltd. Method and apparatus for thermally enhanced semiconductor package
US7932170B1 (en) 2008-06-23 2011-04-26 Amkor Technology, Inc. Flip chip bump structure and fabrication method
US7859033B2 (en) 2008-07-09 2010-12-28 Eastman Kodak Company Wafer level processing for backside illuminated sensors
JP5339800B2 (ja) 2008-07-10 2013-11-13 三菱電機株式会社 半導体装置の製造方法
TWI372453B (en) 2008-09-01 2012-09-11 Advanced Semiconductor Eng Copper bonding wire, wire bonding structure and method for processing and bonding a wire
US8384203B2 (en) 2008-07-18 2013-02-26 United Test And Assembly Center Ltd. Packaging structural member
US8004093B2 (en) 2008-08-01 2011-08-23 Stats Chippac Ltd. Integrated circuit package stacking system
US20100044860A1 (en) 2008-08-21 2010-02-25 Tessera Interconnect Materials, Inc. Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer
KR100997793B1 (ko) 2008-09-01 2010-12-02 주식회사 하이닉스반도체 반도체 패키지 및 이의 제조 방법
KR20100033012A (ko) 2008-09-19 2010-03-29 주식회사 하이닉스반도체 반도체 패키지 및 이를 갖는 적층 반도체 패키지
US7842541B1 (en) 2008-09-24 2010-11-30 Amkor Technology, Inc. Ultra thin package and fabrication method
US8063475B2 (en) 2008-09-26 2011-11-22 Stats Chippac Ltd. Semiconductor package system with through silicon via interposer
JPWO2010041630A1 (ja) 2008-10-10 2012-03-08 日本電気株式会社 半導体装置及びその製造方法
JP5185062B2 (ja) 2008-10-21 2013-04-17 パナソニック株式会社 積層型半導体装置及び電子機器
MY149251A (en) 2008-10-23 2013-07-31 Carsem M Sdn Bhd Wafer-level package using stud bump coated with solder
KR101461630B1 (ko) 2008-11-06 2014-11-20 삼성전자주식회사 실장 높이는 축소되나, 솔더 접합 신뢰도는 개선되는 웨이퍼 레벨 칩 온 칩 패키지와, 패키지 온 패키지 및 그 제조방법
TW201023308A (en) 2008-12-01 2010-06-16 Advanced Semiconductor Eng Package-on-package device, semiconductor package and method for manufacturing the same
KR101011863B1 (ko) 2008-12-02 2011-01-31 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
US7642128B1 (en) 2008-12-12 2010-01-05 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US7898083B2 (en) 2008-12-17 2011-03-01 Texas Instruments Incorporated Method for low stress flip-chip assembly of fine-pitch semiconductor devices
US8012797B2 (en) 2009-01-07 2011-09-06 Advanced Semiconductor Engineering, Inc. Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries
JP2010199528A (ja) 2009-01-27 2010-09-09 Tatsuta System Electronics Kk ボンディングワイヤ
JP2010177597A (ja) 2009-01-30 2010-08-12 Sanyo Electric Co Ltd 半導体モジュールおよび携帯機器
US20100200981A1 (en) 2009-02-09 2010-08-12 Advanced Semiconductor Engineering, Inc. Semiconductor package and method of manufacturing the same
US9142586B2 (en) 2009-02-24 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for backside illuminated image sensor
JP2010206007A (ja) 2009-03-04 2010-09-16 Nec Corp 半導体装置及びその製造方法
JP5471605B2 (ja) 2009-03-04 2014-04-16 日本電気株式会社 半導体装置及びその製造方法
US8106498B2 (en) 2009-03-05 2012-01-31 Stats Chippac Ltd. Integrated circuit packaging system with a dual board-on-chip structure and method of manufacture thereof
US8258010B2 (en) 2009-03-17 2012-09-04 Stats Chippac, Ltd. Making a semiconductor device having conductive through organic vias
US20100244276A1 (en) 2009-03-25 2010-09-30 Lsi Corporation Three-dimensional electronics package
US8194411B2 (en) 2009-03-31 2012-06-05 Hong Kong Applied Science and Technology Research Institute Co. Ltd Electronic package with stacked modules with channels passing through metal layers of the modules
US20100289142A1 (en) 2009-05-15 2010-11-18 Il Kwon Shim Integrated circuit packaging system with coin bonded interconnects and method of manufacture thereof
US8020290B2 (en) 2009-06-14 2011-09-20 Jayna Sheats Processes for IC fabrication
TWI379367B (en) 2009-06-15 2012-12-11 Kun Yuan Technology Co Ltd Chip packaging method and structure thereof
US20100327419A1 (en) 2009-06-26 2010-12-30 Sriram Muthukumar Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
JP5214554B2 (ja) 2009-07-30 2013-06-19 ラピスセミコンダクタ株式会社 半導体チップ内蔵パッケージ及びその製造方法、並びに、パッケージ・オン・パッケージ型半導体装置及びその製造方法
US7923304B2 (en) 2009-09-10 2011-04-12 Stats Chippac Ltd. Integrated circuit packaging system with conductive pillars and method of manufacture thereof
US8264091B2 (en) 2009-09-21 2012-09-11 Stats Chippac Ltd. Integrated circuit packaging system with encapsulated via and method of manufacture thereof
US8390108B2 (en) 2009-12-16 2013-03-05 Stats Chippac Ltd. Integrated circuit packaging system with stacking interconnect and method of manufacture thereof
US8169065B2 (en) 2009-12-22 2012-05-01 Epic Technologies, Inc. Stackable circuit structures and methods of fabrication thereof
TWI392066B (zh) 2009-12-28 2013-04-01 矽品精密工業股份有限公司 封裝結構及其製法
US7928552B1 (en) 2010-03-12 2011-04-19 Stats Chippac Ltd. Integrated circuit packaging system with multi-tier conductive interconnects and method of manufacture thereof
US9496152B2 (en) 2010-03-12 2016-11-15 STATS ChipPAC Pte. Ltd. Carrier system with multi-tier conductive posts and method of manufacture thereof
KR101667656B1 (ko) 2010-03-24 2016-10-20 삼성전자주식회사 패키지-온-패키지 형성방법
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8278746B2 (en) 2010-04-02 2012-10-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including connecting elements
US8564141B2 (en) 2010-05-06 2013-10-22 SK Hynix Inc. Chip unit and stack package having the same
US8217502B2 (en) 2010-06-08 2012-07-10 Stats Chippac Ltd. Integrated circuit packaging system with multipart conductive pillars and method of manufacture thereof
US8330272B2 (en) 2010-07-08 2012-12-11 Tessera, Inc. Microelectronic packages with dual or multiple-etched flip-chip connectors
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
KR101683814B1 (ko) 2010-07-26 2016-12-08 삼성전자주식회사 관통 전극을 구비하는 반도체 장치
US8580607B2 (en) 2010-07-27 2013-11-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
US8304900B2 (en) 2010-08-11 2012-11-06 Stats Chippac Ltd. Integrated circuit packaging system with stacked lead and method of manufacture thereof
US8518746B2 (en) 2010-09-02 2013-08-27 Stats Chippac, Ltd. Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die
US20120063090A1 (en) 2010-09-09 2012-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Cooling mechanism for stacked die package and method of manufacturing the same
US8409922B2 (en) 2010-09-14 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect
US20120080787A1 (en) 2010-10-05 2012-04-05 Qualcomm Incorporated Electronic Package and Method of Making an Electronic Package
US8618646B2 (en) 2010-10-12 2013-12-31 Headway Technologies, Inc. Layered chip package and method of manufacturing same
JP2012104790A (ja) 2010-10-12 2012-05-31 Elpida Memory Inc 半導体装置
US8697492B2 (en) 2010-11-02 2014-04-15 Tessera, Inc. No flow underfill
US8525318B1 (en) * 2010-11-10 2013-09-03 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
KR101075241B1 (ko) 2010-11-15 2011-11-01 테세라, 인코포레이티드 유전체 부재에 단자를 구비하는 마이크로전자 패키지
US8502387B2 (en) 2010-12-09 2013-08-06 Stats Chippac Ltd. Integrated circuit packaging system with vertical interconnection and method of manufacture thereof
US8853558B2 (en) 2010-12-10 2014-10-07 Tessera, Inc. Interconnect structure
KR101215271B1 (ko) 2010-12-29 2012-12-26 앰코 테크놀로지 코리아 주식회사 반도체 패키지 구조물 및 반도체 패키지 구조물의 제조 방법
US20120184116A1 (en) 2011-01-18 2012-07-19 Tyco Electronics Corporation Interposer
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US8476115B2 (en) 2011-05-03 2013-07-02 Stats Chippac, Ltd. Semiconductor device and method of mounting cover to semiconductor die and interposer with adhesive material
US8487421B2 (en) 2011-08-01 2013-07-16 Tessera, Inc. Microelectronic package with stacked microelectronic elements and method for manufacture thereof
US20130037929A1 (en) 2011-08-09 2013-02-14 Kay S. Essig Stackable wafer level packages and related methods
KR101800440B1 (ko) 2011-08-31 2017-11-23 삼성전자주식회사 다수의 반도체 칩들을 가진 반도체 패키지 및 그 형성 방법
US20130049218A1 (en) 2011-08-31 2013-02-28 Zhiwei Gong Semiconductor device packaging having pre-encapsulation through via formation
US9177832B2 (en) 2011-09-16 2015-11-03 Stats Chippac, Ltd. Semiconductor device and method of forming a reconfigured stackable wafer level package with vertical interconnect
KR101906408B1 (ko) 2011-10-04 2018-10-11 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US9105483B2 (en) 2011-10-17 2015-08-11 Invensas Corporation Package-on-package assembly with wire bond vias
US9105552B2 (en) 2011-10-31 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
KR101297015B1 (ko) 2011-11-03 2013-08-14 주식회사 네패스 리드프레임을 이용한 팬-아웃 반도체 패키지 제조방법, 이에 의한 반도체 패키지 및 패키지 온 패키지
US8912651B2 (en) 2011-11-30 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) structure including stud bulbs and method
US8680684B2 (en) 2012-01-09 2014-03-25 Invensas Corporation Stackable microelectronic package structures
US9258922B2 (en) 2012-01-18 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. PoP structures including through-assembly via modules
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US20130234317A1 (en) 2012-03-09 2013-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging Methods and Packaged Semiconductor Devices
US9082763B2 (en) 2012-03-15 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Joint structure for substrates and methods of forming
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9171790B2 (en) 2012-05-30 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US8828860B2 (en) 2012-08-30 2014-09-09 International Business Machines Corporation Double solder bumps on substrates for low temperature flip chip bonding
KR101419597B1 (ko) 2012-11-06 2014-07-14 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101101898A (zh) * 2006-07-06 2008-01-09 三星电机株式会社 层叠封装的底部衬底及其制造方法
CN101286484A (zh) * 2007-04-13 2008-10-15 日本电气株式会社 半导体器件和制造方法
US20120015481A1 (en) * 2010-07-15 2012-01-19 Woo-Jae Kim Method of manufacturing stack type semiconductor package
US20120280386A1 (en) * 2011-05-03 2012-11-08 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105575832A (zh) * 2015-12-22 2016-05-11 华进半导体封装先导技术研发中心有限公司 一种多层堆叠扇出型封装结构及制备方法
CN106898557A (zh) * 2017-03-03 2017-06-27 中芯长电半导体（江阴）有限公司 集成有供电传输系统的封装件的封装方法
CN106898557B (zh) * 2017-03-03 2019-06-18 中芯长电半导体（江阴）有限公司 集成有供电传输系统的封装件的封装方法

Also Published As

Publication number Publication date
JP2016506078A (ja) 2016-02-25
TWI635580B (zh) 2018-09-11
WO2014107301A1 (en) 2014-07-10
US20150034371A1 (en) 2015-02-05
JP6484179B2 (ja) 2019-03-13
EP2936557A1 (en) 2015-10-28
US20140175671A1 (en) 2014-06-26
TW201426921A (zh) 2014-07-01
US20150334831A1 (en) 2015-11-19
US9615456B2 (en) 2017-04-04
TWI555138B (zh) 2016-10-21
US9095074B2 (en) 2015-07-28
US8878353B2 (en) 2014-11-04
KR20150097669A (ko) 2015-08-26
TW201701416A (zh) 2017-01-01

Similar Documents

Publication Publication Date Title
CN104995732A (zh) 用于具有封装键合元件的微电子封装的结构
US10468380B2 (en) Stackable microelectronic package structures
US8399297B2 (en) Methods of forming and assembling pre-encapsulated assemblies and of forming associated semiconductor device packages
EP2537182B1 (en) Microelectronic package with terminals on dielectric mass
US8053349B2 (en) BGA package with traces for plating pads under the chip
US9087815B2 (en) Off substrate kinking of bond wire
KR20130086347A (ko) 영역 어레이 유닛 컨넥터를 갖는 적층 가능한 몰딩된 마이크로전자 패키지
JP2009506571A (ja) インターポーザー基板に接続するための中間コンタクトを有するマイクロ電子デバイスおよびそれに関連する中間コンタクトを備えたマイクロ電子デバイスをパッケージする方法
US6992395B2 (en) Semiconductor device and semiconductor module having external electrodes on an outer periphery
US10332854B2 (en) Anchoring structure of fine pitch bva
CN105097759A (zh) 封装堆栈结构及其制法暨无核心层式封装基板及其制法
WO2015073409A1 (en) Off substrate kinking of bond wire
KR20150092876A (ko) 전자 소자 모듈 및 그 제조 방법
US8354744B2 (en) Stacked semiconductor package having reduced height
US6803666B2 (en) Semiconductor chip mounting substrate and semiconductor device using the same
CN219226269U (zh) 电子器件
US8975738B2 (en) Structure for microelectronic packaging with terminals on dielectric mass
CN105556662A (zh) 具有由延伸经过囊封件的连接器耦接的堆叠端子的微电子组件
CN115084080A (zh) ToF光感模组扇出封装结构、制备方法及可穿戴电子设备
CN116190342A (zh) 半导体封装
CN115939076A (zh) 半导体结构及其形成方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20151021

RJ01 Rejection of invention patent application after publication