CN104701270A - Semiconductor packaging structure and semiconductor process - Google Patents
Semiconductor packaging structure and semiconductor process Download PDFInfo
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- CN104701270A CN104701270A CN201310645713.9A CN201310645713A CN104701270A CN 104701270 A CN104701270 A CN 104701270A CN 201310645713 A CN201310645713 A CN 201310645713A CN 104701270 A CN104701270 A CN 104701270A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1705—Shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention relates to a semiconductor packaging structure and a semiconductor process. The semiconductor packaging structure comprises a first substrate, a second substrate, a grain, a plurality of internal connecting elements, and a coating material. The internal connecting elements are connected with the first substrate and the second substrate. Each of the internal connecting elements comprises an upper part and a lower part, wherein the upper part and the lower part are jointed to form a joint part, and the lower part has a shoulder which surrounds the joint part. The coating material coats the internal connecting elements. Therefore, warpage of the second substrate during reflow soldering is avoided, and the peeling-off problem of the first substrate and the second substrate is solved.
Description
Technical field
The invention relates to a kind of semiconductor package and semiconductor technology.In detail, the invention relates to one and stack semiconductor package and semiconductor technology thereof.
Background technology
The known manufacture method stacking semiconductor package is as follows, first, a crystal grain and several soldered ball (SolderBall) is engaged on the upper surface of an infrabasal plate.Then, envelope mold technique (Molding Process) is utilized to form an adhesive material on the upper surface of this infrabasal plate, with this crystal grain coated and these soldered balls.Then, after solidifying this adhesive material, high-temperature laser is utilized to form several opening to appear the top of these soldered balls in this adhesive material upper surface.Then, put a upper substrate on this adhesive material, make these soldered balls of solder contact being positioned at this upper substrate lower surface.Then, carry out first time heating with a heating oven, make this solder and these soldered ball meltings and form interior Connection Element.Then, after the lower surface of this infrabasal plate forms several soldered ball, reflow process is carried out.Finally carry out cutting step again.
In this known manufacturing methods, in the process moving to this heating oven, upper substrate lower surface only contacts with this adhesive material and without engaging force, and this solder and these soldered balls also only contact and without engaging force, therefore, upper substrate and this adhesive material can offset (Shift).In addition, after first time heating, only have the solder of this upper substrate to engage each other with the soldered ball of infrabasal plate, but upper substrate lower surface and this adhesive material still only contact and without engaging force.Therefore, after reflow, easily there is warpage (Warpage) in upper substrate, and even this upper substrate and this infrabasal plate can be peeled off (Peeling off), affect product yield.
In order to improve the problems referred to above, a kind of new solution is suggested.This solution first utilizes these soldered balls to engage upper and lower base plate, carries out envelope mold technique more afterwards, to form an adhesive material between this upper and lower base plate.But, in the envelope mold technique of this kind of mode, this adhesive material injects between this upper and lower base plate by side, therefore, these soldered balls can affect the flowing of this adhesive material, make the skewness of the particle filled composite in this adhesive material, and can successfully pass through between this crystal grain and this upper substrate to allow this adhesive material due to the mode of this technique, therefore these solder balls maintain certain height, make the size of these soldered balls comparatively large, the spacing of these soldered balls cannot effectively be reduced.
Summary of the invention
The one side of this exposure is about a kind of semiconductor package.In one embodiment, this semiconductor package comprises a first substrate, a second substrate, a crystal grain, several interior Connection Element and a clad material.This first substrate has conductive pad on a upper surface and several first substrate.This second substrate has conductive pad under a lower surface and several second substrate, and wherein the upper surface of this first substrate is the lower surface in the face of this second substrate.This crystal grain is electrically connected to the upper surface of this first substrate.In these, Connection Element to connect on these first substrates conductive pad under conductive pad and these second substrates, this interior Connection Element comprises a top and a bottom, this top is electrically connected conductive pad under these second substrates, this bottom is electrically connected conductive pad on these first substrates, wherein this bottom of upper bond is to form a junction surface, this bottom has a shoulder, and this shoulder is around this junction surface.This clad material is between the upper surface of this first substrate and the lower surface of this second substrate, and this crystal grain coated and Connection Element in these.
The another aspect of this exposure is about a kind of semiconductor technology.In one embodiment, this semiconductor technology comprises the following steps: (a) forms several first conductive part on the first substrate of a first substrate on conductive pad, wherein this first substrate has more a upper surface, and on these first substrates, conductive pad is the upper surface being revealed in this first substrate; B () leveling (Leveling) these first conductive parts, make each these first conductive part have an end face, and these end faces are copline; C one crystal grain is electrically connected to a upper surface of a first substrate by (), wherein this first substrate has more conductive pad on several first substrate, is revealed in the upper surface of this first substrate; D () applies the upper surface of a clad material in this first substrate with this crystal grain coated and these the first conductive parts, wherein this clad material is B-stage (B-stage) glue material; E () forms several this clad material that is opened on to appear these end faces of these the first conductive parts; F () pressing one second substrate is on this clad material, a lower surface of this second substrate is made to attach on this clad material, wherein this second substrate has more conductive pad and several second conductive part under several second substrate, under this second substrate, conductive pad is the lower surface being revealed in this second substrate, these second conductive parts are positioned under these second substrates on conductive pad, and these second conductive parts contact these end faces of these the first conductive parts; And (g) carries out a heating steps, make these second conductive parts and these the first conductive part meltings and form several interior Connection Element, and this clad material is solidified into the C stage.
In the present embodiment, the lower surface due to this second substrate attaches to this clad material, and therefore, in the moving process of whole encapsulating structure, this second substrate and this clad material can not offset.In addition, when reflow, can not there is warpage in this second substrate, and solve the problem of this first and second strippable substrate, and can improve product yield.
Accompanying drawing explanation
Fig. 1 shows the cross-sectional schematic of an embodiment of semiconductor package of the present invention.
Fig. 2 shows the enlarged diagram of the region A of Fig. 1.
Fig. 2 A shows the enlarged diagram of another embodiment of Connection Element in these.
Fig. 3 to Figure 11 shows the schematic diagram of an embodiment of semiconductor technology of the present invention.
Figure 12 shows the cross-sectional schematic of another embodiment of semiconductor package of the present invention.
Figure 13 shows the enlarged diagram of the region B of Figure 12.
Figure 14 shows the cross-sectional schematic of another embodiment of semiconductor package of the present invention.
Embodiment
With reference to figure 1, show the cross-sectional schematic of an embodiment of semiconductor package of the present invention.This semiconductor package 1 comprises first substrate 10, second substrate 12, crystal grain 14, several interior Connection Element 16, clad materials 18 and several lower soldered ball 20.
This first substrate 10 to have on a upper surface 101, a lower surface 102, several first substrate conductive pad 104 under conductive pad 103 and several first substrate.In the present embodiment, this first substrate 10 is a base plate for packaging, and under these first substrates, conductive pad 104 is revealed in the lower surface 102 of this first substrate 10, and on these first substrates, conductive pad 103 is revealed in the upper surface 101 of this first substrate 10.Under these first substrates, conductive pad 104 is electrically connected to conductive pad 103 on these first substrates.
This second substrate 12 to have on a upper surface 121, a lower surface 122, several second substrate conductive pad 124 under conductive pad 123 and several second substrate.The upper surface 101 of this first substrate 10 is the lower surfaces 122 in the face of this second substrate 12.In the present embodiment, this second substrate 12 is a base plate for packaging or an intermediate plate (Interposer), on these second substrates, conductive pad 123 is revealed in the upper surface 121 of this second substrate 12, and under these second substrates, conductive pad 124 is revealed in the lower surface 122 of this second substrate 12.On these second substrates, conductive pad 123 is electrically connected to conductive pad 124 under these second substrates.
This crystal grain 14 is the upper surfaces 101 being electrically connected to this first substrate 10.In the present embodiment, this crystal grain 14 is the upper surfaces 101 being attached to this first substrate 10 in chip bonding mode, that is this crystal grain 14 is the upper surfaces 101 utilizing its active surface to be electrically connected to this first substrate 10, and its back side is upward.In these, Connection Element 16 to connect on these first substrates conductive pad 124 under conductive pad 103 and these second substrates.In the present embodiment, in each these, Connection Element 16 becomes top 161 and a bottom 162 respectively after being melted mutually by one first conductive part (such as: soldered ball (Solder Ball)) and one second conductive part (such as: pre-welding material (Pre-solder)), and wherein this bottom 162 has a shoulder 1621.In these, Connection Element 16 is mainly in order to be electrically connected on these first substrates conductive pad 124 under conductive pad 103 and these second substrates.
On this first substrate of the present invention under conductive pad 103 and this first substrate on conductive pad 104 or this second substrate under conductive pad 123 and this second substrate conductive pad 124 conductive trace (Trace) (not shown) can be utilized as the technical approach be electrically connected, under above-mentioned second substrate, conductive pad 124 optionally with this conductive trace copline (coplanar) or can protrude (projecting) on this conductive trace.
This clad material 18 is between the upper surface 101 of this first substrate 10 and the lower surface 122 of this second substrate 12, and this crystal grain 14 coated and Connection Element 16 in these.This clad material 18 sticks the upper surface 101 of this first substrate 10 and the lower surface 122 of this second substrate 12 respectively, and the adhesive force between the upper surface 101 of this clad material 18 and this first substrate 10 be approximately identical to this clad material 18 and this second substrate 12 lower surface 122 between adhesive force.In the present embodiment, this clad material 18 is non-conductive film (Non Conductive Film, NCF), non-conductive adhesive (Non Conductive Paste, NCP) or ABF(Ajinomoto Build-up Film).When this clad material 18 is in the state of B-stage (B-stage) glue material, namely bind the upper surface 101 of this first substrate 10 and the lower surface 122 of this second substrate 12.Lower surface 122 due to this second substrate 12 attaches to this clad material 18, and therefore, in the moving process of whole encapsulating structure, this second substrate 12 can not offset with this clad material 18.In addition, after the heating, this clad material 18 solidifies and is in the state of C stage (C-stage), adhesive force between the upper surface 101 of itself and this first substrate 10 is approximately identical to the adhesive force between the lower surface 122 of itself and this second substrate 12, add the conjugation of Connection Element 16 in these, therefore, when reflow, can not be there is warpage (Warpage) in this second substrate 12, and can improve product yield.
In the present embodiment, this clad material 18 has several holding tank 181 to hold Connection Element 16 in these, the shape of the sidewall of these holding tanks 181 conforms to completely with Connection Element in these 16, and outer surface of Connection Element 16 contacts the sidewall of these holding tanks 181 completely in these, that is the shape of these holding tanks 181 defined by Connection Element in these 16.In other words, in these Connection Element 16 and these holding tanks 181 sidewall between exist without any space.Therefore, in these, Connection Element 16 and this clad material 18 are combined closely.
In addition, this clad material 18 has more several particle filled composite (Fillers) 182, and these particle filled composites 182 have the particle diameter varied in size, and is uniformly distributed in this clad material 18, and can not be positioned at these Connection Elements 16.Meanwhile, the density of these particle filled composites 182 is also even in this clad material 18.It should be noted that, in process, equally distributed particle filled composite 182 can be beneficial to the hole uniformity of carrying out laser drill on this clad material 18, and then improves the uniformity of Connection Element 16 in these, improves the reliability (Reliability) of this semiconductor package 1.
Moreover these particle filled composites 182 through the flow process of die channel (Molding Channel), therefore must can not reduce the integral thickness of this clad material 18, particularly the thickness of this clad material 18 between this second substrate 12 and this crystal grain 14.In one embodiment, the thickness of this clad material 18 between this second substrate 12 and this crystal grain 14 can be not more than maximum particle diameter size in these particle filled composites 182; In another embodiment, the thickness of this clad material 18 between this second substrate 12 and this crystal grain 14 is for being less than 20 microns (μm).
For example, region A in figure
1and region A
2represent the clad material 18 in left side and the clad material 18 on right side respectively, wherein region A
1for the limit, the leftmost side of this clad material 18 extends a predeterminable range to the right, this predeterminable range is 10% of this clad material 18 Breadth Maximum, and region A
2for the limit, the rightmost side of this clad material 18 extends this predeterminable range left.Be positioned at region A
1and region A
2the domain size distribution of particle filled composite 182 and density identical.In actual experiment, be difference acquisition area A
1and region A
2in arbitrary zonule amplify, respectively get wherein 100 particle filled composites and compare, region A can be found
1in 100 particle filled composites and region A
2in 100 particle filled composites, the domain size distribution of the two and density are that essence is identical.
These time soldered balls 20 are under being positioned at these first substrates on conductive pad 104, in order to be electrically connected to an outer member.
With reference to figure 2, the enlarged diagram of the region A of display Fig. 1.In the present embodiment, this interior Connection Element 16 comprises top 161 and a bottom 162.This top 161 is electrically connected conductive pad 124 under these second substrates, and this bottom 162 is electrically connected conductive pad 103 on these first substrates, and wherein the volume of this bottom 162 is greater than the volume on this top 161.This top 161 engages this bottom 162 to form a junction surface 163.This bottom 162 has shoulder 1621, end face 1622 and a peripheral surface 1623.This shoulder 1621 is the junctions being positioned at this end face 1622 and this peripheral surface 1623, and this shoulder 1621 is around this junction surface 163.In the present embodiment, this end face 1622 is plane, and this peripheral surface 1623 is cambered surface, and wherein this end face 1622 is conductive pads 103 on this first substrate parallel.This junction surface 163 is and this end face 1622 copline, and this end face 1622 is around this junction surface 163.
The region that this bottom 162 contacts with conductive pad 103 on this first substrate has one first width W
1, and the region that this top 161 contacts with conductive pad 124 under this second substrate has one second width W
2.This bottom itself has a Breadth Maximum W
m, this end face 1622 has one the 3rd width W
3, this junction surface 163 has one the 4th width W
4, wherein this Breadth Maximum W
mbe greater than this first width W
1, this second width W
2and the 3rd width W
3, and the 3rd width W
3be greater than the 4th width W
4.
This first width W
1approximate greatly the 4th width W
4.In the present embodiment, due to Connection Element 16 in each these be melted mutually by the first conductive part (such as: soldered ball (Solder Ball)) and one second conductive part (such as: pre-welding material (Pre-solder)) after become this top 161 and this bottom 162 respectively, therefore, the Breadth Maximum W of Connection Element 16 in these
meffectively can reduce, the spacing of Connection Element 16 in these effectively can be reduced, and be applicable to thin space (Fine Pitch) circuit.
The distance of the back side of this crystal grain 14 and the upper surface 101 of this first substrate 10 is the first height h
1, this shoulder 1621(or this end face 1622) and be the second height h with the distance of the upper surface 101 of this first substrate 10
2, this shoulder 1621(or this end face 1622) and be third high degree h with the distance of the lower surface 122 of this second substrate 12
3, wherein h
1> h
2, and h
2+ h
3> h
1.
With reference to figure 2A, show the enlarged diagram of another embodiment of Connection Element in these.In the present embodiment, due to Connection Element 16 in each these be melted mutually by the first conductive part (such as: soldered ball (Solder Ball)) after flattening and one second conductive part (such as: pre-welding material (Pre-solder)) after become this top 161 and this bottom 162 respectively.Because this first conductive part 15 flattens in advance to form smooth end face 151(Fig. 4), and increase the area that can contact, therefore, even if having a skew S between this second conductive part and this first conductive part, this second conductive part still can touch this end face 151, and this top 161 and this bottom 162 connection to each other can be guaranteed, to improve yield.
With reference to figure 3 to Figure 11, show the schematic diagram of an embodiment of semiconductor technology of the present invention.With reference to figure 3, provide this first substrate 10.This first substrate 10 to have on a upper surface 101, a lower surface 102, several first substrate conductive pad 104 under conductive pad 103 and several first substrate.In the present embodiment, this first substrate 10 is a base plate for packaging, and under these first substrates, conductive pad 104 is revealed in the lower surface 102 of this first substrate 10, and on these first substrates, conductive pad 103 is revealed in the upper surface 101 of this first substrate 10.Under these first substrates, conductive pad 104 is electrically connected to conductive pad 103 on these first substrates.
Then, several first conductive parts 15 conductive pad 103 on these first substrates is formed.In the present embodiment, these first conductive parts 15 are several soldered ball, and it is spherical, and has Radius R.
With reference to figure 4, leveling (Leveling) these first conductive parts 15, make each these first conductive part 15 have an end face 151, and these end faces 151 are copline.In the present embodiment, be after being first heated to about 170 DEG C, recycle a mould and flatten these the first conductive parts 15.This first conductive part 15 after leveling has one second height h
2, wherein R < h
2< 2R, and this end face has Breadth Maximum W, wherein a W<2.2R.This Breadth Maximum W equals the 3rd width W in final encapsulating structure haply
3(Fig. 2).
Second height h of these the first conductive parts 15 after leveling
2almost identical, its tolerance can be reduced, reduce the degree of difficulty that in subsequent technique, this second substrate 12 engages.Moreover the similarity of the outward appearance of these the first conductive parts 15 after leveling is quite high, as the anchor point of other techniques, the selection in more Alternative design thus can be provided.In addition, these first conductive parts 15 after leveling also can reduce the thickness of overall package structure.
With reference to figure 5, this crystal grain 14 is electrically connected to the upper surface 101 of this first substrate 10.In the present embodiment, this crystal grain 14 is the upper surfaces 101 being attached to this first substrate 10 in chip bonding mode.That is this crystal grain 14 is the upper surfaces 101 utilizing its active surface to be electrically connected to this first substrate 10, and its back side is upward.The distance of the back side of this crystal grain 14 and the upper surface 101 of this first substrate 10 is the first height h
1, this end face 151 and the distance of the upper surface 101 of this first substrate 10 are the second height h
2, wherein h
1> h
2.
With reference to figure 6, provide this clad material 18.In the present embodiment, this clad material 18 is non-conductive film (NonConductive Film, NCF), non-conductive adhesive (Non Conductive Paste, NCP) or ABF(AjinomotoBuild-up Film), and it has several particle filled composite (Fillers) 182.These particle filled composites 182 have the particle diameter varied in size, and are uniformly distributed in this clad material 18.Now, this clad material 18 is in the state of B-stage (B-stage) glue material.
With reference to figure 7, apply the upper surface 101 of this clad material 18 in this first substrate 10 with this crystal grain 14 coated and these the first conductive parts 15.Now this clad material 18 is still in the state of B-stage.In the present embodiment, this clad material 18 is the upper surfaces 101 utilizing the mode such as pressing or printing to be formed at this first substrate 10 from top to bottom or from bottom to top, therefore, these first conductive parts 15 can not affect the flowing of the particle filled composite 182 in this clad material 18, and these particle filled composites 182 must, through the flow process of die channel (Molding Channel), not make these particle filled composites 182 still be uniformly distributed in this clad material 18.
With reference to figure 8, form several opening 183 on this clad material 18 to appear the end face 151 of these the first conductive parts 15.In the present embodiment, be utilize low temperature laser to form these openings 183.Now, this clad material 18 is still in the state of B-stage.
With reference to figure 9, provide this second substrate 12.This second substrate 12 to have on a upper surface 121, a lower surface 122, several second substrate conductive pad 124 and several second conductive part 125 under conductive pad 123, several second substrate.The lower surface 122 of this second substrate 12 is the upper surfaces 101 in the face of this first substrate 10.In the present embodiment, this second substrate 12 is a base plate for packaging or an intermediate plate (Interposer), on these second substrates, conductive pad 123 is revealed in the upper surface 121 of this second substrate 12, and under these second substrates, conductive pad 124 is revealed in the lower surface 122 of this second substrate 12.On these second substrates, conductive pad 123 is electrically connected to conductive pad 124 under these second substrates.These second conductive parts 125 to be positioned under these second substrates on conductive pad 124.In the present embodiment, these second conductive parts 125 are several pre-welding material, and its outer surface is a cambered surface.The volume of each the second conductive part 125 is the volumes being less than each the first conductive part 15.
Then, a downforce is applied with this second substrate 12 of pressing on this clad material 18.Because this clad material 18 is still in the state of B-stage, the lower surface 122 of this second substrate 12 can be attached on this clad material 18, and the adhesive force between the upper surface 101 of this clad material 18 and this first substrate 10 be approximately identical to this clad material 18 and this second substrate 12 lower surface 122 between adhesive force.According in an embodiment, apply this downforce and be heated to about 90 DEG C simultaneously, now, this clad material 18 is can flow regime, and can fill up any space.In addition, because this clad material 18 does not need the flowing space, therefore, via the amount and this downforce that control this clad material 18, the thickness of overall package structure can significantly be reduced.
With reference to Figure 10, carry out first time heating with a heating oven, this first conductive part 15 and this second conductive part 125 are melted mutually and engages rear this top 161 and this bottom 162 that become this interior Connection Element 16 respectively.Working temperature is now about 245 DEG C.It should be noted that in the process moving to this heating oven, the lower surface 122 of this second substrate 12 has attached on this clad material 18, and therefore, this second substrate 12 can not offset with this adhesive material 18.In the present embodiment, this first conductive part 15 has smooth end face 151, and the volume of this second conductive part 125 is the volumes being less than this first conductive part 15.Therefore, after melting mutually, this bottom 162 can have a shoulder 1621.Now, this clad material 18 can fill up in the space above this shoulder 1621.That is the shape of these holding tanks 181 in this clad material 18 defined by Connection Element in these 16.
Now, this shoulder 1621 is third high degree h with the distance of the lower surface 122 of this second substrate 12
3, wherein h
2+ h
3> h
1.
After heating a period of time, this clad material 18 is solidified into the C stage.There are these holding tanks 181 to hold Connection Element 16 in these in the clad material 18 of solidification, the shape of the sidewall of these holding tanks 181 conforms to completely with Connection Element in these 16, and in these, outer surface of Connection Element 16 contacts the sidewall of these holding tanks 181 completely.In other words, in these Connection Element 16 and these holding tanks 181 sidewall between exist without any space, and in these, Connection Element 16 and this clad material 18 are combined closely.
With reference to Figure 11, form several lower soldered ball 20 under these first substrates on conductive pad 104.Then, reflow is carried out.It should be noted that now this second substrate 12 close attachment is on this adhesive material 18 and this first substrate 10, therefore after reflow, can not there is warpage in this second substrate 12, can improve product yield by this.Then, cut, to form several semiconductor package as shown in Figure 1.When cutting process, close attachment is on this adhesive material 18 and this first substrate 10 equally for this second substrate 12, and the problem that the stress therefore produced during cutting causes this second substrate 12 to peel off also can not occur.
With reference to Figure 12, show the cross-sectional schematic of another embodiment of semiconductor package of the present invention.With reference to Figure 13, the enlarged diagram of the region B of display Figure 12.Semiconductor package 1 shown in semiconductor package 1a and Fig. 1 of the present embodiment and Fig. 2 is roughly the same, and it does not exist together as described below.In this semiconductor package 1a of the present embodiment, upper surface 101 part of this first substrate 10 covers one first upper dielectric layer 105, and lower surface 102 part of this first substrate 10 covers one first time dielectric layer 106.On these first substrates, conductive pad 103 is revealed in this first upper dielectric layer 105, and under these first substrates, conductive pad 104 is revealed in this first time dielectric layer 106.In addition, upper surface 121 part of second substrate 12 covers one second upper dielectric layer 126, and lower surface 122 part of second substrate 12 covers one second time dielectric layer 127.On these second substrates, conductive pad 123 is revealed in this second upper dielectric layer 126, and under these second substrates, conductive pad 124 is revealed in this second time dielectric layer 127.In the present embodiment, the adhesive force of this first upper dielectric layer 105 and this clad material 18 is approximately identical to the adhesive force between this second time dielectric layer 127 and this clad material 18.
With reference to Figure 14, show the cross-sectional schematic of another embodiment of semiconductor package of the present invention.Semiconductor package 1 shown in semiconductor package 1b and Fig. 1 of the present embodiment and Fig. 2 is roughly the same, and it does not exist together as described below.In this semiconductor package 1b of the present embodiment, the thickness of this clad material 18 between this second substrate 12 lower surface 122 and this crystal grain 14 upper surface 141 is defined as T, and this thickness T is less than or equal to the maximum particle diameter size in these particle filled composites 182.Therefore, this thickness T also can equal 0, makes this second substrate 12 lower surface 122 contact this crystal grain 14 upper surface 141.
Only above-described embodiment is only and principle of the present invention and effect thereof is described, and is not used to limit the present invention.Therefore, the personage practised in this technology modifies to above-described embodiment and changes still de-spirit of the present invention.Interest field of the present invention should listed by claims.
Claims (20)
1. a semiconductor package, is characterized in that, comprising:
One first substrate, has conductive pad on a upper surface and several first substrate;
One second substrate, has conductive pad under a lower surface and several second substrate, and wherein the upper surface of this first substrate is the lower surface in the face of this second substrate;
One crystal grain, is electrically connected to the upper surface of this first substrate;
Several interior Connection Element, to connect on described first substrate conductive pad under conductive pad and described second substrate, this interior Connection Element comprises a top and a bottom, this top is electrically connected conductive pad under described second substrate, this bottom is electrically connected conductive pad on described first substrate, wherein this bottom of this upper bond is to form a junction surface, and this bottom has a shoulder, and this shoulder is around this junction surface; And
One clad material, between the upper surface of this first substrate and the lower surface of this second substrate, and this crystal grain coated and described interior Connection Element.
2. semiconductor package as claimed in claim 1, it is characterized in that, this first substrate has more conductive pad under a lower surface and several first substrate, and under described first substrate, conductive pad is revealed in this first substrate lower surface, and on described first substrate, conductive pad is revealed in this first substrate upper surface; This second substrate has more conductive pad on a upper surface and several second substrate, and on described second substrate, conductive pad is revealed in this second substrate upper surface, and under described second substrate, conductive pad is revealed in this second substrate lower surface.
3. semiconductor package as claimed in claim 1, is characterized in that, in described in each, Connection Element becomes this top and this bottom respectively after being melted mutually by a pre-welding material and a soldered ball.
4. semiconductor package as claimed in claim 1, it is characterized in that, the volume of this bottom is greater than the volume on this top.
5. semiconductor package as claimed in claim 1, it is characterized in that, this bottom has more an end face and a peripheral surface, and this shoulder is the junction being positioned at this end face and this peripheral surface.
6. semiconductor package as claimed in claim 5, it is characterized in that, this end face is plane, and this peripheral surface is cambered surface, and this end face is conductive pad on this first substrate parallel.
7. semiconductor package as claimed in claim 1, it is characterized in that, the distance of one back side of this crystal grain and the upper surface of this first substrate is the first height h1, the distance of the upper surface of this shoulder and this first substrate is the second height h2, the distance of the lower surface of this shoulder and this second substrate is third high degree h3, wherein h1 > h2, and h2+h3 > h1.
8. semiconductor package as claimed in claim 1, it is characterized in that, the region that this bottom contacts with conductive pad on this first substrate has one first width, the region that this top contacts with conductive pad under this second substrate has one second width, this bottom itself has a Breadth Maximum, this bottom has more an end face, this end face has one the 3rd width, this junction surface has one the 4th width, wherein this Breadth Maximum is greater than this first width, this second width and the 3rd width, and the 3rd width is greater than the 4th width.
9. semiconductor package as claimed in claim 1, it is characterized in that, this clad material has several holding tank to hold described interior Connection Element, and the shape of the sidewall of described holding tank conforms to completely with described interior Connection Element, and the sidewall of holding tank described in the exterior surface of described interior Connection Element.
10. semiconductor package as claimed in claim 1, it is characterized in that, this clad material has several holding tank to hold described interior Connection Element, and the shape of described holding tank defined by described interior Connection Element.
11. semiconductor packages as claimed in claim 1, it is characterized in that, this clad material is non-conductive film, non-conductive adhesive or ABF.
12. semiconductor packages as claimed in claim 1, it is characterized in that, this clad material has several particle filled composite, and described particle filled composite is uniformly distributed in this clad material.
13. semiconductor packages as claimed in claim 1, it is characterized in that, this clad material has several particle filled composite, and this clad material comprises an a region A1 and region A2, wherein this region A1 is that the limit, the leftmost side of this clad material extends a predeterminable range to the right, this predeterminable range is 10% of this clad material Breadth Maximum, and the limit, the rightmost side that this region A2 is this clad material extends this predeterminable range left, the domain size distribution and the density that are wherein positioned at the particle filled composite of this region A1 and this region A2 are identical.
14. semiconductor packages as claimed in claim 1, it is characterized in that, this first substrate upper surface portion covers one first dielectric layer, the bottom surface section of second substrate covers one second dielectric layer, and wherein the adhesive force of this first dielectric layer and this clad material is approximately identical to the adhesive force between this second dielectric layer and this clad material.
15. 1 kinds of semiconductor technologies, is characterized in that, comprise the following steps:
A () forms several first conductive part on the first substrate of a first substrate on conductive pad, wherein this first substrate has more a upper surface, and on described first substrate, conductive pad is the upper surface being revealed in this first substrate;
B () flattens described first conductive part, make the first conductive part described in each have an end face, and described end face is copline;
C one crystal grain is electrically connected to a upper surface of a first substrate by (), wherein this first substrate has more conductive pad on several first substrate, is revealed in the upper surface of this first substrate;
D () applies the upper surface of a clad material in this first substrate with this crystal grain coated and described first conductive part, wherein this clad material is B-stage glue material;
E () forms several this clad material that is opened on to appear the described end face of described first conductive part;
F () pressing one second substrate is on this clad material, a lower surface of this second substrate is made to attach on this clad material, wherein this second substrate has more conductive pad and several second conductive part under several second substrate, under this second substrate, conductive pad is the lower surface being revealed in this second substrate, described second conductive part is positioned under described second substrate on conductive pad, and the described end face of described first conductive part of described second conductive part contact; And
G () carries out a heating steps, make described second conductive part and described first conductive part melting and form several interior Connection Element, and this clad material is solidified into the C stage.
16., as the semiconductor technology of claim 15, is characterized in that, in step (a), this first substrate has more conductive pad under a lower surface and several first substrate, and under described first substrate, conductive pad is revealed in this first substrate lower surface; More comprise after step (g):
H () forms several lower soldered ball under described first substrate on conductive pad;
I () carries out reflow; And
J () cuts, to form several semiconductor package.
17. as the semiconductor technology of claim 15, and it is characterized in that, in this step (a), this first conductive part is spherical, and has Radius R; In this step (b), this first conductive part after leveling has one second height h2, wherein R < h2 < 2R, and this end face has Breadth Maximum W, wherein a W<2.2R.
18. as the semiconductor technology of claim 15, and it is characterized in that, step (d) is pressing or prints this clad material in the upper surface of this first substrate.
19. as the semiconductor technology of claim 15, and it is characterized in that, in step (g), the clad material of this solidification has several holding tank to hold described interior Connection Element, and the shape of described holding tank defined by described interior Connection Element.
20., as the semiconductor technology of claim 15, is characterized in that, in step (g), this interior Connection Element comprises a top and a bottom, this top formed by this second conductive part haply, and this bottom formed by this first conductive part haply, and this bottom has a shoulder.
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| CN201310645713.9A CN104701270B (en) | 2013-12-04 | 2013-12-04 | Semiconductor package and semiconductor technology |
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| US9679836B2 (en) * | 2011-11-16 | 2017-06-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structures and methods for forming the same |
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| CN104701270B (en) | 2017-12-19 |
| CN107818959B (en) | 2021-09-03 |
| CN107818959A (en) | 2018-03-20 |
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